ST STM32F405 Reference Manual page 1739

RM0090
Date Version
17-May-2016 12
Table 315. Document revision history (continued)
Embedded Flash memory interface
Removed note related to boot from Bank 2 in
Updated notes in Section 3.7.3: Read protection
Changed number of LATENCY bits in
(FLASH_ACR) for STM32F42xxx and STM32F43xxx
In Table 9: 1 Mbyte dual bank Flash memory organization (STM32F42xxx and
STM32F43xxx): updated sector 19 size and option bytes (bank 2) address range.
Power control (PWR)
Removed reference to low-power mode in
STM32F42xxx and STM32F43xxx,
and STM32F43xxx)
STM32F43xxx).
Analog-to-digital converter (ADC)
Added note related to ADC_HTR and ADC_LTR register programming in
Section 13.13.7: ADC watchdog higher threshold register (ADC_HTR)
Section 13.13.8: ADC watchdog lower threshold register
Chrom-Art Accelerator™ controller (DMA2D)
Updated Section 11.3.12: DMA2D transfer control (start, suspend, abort and
completion).
Section 11.5.8: DMA2D foreground PFC control register
updated START bit access type
Section 11.5.10: DMA2D background PFC control register
updated START bit access and description.
LCD-TFT controller (LTDC)
Updated Section 16.3.2: LTDC reset and
Modified LCD_DE description in
Modified Section 16.7.15: LTDC Layerx Window Horizontal Position Configuration
Register (LTDC_LxWHPCR) (where x=1..2)
Window Vertical Position Configuration Register (LTDC_LxWVPCR) (where
x=1..2).
General-purpose timers (TIM2 to TIM5)
Updated Section 18.4.11: TIMx prescaler
General-purpose timers (TIM9 to TIM14)
Added OPM bit in Section 19.5.1: TIM10/11/13/14 control register 1
Updated Section 19.4.9: TIM9/12 prescaler (TIMx_PSC)
TIM10/11/13/14 prescaler
RM0090 Rev 18
Changes
Section 3.9.2: Flash access control register
Section 5.1.4: Voltage regulator for
Section : Entering Stop mode (STM32F42xxx
and Section : Exiting Stop mode (STM32F42xxx and
clocks.
Table 89: LCD-TFT pins and signal
(TIMx_PSC).
(TIMx_PSC).
Revision history
Section 2.4: Boot configuration.
(RDP).
(ADC_LTR).
(DMA2D_FGPFCCR):
(DMA2D_BGPFCCR):
and Section 16.7.16: LTDC Layerx
(TIMx_CR1).
and Section 19.5.8:
and
interface.
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