ST STM32F405 Reference Manual page 1433

RM0090
OTG_HS_Host periodic transmit FIFO/queue status register
(OTG_HS_HPTXSTS)
Address offset: 0x410
Reset value: 0x0008 0100
This read-only register contains the free space information for the periodic TxFIFO and the
periodic transmit request queue.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PTXQTOP
r r r r r r r
Bits 31:24 PTXQTOP: Top of the periodic transmit request queue
Bits 23:16 PTXQSAV: Periodic transmit request queue space available
Bits 15:0 PTXFSAVL: Periodic transmit data FIFO space available
PTXQSAV
r r r r r r
This indicates the entry in the periodic Tx request queue that is currently being processed by
the MAC.
This register is used for debugging.
Bit [31]: Odd/Even frame
– 0: send in even (micro) frame
– 1: send in odd (micro) frame
Bits [30:27]: Channel/endpoint number
Bits [26:25]: Type
– 00: IN/OUT
– 01: Zero-length packet
– 11: Disable channel command
Bit [24]: Terminate (last entry for the selected channel/endpoint)
Indicates the number of free locations available to be written in the periodic transmit request
queue. This queue holds both IN and OUT requests.
00: Periodic transmit request queue is full
01: dx1 location available
10: dx2 locations available
bxn: dxn locations available (0 ≤ dxn ≤ PTXFD)
Others: Reserved
Indicates the number of free locations available to be written to in the periodic TxFIFO.
Values are in terms of 32-bit words
0000: Periodic TxFIFO is full
0001: dx1 word available
0010: dx2 words available
bxn: dxn words available (where 0 ≤ dxn ≤ dx512)
Others: Reserved
USB on-the-go high-speed (OTG_HS)
r r r r r r r
RM0090 Rev 18
9 8 7 6 5
PTXFSAVL
r r r r r r r
4 3 2 1 0
r r r r r
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