ST STM32F405 Reference Manual page 1677

RM0090
Bits 3:0 TMRD[3:0]: Load Mode Register to Active
These bits define the delay between a Load Mode Register command and an Active or Refresh
command in number of memory clock cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: If two SDRAM devices are connected, all the accesses performed simultaneously to both
devices by the Command Mode register (Load Mode Register and Self-refresh commands)
are issued using the timing parameters configured for Bank 1 (TMRD, TRAS and TXSR
timings) in the FMC_SDTR1 register.
The TRP and TRC timings are only configured in the FMC_SDTR1 register. If two SDRAM
devices are used, the TRP and TRC timings must be programmed with the timings of the
slowest device.
SDRAM Command Mode register (FMC_SDCMR)
Address offset: 0x150
Reset value: 0x0000 0000
This register contains the command issued when the SDRAM device is accessed. This
register is used to initialize the SDRAM device, and to activate the Self-refresh and the
Power-down modes. As soon as the MODE field is written, the command will be issued only
to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register
is the same for both SDRAM banks.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:22 Reserved, must be kept at reset value
Bits 21:9 MRD[11:0]: Mode Register definition
This 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using
the Load Mode Register command.
Bits 8:5 NRFS[3:0]: Number of Auto-refresh
These bits define the number of consecutive Auto-refresh commands issued when MODE = '011'.
0000: 1 Auto-refresh cycle
0001: 2 Auto-refresh cycles
....
1110: 15 Auto-refresh cycles
1111: Reserved
Bit 4 CTB1: Command Target Bank 1
This bit indicates whether the command will be issued to SDRAM Bank 1 or not.
0: Command not issued to SDRAM Bank 1
1: Command issued to SDRAM Bank 1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RM0090 Rev 18
Flexible memory controller (FMC)
9 8 7 6 5 4
rw rw w
3 2 1 0
w w w w
1677/1749
1682