ST STM32F405 Reference Manual page 1728

Revision history
Date Version
03-Feb-2014
(continued)
1728/1749
Table 315. Document revision history (continued)
TIM9 to 14:
Updated note related to IC1F in
mode register 1
RTC:
Updated Section 26.3.11: RTC smooth digital
Changed ALRBIE to ALRBE (bit 9) in
(RTC_CR).
I2C:
Introduced Sm (standard mode) and Fm (fast mode) acronyms.
FSMC:
Updated BUSTURN definition in
6
FMC:
Added Mobile LPSDR SDRAM.
Updated Section : SDRAM initialization
and Figure 476: NAND Flash/PC Card controller waveforms for common memory
access.
Updated Section : SRAM/NOR-Flash chip-select control registers 1..4
(FMC_BCR1..4),
(FMC_BTR1..4),
(FMC_BWTR1..4),
Section : SDRAM Refresh Timer register
Removed mention "default valeur after reset" in
timing register 2..4
registers 2..4 (FMC_PATT2..4), and
(FMC_PIO4).
Updated BUSTURN definition in
Updated REV_ID bits in
Changes
Section 19.5.5: TIM10/11/13/14 capture/compare
(TIMx_CCMR1).
Section 26.6.3: RTC control register
Table 245: FSMC_BTRx bit
and
Section : SRAM/NOR-Flash chip-select timing registers 1..4
Section : SRAM/NOR-Flash write timing registers 1..4
Section : SDRAM Timing registers 1,2 (FMC_SDTR1,2)
(FMC_PMEM2..4), Section : Attribute memory space timing
Section : I/O space timing register 4
Table 288: FMC_BTRx bit
Section 38.6.1: MCU device ID
RM0090 Rev 18
calibration.
fields.
Section : SDRAM controller read cycle
(FMC_SDRTR).
Section : Common memory space
fields.
code..
RM0090
and