Table 240. Fsmc_Bcrx Bit Fields; Table 241. Fsmc_Btrx Bit Fields - ST STM32F405 Reference Manual

Flexible static memory controller (FSMC)
Bit No.
31-21
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
WAIT management in asynchronous accesses
If the asynchronous memory asserts a WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.
1568/1749

Table 240. FSMC_BCRx bit fields

Bit name
Reserved 0x000
CBURSTRW 0x0 (no effect on asynchronous mode)
CPSIZE 0x0 (no effect on asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
ASYNCWAIT
0.
EXTMOD 0x0
WAITEN 0x0 (no effect on asynchronous mode)
WREN As needed
WAITCFG Don't care
WRAPMOD 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN 0x1
MWID As needed
MTYP[0:1] 0x2 (NOR Flash memory)
MUXEN 0x1
MBKEN 0x1

Table 241. FSMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles for
DATAST
read accesses and DATAST+1 HCLK cycles for write accesses).
ADDHLD Duration of the middle phase of the access (ADDHLD HCLK cycles).
Duration of the first access phase (ADDSET HCLK cycles).
ADDSET[3:0]
Minimum value for ADDSET is 1.
RM0090 Rev 18
Value to set
Value to set
RM0090