Figure 458. Mode1 Read Access Waveforms; Figure 459. Mode1 Write Access Waveforms - ST STM32F405 Reference Manual

Flexible memory controller (FMC)
Mode 1 - SRAM/PSRAM (CRAM)
The next figures show the read and write transactions for the supported modes followed by
the required configuration of FMC _BCRx, and FMC_BTRx/FMC_BWTRx registers.
NBL[3:0]
NBL[3:0]
D[31:0]
1618/1749

Figure 458. Mode1 read access waveforms

A[25:0]
NEx
NOE
NWE
High
D[31:0]

Figure 459. Mode1 write access waveforms

A[25:0]
NEx
NOE
NWE
HCLK cycles
Memory transaction
ADDSET
HCLK cycles
Memory transaction
data driven by FSMC
ADDSET
RM0090 Rev 18
data driven
by memory
DATAST
HCLK cycles
1HCLK
(DATAST + 1)
HCLK cycles
RM0090
MS30452V1
MS30453V1