ST STM32F405 Reference Manual page 1706

Debug support (DBG)
Bit 20:13 Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted
0: The independent watchdog counter clock continues even if the core is halted
1: The independent watchdog counter clock is stopped when the core is halted
Bit 11 DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted
0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted
Bit 10 DBG_RTC_STOP: RTC stopped when Core is halted
0: The RTC counter clock continues even if the core is halted
1: The RTC counter clock is stopped when the core is halted
Bit 9 Reserved, must be kept at reset value.
Bits 8:0 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=2..7, 12..14)
0: The clock of the involved timer counter is fed even if the core is halted
1: The clock of the involved timer counter is stopped and the outputs are disabled when the
core is halted
38.16.5 Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ)
The DBGMCU_APB2_FZ register is used to configure the MCU under Debug. It concerns
APB2 peripherals.
This register is mapped on the external PPB bus at address 0xE004 200C
It is asynchronously reset by the POR (and not the system reset). It can be written by the
debugger under system reset.
Address: 0xE004 200C
Only 32-bit access is supported.
POR: 0x0000 0000 (not reset by system reset)
31 30 29 28
15 14 13 12
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:16 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=9..11)
0: The clock of the involved timer counter is fed even if the core is halted
1: The clock of the involved timer counter is stopped and the outputs are disabled when the
core is halted
1706/1749
27 26 25 24
Reserved
11 10 9 8
Reserved
RM0090 Rev 18
23 22 21 20
7 6 5 4
19 18 17
DBG_TIM11 DBG_TIM10
_STOP _STOP
rw rw
3 2 1
DBG_TIM8_
STOP
rw
RM0090
16
DBG_TIM9_
STOP
rw
0
DBG_TIM1_
STOP
rw