ST STM32F405 Reference Manual page 1720

Revision history
Date Version
19-Oct-2012
(continued)
1720/1749
Table 315. Document revision history (continued)
SDIO:
Updated value and description for bits [45:40] and [7:1] in
Updated value at bits [45:40] in
CAN:
Updated Figure 335: Dual CAN block
Modified definition of CAN2SB bits in
(CAN_FMR).
Added register access in
ETHERNET:
Updated standard for precision networked clock synchronization in
Ethernet introduction
Updated CR bit definition in
(ETH_MACMIIAR).
Replace RTPR by PM bit in
USB OTG FS
Updated remote wakeup signaling bit and the resume
2
interrupt in Section : Suspended
Added peripheral register access in
registerss.
Updated INEPTXSA description in OTG_FS_DIEPTXFx.
Changed PHYSEL from bit 7 to bit 6 of the OTG_FS_GUSBCFG
register.
USB OTG HS
Updated remote wakeup signaling bit and the resume
interrupt in Section : Suspended
Added peripheral register access in
registers.
Updated OTG_HS_CID reset value.
Updated INEPTXSA description in OTG_HS_DIEPTXFx.
Updated FSLSPCS for LS host mode, added PHYSEL in
configuration register
Renamed PHYSEL into PHSEL and changed from bit 7 to bit 6 of
the OTG_HS_GUSBCFG register.
Updated OTG_HS_DIEPEACHMSK1 and OTG_HS_DOEPEACHMSK1 reset
values.
Changes
Table 178: R5
diagram.
Section : CAN filter master register
Section 32.9: CAN registers
and Section 33.2.1: MAC core
Section : Ethernet MAC MII address register
Table 192: Source address
state.
Section 34.16: OTG_FS control and status
state.
Section 35.12: OTG_HS control and status
(OTG_HS_HCFG).
RM0090 Rev 18
Table 176: R4
response.
Section 33.1:
features.
filtering.
Section : OTG_HS host
RM0090
response.