Table 264. Non-Multiplexed I/O Nor Flash Memory; Table 265. 16-Bit Multiplexed I/O Nor Flash Memory; Table 266. Non-Multiplexed I/Os Psram/Sram - ST STM32F405 Reference Manual

Flexible memory controller (FMC)
NOR Flash memory, non-multiplexed I/Os
The maximum capacity is 512 Mbits (26 address lines).
NOR Flash memory, 16-bit multiplexed I/Os
FMC signal name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT
The maximum capacity is 512 Mbits.
PSRAM/SRAM, non-multiplexed I/Os
FMC signal name
CLK
A[25:0]
D[31:0]
1614/1749

Table 264. Non-multiplexed I/O NOR Flash memory

FMC signal name
CLK
A[25:0]
D[31:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT

Table 265. 16-bit multiplexed I/O NOR Flash memory

I/O
O
O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
I/O
O
O
O
Latch enable (this signal is called address valid, NADV, by some NOR
O
I

Table 266. Non-multiplexed I/Os PSRAM/SRAM

I/O
O
O
I/O
I/O
O
O
I/O
O
O
O
Latch enable (this signal is called address
O
valid, NADV, by some NOR Flash devices)
I NOR Flash wait input signal to the FMC
Clock (for synchronous access)
A[15:0] and data D[15:0] are multiplexed on the databus)
Chip Select, x = 1..4
Output enable
Flash devices)
NOR Flash wait input signal to the FMC
Clock (only for PSRAM synchronous access)
Address bus
Data bidirectional bus
RM0090 Rev 18
Function
Clock (for synchronous access)
Address bus
Bidirectional data bus
Chip Select, x = 1..4
Output enable
Write enable
Function
Address bus
Write enable
Function
RM0090