Table 295. Ecc Result Relevant Bits - ST STM32F405 Reference Manual

Flexible memory controller (FMC)
ECC result registers 2/3 (FMC_ECCR2/3)
Address offset: 0x54 + 0x20 * (x – 1), x = 2 or 3
Reset value: 0x0000 0000
These registers contain the current error correction code value computed by the ECC
computation modules of the FMC controller (one module per NAND Flash memory bank).
When the CPU reads the data from a NAND Flash memory page at the correct address
(refer to
memory), the data read/written from/to the NAND Flash memory are processed
automatically by the ECC computation module. When X byte have been read (according to
the ECCPS field in the FMC_PCRx registers), the CPU must read the computed ECC value
from the FMC_ECCx registers. It then verifies if these computed parity data are the same as
the parity value recorded in the spare area, to determine whether a page is valid, and, to
correct it otherwise. The FMC_ECCRx registers should be cleared after being read by
setting the ECCEN bit to '0'. To compute a new data block, the ECCEN bit must be set to '1'.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:0 ECC[31:0]: ECC result
This field contains the value computed by the ECC computation logic.
contents of these bit fields.
ECCPS[2:0]
1662/1749
Section 37.6.6: Computation of the error correction code (ECC) in NAND Flash

Table 295. ECC result relevant bits

000
001
010
011
100
101
ECC[31:0]
r
Page size in byte
256
512
1024
2048
4096
8192
RM0090 Rev 18
9 8 7 6 5 4 3
Table 295 describes the
ECC bits
ECC[21:0]
ECC[23:0]
ECC[25:0]
ECC[27:0]
ECC[29:0]
ECC[31:0]
RM0090
2 1 0