Table 279. Fmc_Bwtrx Bit Fields; Figure 467. Moded Read Access Waveforms - ST STM32F405 Reference Manual

Flexible memory controller (FMC)
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Mode D - asynchronous access with extended address
1628/1749

Table 279. FMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x2
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) for
DATAST
write accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for write
ADDSET[3:0]
accesses. Minimum value for ADDSET is 0.

Figure 467. ModeD read access waveforms

A[25:0]
NADV
NEx
NOE
NWE
High
D[31:0]
ADDSET
HCLK cycles
RM0090 Rev 18
Value to set
Memory transaction
data driven
by memory
DATAST
HCLK cycles
ADDHLD
HCLK cycles
RM0090
MS30461V1