ST STM32F405 Reference Manual page 1441

RM0090
OTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx)
(x = 0..11, where x = Channel_number)
Address offset: 0x50C + 0x20 * x
Reset value: 0x0000 0000
This register reflects the mask for each channel status described in the previous section.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 DTERRM: Data toggle error mask
Bit 9 FRMORM: Frame overrun mask
Bit 8 BBERRM: Babble error mask
Bit 7 TXERRM: Transaction error mask
Bit 6 NYET: response received interrupt mask
Bit 5 ACKM: ACK response received/transmitted interrupt mask
Bit 4 NAKM: NAK response received interrupt mask
Bit 3 STALLM: STALL response received interrupt mask
Reserved
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
USB on-the-go high-speed (OTG_HS)
RM0090 Rev 18
9 8 7 6 5 4
rw rw rw rw rw rw rw rw rw rw rw
3 2 1 0
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