Figure 456. Fmc Block Diagram - ST STM32F405 Reference Manual

Flexible memory controller (FMC)
FMC interrupts to NVIC
From clock
controller
HCLK
37.3 AHB interface
The AHB slave interface allows internal CPUs and other bus master peripherals to access
the external memories.
AHB transactions are translated into the external device protocol. In particular, if the
selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split
into consecutive 16- or 8-bit accesses. The FMC Chip Select (FMC_NEx) does not toggle
between consecutive accesses except when performing accesses in mode D with the
extended mode enabled.
1604/1749

Figure 456. FMC block diagram

NOR/PSRAM
memory
controller
Configuration
registers
NAND/PC Card
memory
controller
SDRAM
controller
FMC_NL(or NADV)
FMC_CLK
FMC_NBL[3:0]
FMC_A[25:0]
FMC_D[ 31:0]
FMC_NE[4:1]
FMC_NOE
FMC_NWE
FMC_NWAIT
FMC_NCE[3:2]
FMC_INT[3:2]
FMC_INTR
FMC_NCE4_1
FMC_NCE4_2
FMC_NIORD
FMC_NIOWR
FMC_NREG
FMC_CD
FMC_SDCLK
FMC_SDNWE
FMC_SDCKE[1:0]
FMC_SDNE[1:0]
FMC_NRAS
FMC_NCAS
RM0090 Rev 18
RM0090
NOR/PSRAM
signals
SRAM/PSRAM/SDRAM
Shared signals
Shared
signals
NOR/PSRAM/SRAM
Shared signals
NAND
signals
PC Card
signals
SDRAM
signals
MS30443V5