Table 238. Fsmc_Btrx Bit Fields; Table 239. Fsmc_Bwtrx Bit Fields - ST STM32F405 Reference Manual

Flexible static memory controller (FSMC)
Bit No.
1
0
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
1566/1749
Table 237. FSMC_BCRx bit fields (continued)
Bit name
MUXEN
MBKEN

Table 238. FSMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x3
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) for
DATAST
read accesses.
Duration of the middle phase of the read access (ADDHLD HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for read
ADDSET[3:0]
accesses. Minimum value for ADDSET is 0.

Table 239. FSMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x3
DATLAT 0x0
CLKDIV 0x0
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles) for
DATAST
write accesses
Duration of the middle phase of the write access (ADDHLD HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET+1 HCLK cycles) for
ADDSET[3:0]
write accesses. Minimum value for ADDSET is 0.
RM0090 Rev 18
0x0
0x1
Value to set
Value to set
Value to set
RM0090