Table 257. Nand Bank Selection; Table 258. Sdram Bank Selection; Table 259. Sdram Address Mapping - ST STM32F405 Reference Manual

RM0090
Section name
Address section
Command section
Data section
The application software uses the 3 sections to access the NAND Flash memory:
•
To send a command to NAND Flash memory, the software must write the command
value to any memory location in the command section.
• To specify the NAND Flash address that must be read or written, the software
must write the address value to any memory location in the address section. Since an
address can be 4 or 5 byte long (depending on the actual memory size), several
consecutive write operations to the address section are required to specify the full
address.
•
To read or write data, the software reads or writes the data from/to any memory
location in the data section.
Since the NAND Flash memory automatically increments addresses, there is no need to
increment the address of the data section to access consecutive memory locations.
37.4.3 SDRAM address mapping
The HADDR[28] bit (internal AHB address line 28) is used to select one of the two memory
banks as indicated in
HADDR[28]
The following table shows SDRAM mapping for an 13-bit row ,a 11-bit column and 4 internal
bank configurations.
Memory width
8-bit
16-bit
32-bit

Table 257. NAND bank selection

Table 258.

Table 258. SDRAM bank selection

Selected bank
0 SDRAM Bank1
1 SDRAM Bank2

Table 259. SDRAM address mapping

(1)
Internal bank
HADDR[25:24]
HADDR[26:25]
HADDR[27:26]
HADDR[17:16]
1X
01
00
Control register
FMC_SDCR1
FMC_SDCR2
Row address
HADDR[23:11]
HADDR[24:12]
HADDR[25:13]
RM0090 Rev 18
Flexible memory controller (FMC)
Address range
0x020000-0x03FFFF
0x010000-0x01FFFF
0x000000-0x0FFFF
Timing register
FMC_SDTR1
FMC_SDTR2
Column
memory capacity
(2)
address
HADDR[10:0]
HADDR[11:1]
4 x 8K x 2K x 2
HADDR[12:2]
4 x 8K x 2K x 4
Maximum
(Mbyte)
64 Mbyte:
4 x 8K x 2K
128 Mbyte:
256 Mbyte:
1609/1749
1682