Table 206. Otg_Hs Input/Output Pins; Figure 410. Usb Otg Interface Block Diagram - ST STM32F405 Reference Manual

USB on-the-go high-speed (OTG_HS)
CPU
AHB
Memory
master
interface
AHB
Peripheral 1
slave
interface
Peripheral 2
1. The USB DMA cannot directly address the internal Flash memory.
35.3.1 OTG pins
Signal name
OTG_HS_DP
OTG_HS_DM
OTG_HS_ID
OTG_HS_VBUS
OTG_HS_SOF
OTG_HS_ULPI_CK
OTG_HS_ULPI_DIR
OTG_HS_ULPI_STP
OTG_HS_ULPI_NXT
OTG_HS_ULPI_D[0..7]
35.3.2 High-speed OTG PHY
The USB OTG HS core embeds an ULPI interface to connect an external HS phy.
1384/1749

Figure 410. USB OTG interface block diagram

serial
OTG_HS
(USB OTG HS core)
Interrupt: async wakeup
Interrupt: EP1 out
Interrupt: EP1 in
Interrupt: global
Data FIFO
Single-port RAM
(SPRAM)

Table 206. OTG_HS input/output pins

Signal type
Digital input/output USB OTG D+ line
Digital input/output USB OTG D- line
Digital input
Analog input
Digital output
Digital input
Digital input
Digital output
Digital input
Digital input/output USB OTG ULPI 8-bit bi-directional data bus
RM0090 Rev 18
OTG FS PHY
transceiver
OTG detections
EXTI EXTI
NVIC
ULPI interface (12 pins)
Description
USB OTG ID
USB OTG VBUS
USB OTG Start Of Frame (visibility)
USB OTG ULPI clock
USB OTG ULPI data bus direction control
USB OTG ULPI data stream stop
USB OTG ULPI next data stream request
RM0090
OTG_HS_DP
OTG_HS_DM
OTG_HS_ID
OTG_HS_VBUS
ULPI_CK;
ULPI_DIR;
ULPI_STP;
ULPI_NXT;
ULPI_D0-7
USB2.0 (D+/D-)
ULPI PHY
(external
component)
OTG_HS_SOF
MSv43325V1