Table 244. Fsmc_Bcrx Bit Fields; Figure 453. Synchronous Multiplexed Write Mode - Psram (Cram) - ST STM32F405 Reference Manual

RM0090
HCLK
CLK
A[25:16]
NEx
Hi-Z
NOE
NWE
NADV
NWAIT
(WAITCFG = 0)
A/D[15:0]
1 clock 1 clock
1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. NWAIT polarity is set to 0.
3. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Bit No.
31-20
19
18-16
15
14
13
12
11
10

Figure 453. Synchronous multiplexed write mode - PSRAM (CRAM)

Memory transaction = burst of 2 half words
addr[25:16]
(DATLAT + 2)
CLK cycles
Addr[15:0]

Table 244. FSMC_BCRx bit fields

Bit name
Reserved 0x000
CBURSTRW 0x1
CPSIZE As needed (0x1 for CRAM 1.5)
ASCYCWAIT 0x0
EXTMOD 0x0
WAITEN Set to 1 if the memory supports this feature, otherwise keep at 0.
WREN 0x1
WAITCFG 0x0
WRAPMOD 0x0
Flexible static memory controller (FSMC)
data
RM0090 Rev 18
inserted wait state
data
Value to set
ai14731f
1575/1749
1601