ST STM32F405 Reference Manual page 1448

USB on-the-go high-speed (OTG_HS)
OTG_HS device IN endpoint common interrupt mask register
(OTG_HS_DIEPMSK)
Address offset: 0x810
Reset value: 0x0000 0000
This register works with each of the Device IN endpoint interrupt (OTG_HS_DIEPINTx)
registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt
for a specific status in the OTG_HS_DIEPINTx register can be masked by writing to the
corresponding bit in this register. Status bits are masked by default.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:10 Reserved, must be kept at reset value.
Bit 13 NAKM: NAK interrupt mask
Bits 12:9 Reserved, must be kept at reset value.
Bit 8 TXFURM: FIFO underrun mask
Bit 7 Reserved, must be kept at reset value.
Bit 6 INEPNEM: IN endpoint NAK effective mask
Bit 5 INEPNMM: IN token received with EP mismatch mask
Bit 4 ITTXFEMSK: IN token received when TxFIFO empty mask
Bit 3 TOM: Timeout condition mask (nonisochronous endpoints)
1448/1749
Reserved
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
Reserved
rw
RM0090 Rev 18
9 8 7 6 5 4 3
rw rw rw rw rw rw rw rw
RM0090
2 1 0