Figure 473. Wait Configuration Waveforms; Figure 474. Synchronous Multiplexed Read Mode Waveforms - Nor, Psram (Cram) - ST STM32F405 Reference Manual

Flexible memory controller (FMC)
The FMC supports both NOR Flash wait state configurations, for each Chip Select, thanks
to the WAITCFG bit in the FMC_BCRx registers (x = 0..3).
A[25:16]
NWAIT
(WAITCFG = 0)
NWAIT
(WAITCFG = 1)
A/D[15:0]

Figure 474. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)

(WAITCFG=
1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access,
1636/1749

Figure 473. Wait configuration waveforms

HCLK
CLK
addr[25:16]
NADV
addr[15:0]
HCLK
CLK
A[25:16] addr[25:16]
NEx
NOE
High
NWE
NADV
NWAIT
0)
A/D[15:0]
Addr[15:0]
1 clock 1 clock
cycle cycle
Memory transaction = burst of 4 half words
data data
Memory transaction = burst of 4 half words
(DATLAT + 2)
CLK cycles
data
Data strobes
RM0090 Rev 18
inserted wait state
data
inserted wait state
data data data
Data strobes
RM0090
ai15798c
ai17723f