ST STM32F405 Reference Manual page 1727

RM0090
Date Version
03-Feb-2014
Table 315. Document revision history (continued)
Added note related to
in Section 3.5.1: Relation between CPU clock frequency and Flash
memory read
Updated maximum CPU frequency in
memory accelerator (ART
PWR:
Updated Run mode/ over-drive mode in
STM32F42xxx and
RCC for STM32F42/43xx:
Changed APB1/2 and AHB maximum frequencies.xw
GPIOs:
Updated Figure 27: Selecting an alternate function on STM32F42xxx and
STM32F43xxx.
DMA:
Updated Section 10.3.7: Pointer incrementation
burst transfers..
6
INTERRUPTS AND EVENTS:
Updated Table 62: Vector table for STM32F42xxx and
ADC:
Updated Section 13.3.10: Discontinuous mode/Section : Regular
DCMI:
Updated Section 15.5.2: DCMI physical
LTDC:
Updated resolution in note below
TIM1 and 8:
Added note related to IC1F in
mode register 1
TIM2 to 5:
Updated note related to IC1F in
register 1 (TIMx_CCMR1).
Changes
over-drive mode unavailable in 1.8 to 2.1 V V
time.
Accelerator™).
STM32F43xxx.
Figure 82: LCD-TFT Synchronous
Section 17.4.7: TIM1 and TIM8 capture/compare
(TIMx_CCMR1).
Section 18.4.7: TIMx capture/compare mode
RM0090 Rev 18
Section 3.5.2: Adaptive real-time
Section 5.1.4: Voltage regulator for
and Section 10.3.11: Single and
STM32F43xxx.
interface.
Revision history
ge
DD ran
group.
timings.
1727/1749
1743