ST STM32F405 Reference Manual page 1660

Flexible memory controller (FMC)
Bits 23:16 ATTHOLD[7:0]: Attribute memory x hold time
Bits 15:8 ATTWAIT[7:0]: Attribute memory x wait time
Bits 7:0 ATTSET[7:0]: Attribute memory x setup time
I/O space timing register 4 (FMC_PIO4)
Address offset: 0xB0
Reset value: 0xFCFCFCFC
The FMC_PIO4 read/write registers contain the timing information used to access the I/O
space of the 16-bit PC Card/CompactFlash.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IOHIZ[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1660/1749
For PC Card/NAND Flash read accesses to attribute memory space on socket x, these bits
define the number of HCLK clock cycles (HCLK +2) clock cycles during which the address is
held after the command is deasserted (NWE, NOE).
For PC Card/NAND Flash write accesses to attribute memory space on socket x, these bits
define the number of HCLK clock cycles during which the data are held after the command
is deasserted (NWE, NOE).
0000 0000: Reserved
0000 0001: 1 HCLK cycle for write access, 3 HCLK cycles for read accesses
1111 1110: 254 HCLK cycle for write access, 256 HCLK cycles for read accesses
1111 1111: Reserved.
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for PC Card/NAND Flash read or write access to attribute memory space on socket x.
The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at
the end of the programmed value of HCLK:
0000 0000: reserved
0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
1111 1110: 255 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
1111 1111: Reserved
Defines the number of HCLK (+1) clock cycles to set up address before the command
assertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory
space on socket x:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: Reserved
IOHOLD[7:0] IOWAIT[7:0]
RM0090 Rev 18
9 8 7 6 5 4 3
IOSET[7:0]
RM0090
2 1 0