Table 226. Fsmc_Bcrx Bit Fields; Figure 437. Mode1 Write Accesses - ST STM32F405 Reference Manual

RM0090
The one HCLK cycle at the end of the write transaction helps guarantee the address and
data hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the
DATAST value must be greater than zero (DATAST > 0).
Bit number
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2

Figure 437. Mode1 write accesses

A[25:0]
NBL[1:0]
NEx
NOE
NWE
D[15:0]

Table 226. FSMC_BCRx bit fields

Bit name
Reserved 0x000
CBURSTRW 0x0 (no effect on asynchronous mode)
CPSIZE 0x0 (no effect on asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x0
WAITEN 0x0 (no effect on asynchronous mode)
WREN As needed
WAITCFG Don't care
WRAPMOD 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN Don't care
MWID As needed
MTYP[0:1] As needed, exclude 0x2 (NOR Flash)
RM0090 Rev 18
Flexible static memory controller (FSMC)
Memory transaction
ADDSET
HCLK cycles
Value to set
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
ai15558
1555/1749
1601