ST STM32F405 Reference Manual page 1731

RM0090
Date Version
14-Oct-2014
Table 315. Document revision history (continued)
Memory and bus architecture:
Updated Table 3: Memory mapping vs. Boot mode/physical remap in
STM32F405xx/07xx and STM32F415xx/17xx
Boot mode/physical remap in STM32F42xxx and
RCC (STM32F40/41xx) and RCC (STM32F42/43xx):
Removed all references to Flash programming manual. Changed
RCC_AHB1LPENR, RCC_APB1LPENR, RCC_APB2LPENR, RCC_PLLI2SCFGR
and RCC_APB2LPENR reset values.
Updated access type to "r" for bits 24 to 31 in RCC_CSR.
GPIOs:
Updated Figure 27: Selecting an alternate function on STM32F42xxx and
STM32F43xxx.
IWDG
Update note in
CRYPTO and HASH
Removed STM32F405/407xx and STM32F42xx from the whole sections.
8 Removed STM32F405/407xx and STM32F42xx from the whole section.
TIM10/11/13/14
Added TIMx_DIER description in
ETHERNET:
Updated Table 187: Clock
USB OTG FS:
Removed TRDT formula in
Table 203: TRDT
USB OTG HS:
Removed TRDT formula in
Table 213: TRDT
FSMC:
Updated EXTMOD definition in
registers 1..4 (FSMC_BCR1..4).
Updated ADDSET definition in
registers 1..4 (FSMC_BTR1..4)
registers 1..4 (FSMC_BWTR1..4).
Changes
Table 107: Min/max IWDG timeout period (in ms) at 32 kHz
Section 19.5: TIM10/11/13/14
range.
Section 34.17.7: Worst case response time
values.
Section 35.13.8: Worst case response time
values.
Section : SRAM/NOR-Flash chip-select control
Section : SRAM/NOR-Flash chip-select timing
and Section : SRAM/NOR-Flash write timing
RM0090 Rev 18
Revision history
and Table 4: Memory mapping vs.
STM32F43xxx.
registers.
(LSI).
and added
and added
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