Table 227. Fsmc_Btrx Bit Fields; Figure 438. Modea Read Accesses - ST STM32F405 Reference Manual

Flexible static memory controller (FSMC)
Bit number
1
0
Bit number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Mode A - SRAM/PSRAM (CRAM) OE toggling
1. NBL[1:0] are driven low during read access.
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Table 226. FSMC_BCRx bit fields (continued)
Bit name
MUXE 0x0
MBKEN 0x1

Table 227. FSMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD Don't care
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
DATAST
write accesses, DATAST HCLK cycles for read accesses).
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles).
ADDSET[3:0]
Minimum value for ADDSET is 0.

Figure 438. ModeA read accesses

A[25:0]
NBL[1:0]
NEx
NOE
NWE
High
D[15:0]
RM0090 Rev 18
Value to set
Value to set
Memory transaction
ADDSET DATAST
HCLK cycles HCLK cycles
RM0090
data driven
by memory
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