ST STM32F405 Reference Manual page 1684

Debug support (DBG)
The Arm
comprised of:
•
SWJ-DP: Serial wire / JTAG debug port
•
AHP-AP: AHB access
•
ITM: Instrumentation trace macrocell
•
FPB: Flash patch breakpoint
•
DWT: Data watchpoint trigger
•
TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
•
ETM: Embedded Trace Macrocell (available on larger packages, where the
corresponding pins are mapped)
It also includes debug features dedicated to the STM32F4xx:
•
Flexible debug pinout assignment
•
MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the Arm
core, refer to the Cortex
CoreSight Design Kit-r0p1 TRM (see
38.2 Reference Arm
•
Cortex
(see Related documents on page 1)
•
Arm
• Arm
38.3 SWJ debug port (serial wire and JTAG)
The core of the STM32F4xx integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an
®
Arm standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-
DP (2-pin) interface.
•
The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the
AHP-AP port.
•
The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
1684/1749
® ®
Cortex -M4 with FPU core provides integrated on-chip debug support. It is
ort
p
®
-M4 with FPU -r0p1 Technical Reference Manual and to the
®
documentation
®
-M4 with FPU r0p1 Technical Reference Manual (TRM)
®
Debug Interface V5
®
CoreSight Design Kit revision r0p1 Technical Reference Manual
Section 38.2).
RM0090 Rev 18
RM0090
® ®
Cortex -M4 with FPU