ST STM32F405 Reference Manual page 1681

RM0090
Offset Register
0x10C FMC_BWTR2 Res.
0x104 FMC_BWTR3 Res.
0x10C FMC_BWTR4 Res.
0x60 FMC_PCR2
0x80 FMC_PCR3
0xA0 FMC_PCR4
0x64 FMC_SR2
0x84 FMC_SR3
0xA4 FMC_SR4
0x68 FMC_PMEM2
0x88 FMC_PMEM3
0xA8 FMC_PMEM4
0x6C FMC_PATT2
0x8C FMC_PATT3
0xAC FMC_PATT4
0xB0 FMC_PIO4
0x74 FMC_ECCR2
0x94 FMC_ECCR3
0x140 FMC_SDCR_1
0x144 FMC_SDCR_2
0x148 FMC_SDTR1 Reserved
0x14C FMC_SDTR2 Reserved
0x150 FMC_SDCMR
Table 297. FMC register map (continued)
Res.
Res.
Res.
Reserved
Reserved
Reserved
MEMHIZ[7:0] MEMHOLD[7:0]
MEMHIZ[7:0] MEMHOLD[7:0]
MEMHIZ[7:0] MEMHOLD[7:0]
ATTHIZ[7:0] ATTHOLD[7:0]
ATTHIZ[7:0] ATTHOLD[7:0]
ATTHIZ[7:0] ATTHOLD[7:0]
IOHIZ[7:0]
Reserved
Reserved
TRCD[3:0] TRP[3:0]
TRCD[3:0] TRP[3:0]
Reserved
RM0090 Rev 18
BUSTURN[3:0]
BUSTURN[3:0]
BUSTURN[3:0]
Reserved
Reserved
Reserved
MEMWAIT[7:0]
MEMWAIT[7:0]
MEMWAIT[7:0]
ATTWAIT[7:0]
ATTWAIT[7:0]
ATTWAIT[7:0]
IOHOLD[7:0]
ECC[31:0]
ECC[31:0]
TWR[3:0] TRC[3:0]
TWR[3:0] TRC[3:0]
Flexible memory controller (FMC)
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
Res.
Res.
Res.
MEMSET[7:0]
MEMSET[7:0]
MEMSET[7:0]
IOWAIT[7:0]
TRAS[3:0] TXSR[3:0]
TRAS[3:0] TXSR[3:0]
ATTSET[7:0]
ATTSET[7:0]
ATTSET[7:0]
IOSET[7:0]
TMRD[3:0]
TMRD[3:0]
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