ST STM32F405 Reference Manual page 1676

Flexible memory controller (FMC)
Bits 23:20 TRP[3:0]: Row precharge delay
These bits define the delay between a Precharge command and another command in number of
memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM
devices are used, the TRP must be programmed with the timing of the slowest device.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: The corresponding bits in the FMC_SDTR2 register are don't care.
Bits 19:16 TWR[3:0]: Recovery delay
These bits define the delay between a Write and a Precharge command in number of memory clock
cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: TWR must be programmed to match the write recovery time (t
datasheet, and to guarantee that:
TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP
Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be
programmed to 0x1.
If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed
with the same TWR timing corresponding to the slowest SDRAM device.
Bits 15:12 TRC[3:0]: Row cycle delay
These bits define the delay between the Refresh command and the Activate command, as well as d
the delay between two consecutive Refresh commands. It is expressed in number of memory clock
cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are
used, the TRC must be programmed with the timings of the slowest device.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM
device datasheet.
Note: The corresponding bits in the FMC_SDTR2 register are don't care.
Bits 11:8 TRAS[3:0]: Self refresh time
These bits define the minimum Self-refresh period in number of memory clock cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Bits 7:4 TXSR[3:0]: Exit Self-refresh delay
These bits define the delay from releasing the Self-refresh command to issuing the Activate
command in number of memory clock cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
1676/1749 RM0090 Rev 18
RM0090
) defined in the SDRAM
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