Figure 449. Asynchronous Wait During A Read Access; Figure 450. Asynchronous Wait During A Write Access - ST STM32F405 Reference Manual

Flexible static memory controller (FSMC)
A[25:0]
NEx
NWAIT
NOE
D[15:0]
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
A[25:0]
NWAIT
D[15:0]
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
1570/1749

Figure 449. Asynchronous wait during a read access

address phase
don't care

Figure 450. Asynchronous wait during a write access

address phase
NEx
don't care
NWE
Memory transaction
data setup phase
Memory transaction
data setup phase
data driven by FSMC
RM0090 Rev 18
don't care
data driven
by memory
4HCLK
don't care
1HCLK
3HCLK
RM0090
ai18471b
ai15797c