ST STM32F405 Reference Manual page 1734

Revision history
Date Version
16-Mar-2015
(continued)
1734/1749
Table 315. Document revision history (continued)
I2C2:
Updated FREQ[5:0] description in
USART:
Removed note related to RXNEIE in
FSMC:
Updated Figure 474: Synchronous multiplexed read mode waveforms - NOR,
PSRAM (CRAM).
USB OTG FS
9
Updated Table 203: TRDT values
FMC
Updated FMC_NL in
Updated 'Memory wait' and 'Memory data bus high-z' parameters in
Programmable NAND Flash/PC Card access
Updated Section : Common memory space timing register 2..4
Updated Figure 476: NAND Flash/PC Card controller waveforms for common
memory access.
DEBUG:
Updated REV_ID[15:0) and JTAG ID code in
and Section 38.6.2: Boundary scan
Changes
Section 27.6.2: I
Section : Reception using DMA
Figure 456: FMC block
TAP, respectively
RM0090 Rev 18
2
C Control register 2
diagram.
Table 289:
parameters.
(FMC_PMEM2..4).
Section 38.6.1: MCU device ID code
RM0090
(I2C_CR2).