Figure 460. Modea Read Access Waveforms - ST STM32F405 Reference Manual

Flexible memory controller (FMC)
Bit
number
7-4
3-0
Mode A - SRAM/PSRAM (CRAM) OE toggling
1. NBL[3:0] are driven low during the read access
1620/1749
Table 270. FMC_BTRx bit fields (continued)
Bit name
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles).
ADDSET
Minimum value for ADDSET is 0.

Figure 460. ModeA read access waveforms

A[25:0]
NBL[3:0]
NEx
NOE
NWE
High
D[31:0]
Memory transaction
ADDSET DATAST
HCLK cycles HCLK cycles
RM0090 Rev 18
Value to set
data driven
by memory
RM0090
MS30454V1