ST STM32F405 Reference Manual page 1451

RM0090
Bits 31:16 OEPINT: OUT endpoint interrupt bits
Bits 15:0 IEPINT: IN endpoint interrupt bits
OTG_HS all endpoints interrupt mask register (OTG_HS_DAINTMSK)
Address offset: 0x81C
Reset value: 0x0000 0000
The device endpoint interrupt mask register works with the device endpoint interrupt register
to interrupt the application when an event occurs on a device endpoint. However, the device
all endpoints interrupt (OTG_HS_DAINT) register bit corresponding to that interrupt is still
set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 OEPM: OUT EP interrupt mask bits
Bits 15:0 IEPM: IN EP interrupt mask bits
OTG_HS device V
Address offset: 0x0828
Reset value:
This register specifies the V
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 VBUSDT: Device V
One bit per OUT endpoint:
Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15
One bit per IN endpoint:
Bit 0 for IN endpoint 0, bit 15 for endpoint 15
OEPM
One per OUT endpoint:
Bit 16 for OUT EP 0, bit 18 for OUT EP 3
0: Masked interrupt
1: Unmasked interrupt
One bit per IN endpoint:
Bit 0 for IN EP 0, bit 3 for IN EP 3
0: Masked interrupt
1: Unmasked interrupt
discharge time register (OTG_HS_DVBUSDIS)
BUS
0x0000 17D7
BUS
Reserved
discharge time
BUS
Specifies the V discharge time after V
BUS
V discharge time in PHY clocks / 1 024
BUS
Depending on your V
BUS
USB on-the-go high-speed (OTG_HS)
discharge time after V
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
pulsing during SRP. This value equals:
BUS
load, this value may need adjusting.
RM0090 Rev 18
9 8 7 6 5
IEPM
pulsing during SRP.
BUS
9 8 7 6 5
VBUSDT
4 3 2 1 0
4 3 2 1 0
1451/1749
1543