Table 280. Fmc_Bcrx Bit Fields; Figure 468. Moded Write Access Waveforms - ST STM32F405 Reference Manual

RM0090
The differences with mode1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.
Bit No.
31-21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4

Figure 468. ModeD write access waveforms

A[25:0]
NADV
NEx
NOE
NWE
D[31:0]
ADDSET
HCLK cycles

Table 280. FMC_BCRx bit fields

Bit name
Reserved
CCLKEN
CBURSTRW
CPSIZE
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID
RM0090 Rev 18
Flexible memory controller (FMC)
Memory transaction
1HCLK
data driven by FSMC
(DATAST+ 1)
HCLK cycles
ADDHLD
HCLK cycles
0x000
As needed
0x0 (no effect in asynchronous mode)
0x0 (no effect in asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep
at 0.
0x1
0x0 (no effect in asynchronous mode)
As needed
Don't care
0x0
Meaningful only if bit 15 is 1
0x0
0x1
Set according to memory support
As needed
Value to set
MS30462V1
1629/1749
1682