ST STM32F405 Reference Manual page 1733

RM0090
Date Version
16-Mar-2015
Table 315. Document revision history (continued)
PWR:
Updated Section 5.1.2: Battery backup
Updated Table 23: Low-power mode summary
condition.
Added Section : Entering low-power mode
Updated Section : Entering Sleep
Sleep-now entry and exit
Updated Section : Entering Stop mode (for STM32F405xx/07xx and
STM32F415xx/17xx),
STM32F415xx/17xx)
STM32F405xx/07xx and
mode (STM32F42xxx and
(STM32F42xxx and STM32F43xxx)
(STM32F42xxx and
Updated Section : Entering Standby
Table 30: Standby mode entry and
RCC:
Updated bits 24 to 31 access type in
register (RCC_CSR).
GPIOs:
9
Added port A reset value in
(GPIOx_OSPEEDR) (x =
DMA:
Update FTH[1:0] description in
register (DMA_SxFCR) (x =
TIM2/5:
Register format changed to 32 bits instead of 16 in
(TIMx_CNT) and
TIM9 to 14:
Updated Table 101: TIMx internal trigger connection
WWDG:
Updated Figure 214: Watchdog block diagram
the watchdog timeout.
Updated Figure 215: Window watchdog timing diagram
RNG:
Replaced PLL48CLK by RNG_CLK in the whole section.
Changes
domain.
mode, Section : Exiting Sleep
and Table 25: Sleep-on-exit entry and
Section : Exiting Stop mode (for STM32F405xx/07xx and
and Table 27: Stop mode entry and exit (for
STM32F415xx/17xx). Updated
STM32F43xxx),
and Table 29: Stop mode entry and exit
STM32F43xxx).
mode,
exit.
Section 7.3.21: RCC clock control & status
Section 8.4.3: GPIO port output speed register
A..I/J/K).
Section 10.5.10: DMA stream x FIFO control
0..7).
Section 18.4.12: TIMx auto-reload register
RM0090 Rev 18
Revision history
to add Return from ISR as entry
and Section : Exiting low-power
mode,
exit.
Section : Entering Stop
Section : Exiting Stop mode
Section : Exiting Standby mode
Section 18.4.10: TIMx counter
(TIMx_ARR).
and Section 22.4: How to program
mode.
Table 24:
and
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