Figure 476. Nand Flash/Pc Card Controller Waveforms For Common Memory Access - ST STM32F405 Reference Manual

RM0090

Figure 476. NAND Flash/PC Card controller waveforms for common memory access

HCLK
A[25:0]
NCEx
NREG,
NIOW,
NIOR
NWE,
NOE
write_data
read_data
1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.
2. For write accesses, the hold phase delay is (MEMHOLD) x HCLK cycles, while it is (MEMHOLD + 2) x
HCLK cycles for read accesses.
37.6.4 NAND Flash operations
The command latch enable (CLE) and address latch enable (ALE) signals of the NAND
Flash memory device are driven by address signals from the FMC controller. This means
that to send a command or an address to the NAND Flash memory, the CPU has to perform
a write to a specific address in its memory space.
A typical page read operation from the NAND Flash device requires the following steps:
3. Program and enable the corresponding memory bank by configuring the FMC_PCRx
and FMC_PMEMx (and for some devices, FMC_PATTx, see
Flash prewait
Flash memory (PWID bits for the data bus width of the NAND Flash, PTYP = 1,
PWAITEN = 0 or 1 as needed, see section
Card address mapping
4. The CPU performs a byte write to the common memory space, with data byte equal to
one Flash command byte (for example 0x00 for Samsung NAND Flash devices). The
LE input of the NAND Flash memory is active during the write strobe (low pulse on
NWE), thus the written byte is interpreted as a command by the NAND Flash memory.
Once the command is latched by the memory device, it does not need to be written
again for the following page read operations.
5. The CPU can send the start address (STARTAD) for a read operation by writing four
byte (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9],
STARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND Flash memories) in
the common memory or attribute space. The ALE input of the NAND Flash device is
active during the write strobe (low pulse on NWE), thus the written byte are interpreted
as the start address for read operations. Using the attribute memory space makes it
possible to use a different timing configuration of the FMC, which can be used to
High
MEMxSET
+ 1
(1)
MEMxHIZ
functionality) registers according to the characteristics of the NAND
for timing configuration).
RM0090 Rev 18
Flexible memory controller (FMC)
MEMxHOLD
MEMxWAIT + 1
Valid
Section 37.4.2: NAND Flash memory/PC
MS33733V2
Section 37.6.5: NAND
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