Table 281. Fmc_Btrx Bit Fields; Table 282. Fmc_Bwtrx Bit Fields - ST STM32F405 Reference Manual

Flexible memory controller (FMC)
Bit No.
3-2
1
0
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Bit No.
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
1630/1749
Table 280. FMC_BCRx bit fields (continued)
Bit name
MTYP[1:0]
MUXEN
MBKEN

Table 281. FMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x3
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) for
DATAST
read accesses.
Duration of the middle phase of the read access (ADDHLD HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for read
ADDSET[3:0]
accesses. Minimum value for ADDSET is 1.

Table 282. FMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x3
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST + 1 HCLK cycles) for
DATAST
write accesses.
Duration of the middle phase of the write access (ADDHLD HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for write
ADDSET[3:0]
accesses. Minimum value for ADDSET is 1.
RM0090 Rev 18
As needed
0x0
0x1
Value to set
Value to set
Value to set
RM0090