Figure 397. Receive Fifo Read Task - ST STM32F405 Reference Manual

RM0090
The application must ignore all packet statuses other than IN data packet (bx0010).
•
Bulk and control OUT/SETUP transactions
A typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in
Figure
SETUP transaction operates in the same way but has only one packet. The
assumptions are:
–
–
–
•
Normal bulk and control OUT/SETUP operations
The sequence of operations in (channel 1) is as follows:
a)
b)
c)
d)
e)
f)

Figure 397. Receive FIFO read task

Unmask RXFLVL
interrupt
Read the received
packet from the
Receive FIFO
Yes
398. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control
The application is attempting to send two maximum-packet-size packets (transfer
size = 1, 024 bytes).
The non-periodic transmit FIFO can hold two packets (128 bytes for FS).
The non-periodic request queue depth = 4.
Initialize channel 1
Write the first packet for channel 1
Along with the last word write, the core writes an entry to the non-periodic request
queue
As soon as the non-periodic queue becomes non-empty, the core attempts to
send an OUT token in the current frame
Write the second (last) packet for channel 1
The core generates the XFRC interrupt as soon as the last transaction is
completed successfully
USB on-the-go full-speed (OTG_FS)
Start
No
RXFLVL
interrupt ?
Yes
Mask RXFLVL
interrupt
Read
OTG_FS_GRXSTSP
PKTSTS
0b0010?
Yes
BCNT > 0?
RM0090 Rev 18
Unmask RXFLVL
interrupt
No
No
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