ST STM32F405 Reference Manual page 1723

RM0090
Date Version
19-Feb-2013
Table 315. Document revision history (continued)
Updated Section 2: Memory and bus
Updated Figure 1: System architecture for STM32F405xx/07xx and
STM32F415xx/17xx
STM32F405xx/07xx and STM32F415xx/17xx
mapping vs. Boot mode/physical
instruction execution. removed note 1 from
PWR:
Updated Figure 7: Power supply
Updated Section 5.1.3: Voltage
Added ADCDC1 bit in
STM32F42xxx and
SYSCFG:
Added ADCxDC2 bit in
register (SYSCFG_PMC) for STM32F42xxx and
4
ADC:
Updated Section 13.9.3: Interleaved
and Section 13.9.5: Combined regular/injected simultaneous mode
case of interrupted conversion.
Updated Section : Temperature sensor, V
Section 13.10: Temperature
RTC:
Updated BKP[31:0] bit description in
(RTC_BKPxR).
I2C:
Updated Section 27.3.5: Programmable noise
Changes
architecture.
devices, and Figure 1: System architecture for
remap. Updated
overview.
regulator.
Section 5.5.1: PWR power control register (PWR_CR) for
STM32F43xxx.
Section 8.2.3: SYSCFG peripheral mode configuration
mode,
sensor, and Section 13.11: Battery charge
Section 26.6.20: RTC backup registers
RM0090 Rev 18
Revision history
devices. Updated Table 4: Memory
Figure 5: Sequential 32-bit
Table 12: Program/erase
STM32F43xxx.
Section 13.9.4: Alternate trigger
and V internal
REFINT BAT
filter.
parallelism.
mode,
to describe
channels,
monitoring.
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