Download Print this page

Renesas SH7751 Group User Manual

Renesas 32-bit risc microcomputer superh risc engine family / sh7750 series

page of 1186

/ 1186
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Download this manual

SH7751 Group, SH7751R Group

32

Renesas 32-Bit RISC Microcomputer

SuperH™ RISC engine Family / SH7750 Series

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

User's Manual: Hardware

Rev.3.01 Sep 2013

Table of Contents

Advertisement

Chapters

Table of Contents

Need help?

Need help?

Do you have a question about the SH7751 Group and is the answer not in the manual?

Questions and answers

Summary of Contents for Renesas SH7751 Group

Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7751 Group, SH7751R Group User’s Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7750 Series Rev.3.01 Sep 2013...
Page 2 Page ii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 3 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 4 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 CPU and is also equipped with peripheral functions necessary for configuring a user system. The SH7751 Group is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and PCI controller (PCIC).
Page 6 • User manuals for SH7751 and SH7751R Name of Document Document No. SH7751 Group, SH7751R Group Hardware Manual This manual SH-4 Software Manual REJ09B0318-0600 • User manuals for development tools Name of Document Document No. SuperH™ C/C++ Compiler, Assembler, Optimizing Linkage Editor User's...
Page 7 Note amended Register 0 (PCICONF0) Note: * The vendor ID H'1054 specifies Hitachi, Ltd., but the SH7751 and SH7751R are now products of Renesas Electronics Corp. For information on these products, contact Renesas Electronics Corp. 22.12.5 Notes on Parity 980,...
Page 8 Item Page Revision (See Manual for Details) 23.2 DC Characteristics 982, Table title amended and note added Table 23.2 DC Notes: 3. T = –40 to 85°C for the HD6417751RBA240HV. Characteristics (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV) = –20 to +75°C* Table 23.4 DC 988,.
Page 9: Bus Timing
Item Page Revision (See Manual for Details) 23.3.1 Clock and Control 1002, Table title and table amended and note added Signal Timing 1003 Item Symbol Unit Figure Standby return oscillation settling time 1* — Table 23.16 Clock and OSC2 Standby return oscillation settling time 2* —...
Page 10 Item Page Revision (See Manual for Details) 23.3.4 Peripheral 1067 Table amended and note added Module Signal Timing HD6417751 HD6417751 RBP240 (V) RBP200 (V) 1069 Table 23.23 Peripheral HD6417751 HD6417751 RBG240 (V) RBG200 (V) Module Signal Timing (1) HD6417751 HD6417751 HD6417751 HD6417751 RBA240HV...
Page 11 Pins When PCI Is Not Used Appendix H Product 1125 Table note amended Lineup Notes: 1. Contact a Renesas sales office regarding Table H.1 product versions with specifications for a wider SH7751/SH7751R temperature range (−40 to +85°C). The wide Product Lineup temperature range (−40 to +85°C) is the...
Page 12 All trademarks and registered trademarks are the property of their respective owners. Page xii of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 13: Table Of Contents
Contents Section 1 Overview....................1 SH7751/SH7751R Group Features ..................1 Block Diagram ........................9 Pin Arrangement ........................10 Pin Functions ........................13 1.4.1 Pin Functions (256-Pin QFP).................. 13 1.4.2 Pin Functions (256-Pin BGA)................. 24 1.4.3 Pin Functions (292-Pin BGA)................. 35 Section 2 Programming Model ................47 Data Formats........................
Page 14 3.3.7 Address Space Identifier (ASID) ................77 TLB Functions ........................78 3.4.1 Unified TLB (UTLB) Configuration ..............78 3.4.2 Instruction TLB (ITLB) Configuration..............82 3.4.3 Address Translation Method................... 82 MMU Functions........................85 3.5.1 MMU Hardware Management................85 3.5.2 MMU Software Management ................. 85 3.5.3 MMU Instruction (LDTLB)..................
Page 15 4.3.7 OC Index Mode ....................113 4.3.8 Coherency between Cache and External Memory ..........113 4.3.9 Prefetch Operation ....................113 4.3.10 Notes on Using OC RAM Mode (SH7751R Only) when in Cache Enhanced Mode ........................114 Instruction Cache (IC)......................116 4.4.1 Configuration ......................
Page 16 5.5.3 Exception Requests and BL Bit ................146 5.5.4 Return from Exception Handling................146 Description of Exceptions....................146 5.6.1 Resets........................147 5.6.2 General Exceptions....................152 5.6.3 Interrupts....................... 166 5.6.4 Priority Order with Multiple Exceptions .............. 169 Usage Notes ........................170 Restrictions ........................
Page 17 Section 8 Pipelining ...................211 Pipelines..........................211 Parallel-Executability......................218 Execution Cycles and Pipeline Stalling ................222 Usage Notes ........................238 Section 9 Power-Down Modes ................239 Overview..........................239 9.1.1 Types of Power-Down Modes ................239 9.1.2 Register Configuration..................241 9.1.3 Pin Configuration....................241 Register Descriptions ......................
Page 18 9.9.1 In Reset ......................... 255 9.9.2 In Exit from Standby Mode .................. 256 9.9.3 In Exit from Sleep Mode ..................257 9.9.4 In Exit from Deep Sleep Mode ................260 9.9.5 Hardware Standby Mode Timing................262 9.10 Usage Notes ........................264 9.10.1 Note on Current Consumption ................
Page 19 Section 11 Realtime Clock (RTC) ..............291 11.1 Overview..........................291 11.1.1 Features......................... 291 11.1.2 Block Diagram...................... 292 11.1.3 Pin Configuration....................293 11.1.4 11.1.4 Register Configuration................293 11.2 Register Descriptions ......................295 11.2.1 64 Hz Counter (R64CNT)..................295 11.2.2 Second Counter (RSECCNT) ................296 11.2.3 Minute Counter (RMINCNT) ................
Page 20 12.1.4 Register Configuration..................317 12.2 Register Descriptions......................318 12.2.1 Timer Output Control Register (TOCR)............... 318 12.2.2 Timer Start Register (TSTR) ................319 12.2.3 Timer Start Register 2 (TSTR2) ................320 12.2.4 Timer Constant Registers (TCOR) ............... 321 12.2.5 Timer Counters (TCNT) ..................321 12.2.6 Timer Control Registers (TCR) ................
Page 21 13.2.13 Refresh Time Constant Register (RTCOR) ............391 13.2.14 Refresh Count Register (RFCR) ................392 13.2.15 Notes on Accessing Refresh Control Registers ............ 392 13.3 Operation ........................... 393 13.3.1 Endian/Access Size and Data Alignment.............. 393 13.3.2 Areas ........................400 13.3.3 SRAM Interface....................405 13.3.4 DRAM Interface ....................
Page 22 14.4.1 Examples of Transfer between External Memory and an External Device with DACK......................552 14.5 On-Demand Data Transfer Mode (DDT Mode) ..............553 14.5.1 Operation ......................553 14.5.2 Pins in DDT Mode....................555 14.5.3 Transfer Request Acceptance on Each Channel ........... 558 14.5.4 Notes on Use of DDT Module ................
Page 23 15.2.9 Bit Rate Register (SCBRR1) ................623 15.3 Operation ........................... 631 15.3.1 Overview....................... 631 15.3.2 Operation in Asynchronous Mode ................ 633 15.3.3 Multiprocessor Communication Function............. 644 15.3.4 Operation in Synchronous Mode ................655 15.4 SCI Interrupt Sources and DMAC ..................665 15.5 Usage Notes ........................
Page 24 17.2 Register Descriptions......................722 17.2.1 Smart Card Mode Register (SCSCMR1) .............. 722 17.2.2 Serial Mode Register (SCSMR1)................723 17.2.3 Serial Control Register (SCSCR1)................ 724 17.2.4 Serial Status Register (SCSSR1) ................725 17.3 Operation ........................... 726 17.3.1 Overview ......................726 17.3.2 Pin Connections ....................727 17.3.3 Data Format ......................
Page 25 19.3 Register Descriptions ......................780 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ..........780 19.3.2 Interrupt Control Register (ICR)................781 19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00) ........783 19.3.4 Interrupt Factor Register 00 (INTREQ00)............784 19.3.5 Interrupt Mask Register 00 (INTMSK00)............. 784 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) ...........
Page 26 20.3.7 Program Counter (PC) Value Saved ..............812 20.3.8 Contiguous A and B Settings for Sequential Conditions ........813 20.3.9 Usage Notes ......................814 20.4 User Break Debug Support Function ................. 816 20.5 Examples of Use ........................ 818 20.6 User Break Controller Stop Function................. 820 20.6.1 Transition to User Break Controller Stopped State..........
Page 27 22.2.5 PCI Configuration Register 4 (PCICONF4) ............867 22.2.6 PCI Configuration Register 5 (PCICONF5) ............869 22.2.7 PCI Configuration Register 6 (PCICONF6) ............871 22.2.8 PCI Configuration Register 7 (PCICONF7) to PCI Configuration Register 10 (PCICONF10)....................... 873 22.2.9 PCI Configuration Register 11 (PCICONF11) ............. 874 22.2.10 PCI Configuration Register 12 (PCICONF12) .............
Page 28 22.3.2 PCI Commands..................... 929 22.3.3 PCIC Initialization ....................930 22.3.4 Local Register Access................... 931 22.3.5 Host Functions ...................... 931 22.3.6 PCI Bus Arbitration in Non-host Mode ..............934 22.3.7 PIO Transfers......................934 22.3.8 Target Transfers....................937 22.3.9 DMA Transfers..................... 940 22.3.10 Transfer Contention within PCIC .................
Page 29 Section 23 Electrical Characteristics ..............983 23.1 Absolute Maximum Ratings ....................983 23.2 DC Characteristics ......................984 23.3 AC Characteristics ......................996 23.3.1 Clock and Control Signal Timing ................. 998 23.3.2 Control Signal Timing ..................1012 23.3.3 Bus Timing ......................1016 23.3.4 Peripheral Module Signal Timing...............
Page 30 Page xxx of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 31 Figures Section 1 Overview Figure 1.1 Block Diagram of SH7751/SH7751R Group Functions ..........9 Figure 1.2 Pin Arrangement (256-Pin QFP)................10 Figure 1.3 Pin Arrangement (256-Pin BGA)................11 Figure 1.4 Pin Arrangement (292-Pin BGA)................12 Section 2 Programming Model Figure 2.1 Data Formats ......................
Page 32 Figure 4.3 Configuration of Operand Cache (SH7751R) ............107 Figure 4.4 Configuration of Write-Back Buffer ............... 111 Figure 4.5 Configuration of Write-Through Buffer..............111 Figure 4.6 Configuration of Instruction Cache (SH7751) ............117 Figure 4.7 Configuration of Instruction Cache (SH7751R)............118 Figure 4.8 Memory-Mapped IC Address Array ...............
Page 33 STATUS Output in Deep Sleep → Interrupt Sequence .......... 260 Figure 9.9 Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence ......260 Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence ........261 Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation)... 262 Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) ....
Page 34 Figure 13.7 Example of 32-Bit Data Width SRAM Connection..........407 Figure 13.8 Example of 16-Bit Data Width SRAM Connection..........408 Figure 13.9 Example of 8-Bit Data Width SRAM Connection..........409 Figure 13.10 SRAM Interface Wait Timing (Software Wait Only)........... 410 Figure 13.11 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal)..
Page 35 Figure 13.38 (1) Synchronous DRAM Mode Write Timing (PALL) .......... 452 Figure 13.38 (2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ....453 Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8) ..455 Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM ........
Page 36 Section 14 Direct Memory Access Controller (DMAC) Figure 14.1 Block Diagram of DMAC..................500 Figure 14.2 DMAC Transfer Flowchart................... 519 Figure 14.3 Round Robin Mode....................524 Figure 14.4 Example of Changes in Priority Order in Round Robin Mode ......525 Figure 14.5 Data Flow in Single Address Mode ..............
Page 37 Figure 14.26 Single Address Mode/Synchronous DRAM → External Device Longword Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD = 1, CAS latency = 3, TPC = 3) ..............559 Figure 14.27 Single Address Mode/External Device → Synchronous DRAM Longword Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD = 1, TRWL = 2, TPC = 1) ................
Page 38 Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer/Direct Data Transfer Request to Channel 2..........576 Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer/Direct Data Transfer Request to Channel 2..........577 Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 ..
Page 39 Figure 15.17 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ................ 654 Figure 15.18 Data Format in Synchronous Communication............655 Figure 15.19 Sample SCI Initialization Flowchart..............657 Figure 15.20 Sample Serial Transmission Flowchart..............658 Figure 15.21 Example of SCI Transmit Operation ..............
Page 40 Figure 17.9 Sample Reception Processing Flowchart.............. 739 Figure 17.10 Receive Data Sampling Timing in Smart Card Mode .......... 741 Figure 17.11 Retransfer Operation in SCI Receive Mode ............743 Figure 17.12 Retransfer Operation in SCI Transmit Mode............743 Figure 17.13 Procedure for Stopping and Restarting the Clock..........744 Section 18 I/O Ports Figure 18.1 16-Bit Port A......................
Page 41 Figure 22.8 Master Read Cycle in Host Mode (Single) ............949 Figure 22.9 Master Memory Write Cycle in Non-Host Mode (Burst) ........950 Figure 22.10 Master Memory Read Cycle in Non-Host Mode (Burst) ........951 Figure 22.11 Target Read Cycle in Non-Host Mode (Single)............ 953 Figure 22.12 Target Write Cycle in Non-Host Mode (Single)...........
Page 42 Standby Return Oscillation Settling Time (Return by IRL3–IRL0) ....1010 Figure 23.8 PLL Synchronization Settling Time in Case of RESET, MRESET or Figure 23.9 NMI Interrupt...................... 1011 Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt ......1011 Figure 23.11 Control Signal Timing ..................
Page 43 Figure 23.31 Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001)..1038 Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001). 1039 Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001)..... 1040 Figure 23.34 (a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL)....
Page 44 Figure 23.52 PCMCIA I/O Bus Cycle (TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait, Bus Sizing)................1060 Figure 23.53 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data (One Internal Wait + One External Wait)..........1061 Figure 23.54 MPX Basic Bus Cycle: Write (1) 1st Data (No Wait) (2) 1st Data (One Internal Wait) (3) 1st Data (One Internal Wait + One External Wait)..
Page 45 Figure B.3 Package Dimensions (292-pin BGA) ..............1093 Figure B.4 Package Dimensions (256-pin BGA: HD6417751RBA240HV)......1094 Appendix F Instruction Prefetching and Its Side Effects Figure F.1 Instruction Prefetch ....................1119 Appendix G Power-On and Power-Off Procedures Figure G.1 Method for Temporarily Selecting Clock Operation Mode 6 ....... 1123 Figure G.2 Power-On Procedure 1 ..................
Page 46 Page xlvi of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 47 Tables Section 1 Overview Table 1.1 SH7751/SH7751R Group Features ................2 Table 1.2 Pin Functions......................13 Table 1.3 Pin Functions......................24 Table 1.4 Pin Functions......................35 Section 2 Programming Model Table 2.1 Initial Register Values....................49 Section 3 Memory Management Unit (MMU) Table 3.1 MMU Registers......................
Page 48 Table 7.10 Floating-Point Double-Precision Instructions ............206 Table 7.11 Floating-Point Control Instructions................. 206 Table 7.12 Floating-Point Graphics Acceleration Instructions ..........207 Section 8 Pipelining Table 8.1 Instruction Groups....................218 Table 8.2 Parallel-Executability....................222 Table 8.3 Execution Cycles..................... 229 Section 9 Power-Down Modes Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes......
Page 49 Table 13.7 When MPX Interface Is Set (Areas 0 to 6).............. 373 Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment ......394 Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment ......395 Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment......396 Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment ......
Page 50 Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)..................... 629 Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)....630 Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)..... 630 Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection .........
Page 51 Table 19.4 Interrupt Exception Handling Sources and Priority Order ........777 Table 19.5 Interrupt Request Sources and IPRA–IPRD Registers..........781 Table 19.6 Interrupt Request Sources and INTPRI00 Register..........783 Table 19.7 Bit Allocation ......................786 Table 19.8 Interrupt Response Time ..................790 Section 20 User Break Controller (UBC) Table 20.1 UBC Registers......................
Page 52 Table 23.8 Permissible Output Currents ................... 996 Table 23.9 Clock Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV)..................996 Table 23.10 Clock Timing (HD6417751RF240 (V))..............996 Table 23.11 Clock Timing (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*)..................997 Table 23.12 Clock Timing (HD6417751RF200 (V))..............997 Table 23.13 Clock Timing (HD6417751BP167 (V), HD6417751F167 (V))......
Page 53 Appendix D Pin Functions Table D.1 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable, Disable Common)................1099 Table D.2 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable)..1101 Table D.3 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Disable) .. 1103 Table D.4 Handling of Pins When PCI Is Not Used ..............
Page 54 Page liv of liv R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 55: Section 1 Overview
SH7751/SH7751R Group Features The SH7751/SH7751R Group microprocessor, featuring a built-in PCI bus controller compatible with PCs and multimedia devices. The SuperH™* RISC engine is a Renesas original 32-bit RISC (Reduced Instruction Set Computer) microcomputer. The SuperH™ RISC engine employs a fixed- length 16-bit instruction set, allowing an approximately 50% reduction in program size over a 32- bit instruction set.
Page 56: Section 1 Overview
Section 1 Overview SH7751 Group, SH7751R Group Table 1.1 SH7751/SH7751R Group Features Item Features • Superscalar architecture: Parallel execution of two instructions • External buses (SH buses) ⎯ Separate 26-bit address and 32-bit data buses ⎯ External bus frequency of 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus frequency •...
Page 57 SH7751 Group, SH7751R Group Section 1 Overview Item Features • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero •...
Page 58 Section 1 Overview SH7751 Group, SH7751R Group Item Features • Clock pulse Choice of main clock generator (CPG) ⎯ SH7751: 1/2, 1, 3, or 6 times EXTAL ⎯ SH7751R: 1, 6, or 12 times EXTAL • Clock modes: (Maximum frequency: Varies with models) ⎯...
Page 59 SH7751 Group, SH7751R Group Section 1 Overview Item Features • Instruction cache (IC) Cache memory ⎯ 8 Kbytes, direct mapping [SH7751] ⎯ 256 entries, 32-byte block length ⎯ Normal mode (8-Kbyte cache) ⎯ Index mode • Operand cache (OC) ⎯ 16 Kbytes, direct mapping ⎯...
Page 60 Section 1 Overview SH7751 Group, SH7751R Group Item Features • Interrupt controller Five independent external interrupts (NMI, IRL3 to IRL0) (INTC) • 15-level signed external interrupts: IRL3 to IRL0 • On-chip peripheral module interrupts: Priority level can be set for each module •...
Page 61 SH7751 Group, SH7751R Group Section 1 Overview Item Features • Direct memory Physical address DMA controller access controller ⎯ SH7751: 4-channel (DMAC) ⎯ SH7751R: 8-channel • Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes • Address modes: ⎯...
Page 62 Section 1 Overview SH7751 Group, SH7751R Group Item Features • PCI bus controller PCI bus controller (supports a subset of PCI revision 2.1)* (PCIC) ⎯ 32-bit bus ⎯ 33 MHz/66 MHz support • PCI master/slave support • PCI host function support ⎯...
Page 63: Block Diagram
SH7751 Group, SH7751R Group Section 1 Overview Block Diagram Figure 1.1 shows an internal block diagram of the SH7751/SH7751R Group. Lower 32-bit data SH-4 Core Cache and I cache ITLB UTLB O cache controller INTC DMAC (SCIF) PCIC (PCI)DMAC Legend:...
Page 64: Pin Arrangement
Section 1 Overview SH7751 Group, SH7751R Group Pin Arrangement SERR XTAL2 PCIREQ1/GNTIN EXTAL2 PCIGNT1/REQOUT VDD-RTC VSS-RTC PCICLK PCIRST RESET INTA TRST IDSEL MRESET PCIREQ2/MD9 BACK/BSREQ BREQ/BSACK PCIREQ3/MD10 PCIREQ4 MD6/IOIS16 PCIGNT2 PCIGNT3 PCIGNT4 SLEEP WE3/ICIOWR MD2/RXD2 WE2/ICIORD QFP256 TCLK MD8/RTS2 MD1/TXD2...
Page 65: Figure 1.3 Pin Arrangement (256-Pin Bga)
SH7751 Group, SH7751R Group Section 1 Overview DREQ0 BACK/BSREQ XTAL VDD-PLL1 DACK1 AUDATA1 MD7/CTS2 XTAL2 RESET EXTAL VDD-PLL2 DRAK1 MD3/CE2A AUDCK MD8/RTS2 EXTAL2 IRL3 MRESET STATUS1 DACK0 AUDSYNC BREQ/BSACK MD1/TXD2 DRAK0 AUDATA2 TCLK TRST IRL1 STATUS0 AUDATA0 MD0/SCK2 DREQ1 IRL2...
Page 66: Figure 1.4 Pin Arrangement (292-Pin Bga)
Section 1 Overview SH7751 Group, SH7751R Group XTAL VDD-PLL1 STATUS0 AUDATA0 MD1/TXD2 MD2/RXD2 XTAL2 VDD-RTC RESET EXTAL VDD-PLL2 DRAK0 AUDATA3 AUDSYNC TCLK EXTAL2 VSS-CPG MD6/IOIS16 IRL3 BACK/BSREQ VSS-PLL2 STATUS1 DACK0 AUDATA1 MD0/SCK2 VSS-RTC ASEBRK/ TRST AUDCK VDD-CPG DRAK1 MD3/CE2A MD8/RTS2...
Page 67: Pin Functions
SH7751 Group, SH7751R Group Section 1 Overview Pin Functions 1.4.1 Pin Functions (256-Pin QFP) Table 1.2 Pin Functions Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Mode (H-UDI) Clock (H-UDI) VDDQ Power IO VDD VSSQ Power IO GND...
Page 68 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Data Data Data VDDQ Power IO VDD VSSQ Power IO GND Data Data Data Data Data CAS0/ CAS0 D7–D0 DQM0 DQM0 select signal...
Page 69 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSSQ Power IO GND Address Address Address Address Address Address Address Address Address Address VDDQ Power IO VDD VSSQ Power IO GND...
Page 70 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Data Data Data Data Data Data ACCSIZE0 VDDQ Power IO VDD VSSQ Power IO GND Data ACCSIZE1 Data ACCSIZE2 Power Internal VDD...
Page 71 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA 116 PCIGNT2 Bus grant (host function) 117 PCIREQ4 Bus request (host function) 118 PCIREQ3/ Bus request MD10 MD10 (host function)/ mode 119 VDDQ...
Page 72 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA 134 AD28 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 135 AD27 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 136 AD26...
Page 73 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA 156 DEVSEL Device select 157 VDDQ Power IO VDD 158 VSSQ Power IO GND 159 PCISTOP Transaction stop 160 PCILOCK Exclusive access...
Page 74 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA 179 AD5 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 180 AD4 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port 181 AD3...
Page 75 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA 202 BACK/ BSREQ acknowledge/ bus request 203 BREQ/ BSACK request/bus acknowledge IOIS16 204 MD6/ Mode/IOIS16 IOIS16 (PCMCIA) 205 RDY Bus ready 206 TXD...
Page 76 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA 225 VDD Power Internal VDD 226 VSS Power Internal GND 227 AUDATA2 AUD data 228 AUDATA3 AUD data 229 Reserved Do not...
Page 77 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface No. Pin Name Function Reset SRAM DRAM SDRAM PCMCIA 247 VDDQ Power IO VDD 248 VSSQ Power IO GND 249 VDD-PLL2 Power PLL2 VDD 250 VSS-PLL2 Power PLL2 GND 251 VDD-PLL1...
Page 78: Pin Functions (256-Pin Bga)
Section 1 Overview SH7751 Group, SH7751R Group 1.4.2 Pin Functions (256-Pin BGA) Table 1.3 Pin Functions Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Mode (H-UDI) Clock (H-UDI) VDDQ Power IO VDD VSSQ Power IO GND Data in...
Page 79 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA Data Data VDDQ Power IO VDD VSSQ Power IO GND Data Data Data Data Data CAS0/ CAS0 D7–D0 DQM0 DQM0 select signal...
Page 80 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSSQ Power IO GND Address Address Address Address Address Address Address Address Address Address VDDQ Power IO VDD VSSQ Power IO GND...
Page 81 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data Data Data Data Data Data ACCSIZE0 VDDQ Power IO VDD VSSQ Power IO GND Data ACCSIZE1 Data ACCSIZE2 Power Internal VDD...
Page 82 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA PCIGNT2 Bus grant (host function) PCIREQ4 Bus request (host function) PCIREQ3/ Bus request MD10 MD10 (host function)/ mode VDDQ Power IO VDD...
Page 83 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA AD26 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD25 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD24 PCI address/ (Port)
Page 84 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSSQ Power IO GND PCISTOP Transaction stop PCILOCK Exclusive access PERR Parity error Parity C/BE1 Command/ byte enable AD15 PCI address/ (Port)
Page 85 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA PCI address/ (Port) (Port) (Port) (Port) (Port) data/port PCI address/ (Port) (Port) (Port) (Port) (Port) data/port PCI address/ (Port) (Port) (Port) (Port)
Page 86 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA BREQ/ BSACK request/bus acknowledge IOIS16 MD6/ Mode/IOIS16 IOIS16 (PCMCIA) Bus ready SCI data output VDDQ Power IO VDD VSSQ Power IO GND...
Page 87 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA AUDATA2 AUD data AUDATA3 AUD data Do not connect CE2A MD3/CE2A I/O Mode/ PCMCIA-CE CE2B MD4/CE2B I/O Mode/ PCMCIA-CE Mode VDDQ Power...
Page 88 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA VSS-PLL2 Power PLL2 GND VDD-PLL1 Power PLL1 VDD VSS-PLL1 Power PLL1 GND VDD-CPG Power CPG VDD VSS-CPG Power CPG GND XTAL Crystal...
Page 89: Pin Functions (292-Pin Bga)
SH7751 Group, SH7751R Group Section 1 Overview 1.4.3 Pin Functions (292-Pin BGA) Table 1.4 Pin Functions Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Mode (H-UDI) Clock (H-UDI) VDDQ Power IO VDD Power Data in (H-UDI)
Page 90 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data Data VDDQ Power IO VDD Power Data Data Data Data Data CAS0/ CAS0 D7–D0 DQM0 DQM0 select signal CAS1/ CAS1 D15–D8...
Page 91 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Address Address Address Address Address Address Address Address Address Address VDDQ Power IO VDD Power Address Address Address Address CAS2/ CAS2 D23–D16 select...
Page 92 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data Data Data Data ACCSIZE0 VDDQ Power IO VDD Power Data ACCSIZE1 Data ACCSIZE2 Power Internal VDD Power Address Address Address...
Page 93 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX PCIREQ3/ Bus request MD10 MD10 (host function)/ mode VDDQ Power IO VDD Power PCIREQ2/ Bus request (host function)/ mode IDSEL Configuration...
Page 94 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX AD24 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port C/BE3 PCI address/ data/port AD23 PCI address/ (Port) (Port) (Port) (Port) (Port)
Page 95 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Parity C/BE1 Command/ byte enable AD15 PCI address/ (Port) (Port) (Port) (Port) (Port) data/port AD14 PCI address/ (Port) (Port) (Port) (Port)
Page 96 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX VDDQ Power I/O VDD PCI address/ (Port) (Port) (Port) (Port) (Port) data/port PCI address/ (Port) (Port) (Port) (Port) (Port) data/port IRL0...
Page 97 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Power Internal VDD Power MD2/RXD2 I Mode/SCIF RXD2 RXD2 RXD2 RXD2 RXD2 data input SCI data input TCLK RTC/TMU clock MD8/RTS2 I/O...
Page 98 Section 1 Overview SH7751 Group, SH7751R Group Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX DACK0 DMAC0 bus acknowledge DACK1 DMAC1 bus acknowledge DRAK0 DMAC0 request acknowledge DRAK1 DMAC1 request acknowledge Power Internal VDD VDDQ Power...
Page 99 SH7751 Group, SH7751R Group Section 1 Overview Memory Interface Number Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power...
Page 100 Section 1 Overview SH7751 Group, SH7751R Group Legend: Input Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used.
Page 101: Section 2 Programming Model
SH7751 Group, SH7751R Group Section 2 Programming Model Section 2 Programming Model Data Formats The data formats handled by the SH-4 are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) 31 30 Single-precision floating-point (32 bits)
Page 102: Register Configuration
Section 2 Programming Model SH7751 Group, SH7751R Group Register Configuration 2.2.1 Privileged Mode and Banks Processor Modes: The SH-4 has two processor modes, user mode and privileged mode. The SH-4 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted.
Page 103 SH7751 Group, SH7751R Group Section 2 Programming Model Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0–...
Page 104: Figure 2.2 Cpu Register Configuration In Each Processor Mode
Section 2 Programming Model SH7751 Group, SH7751R Group R0 _ BANK0* R0 _ BANK0* R0 _ BANK1* R1 _ BANK0* R1 _ BANK1* R1 _ BANK0* R2 _ BANK0* R2 _ BANK1* R2 _ BANK0* R3 _ BANK0* R3 _ BANK1*...
Page 105: General Registers
SH7751 Group, SH7751R Group Section 2 Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processor modes and general registers. The SH-4 has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0–R15 in one processor mode.
Page 106: Figure 2.3 General Registers
Section 2 Programming Model SH7751 Group, SH7751R Group SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0_BANK0 R0_BANK0 R1_BANK0 R1_BANK0 R2_BANK0 R2_BANK0 R3_BANK0 R3_BANK0 R4_BANK0 R4_BANK0 R5_BANK0 R5_BANK0 R6_BANK0 R6_BANK0 R7_BANK0 R7_BANK0...
Page 107: Floating-Point Registers
SH7751 Group, SH7751R Group Section 2 Programming Model 2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX.
Page 108: Figure 2.4 Floating-Point Registers
Section 2 Programming Model SH7751 Group, SH7751R Group XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} •...
Page 109: Control Registers
SH7751 Group, SH7751R Group Section 2 Programming Model Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X = undefined))
Page 110: System Registers
Section 2 Programming Model SH7751 Group, SH7751R Group • T: True/false condition or carry/borrow bit Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt.
Page 111 SH7751 Group, SH7751R Group Section 2 Programming Model Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0.
Page 112: Memory-Mapped Registers
Section 2 Programming Model SH7751 Group, SH7751R Group When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
Page 113: Data Format In Registers
SH7751 Group, SH7751R Group Section 2 Programming Model Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined.
Page 114: Processor States
Section 2 Programming Model SH7751 Group, SH7751R Group The data format in memory is shown in figure 2.5. A + 1 A + 2 A + 3 A + 11 A + 10 A + 9 A + 8 Address A...
Page 115: Figure 2.6 Processor State Transitions
SH7751 Group, SH7751R Group Section 2 Programming Model branches to the start address of the user-coded exception service routine found from the sum of the contents of the vector base address and the vector offset. See section 5, Exceptions, for more information on resets, general exceptions, and interrupts.
Page 116: Processor Modes
Section 2 Programming Model SH7751 Group, SH7751R Group Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1.
Page 117: Section 3 Memory Management Unit (Mmu)
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Section 3 Memory Management Unit (MMU) Overview 3.1.1 Features The SH-4 can handle 29-bit external memory space from an 8-bit address space identifier and 32- bit logical (virtual) address space. Address translation from virtual address to physical address is performed using the memory management unit (MMU) built into the SH-4.
Page 118 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group manner. It is also provided with memory protection functions to prevent a process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake.
Page 119: Figure 3.1 Role Of The Mmu
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Virtual memory Physical Process 1 memory Physical Physical Process 1 memory memory Process 1 Virtual Physical Process 1 Process 1 memory memory Physical memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 Role of the MMU...
Page 120: Register Configuration
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Initial Area 7 Acces Name tion Value* Address* Address* s Size Page table entry high...
Page 121: Register Descriptions
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Register Descriptions There are six MMU-related registers. 1. PTEH 10 9 — — ASID 2. PTEL 31 30 29 28 10 9 — — — — V SZ SZ C D SH WT 3.
Page 122 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID).
Page 123 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) TLB invalidate Address translation bit Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area.
Page 124 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group Ensure that values for which “Setting prohibited” is indicated in the above table are not set at the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update.
Page 125: Address Space
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Address Space 3.3.1 Physical Address Space The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical address space.
Page 126: Figure 3.4 P4 Area
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. For details, see section 14, Direct Memory Access Controller (DMAC). P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or not the cache is used is determined by the cache control register (CCR).
Page 127 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the MMUCR.SQMD bit.
Page 128: External Memory Space
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 3.3.2 External Memory Space The SH-4 supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA.
Page 129: Virtual Address Space
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) 3.3.3 Virtual Address Space Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical address space in the SH-4 to be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page units.
Page 130: On-Chip Ram Space
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group Here, access to an area of the PCMCIA interface by accessing an area of P1, P2, or P4 from the CPU is disabled. In addition, the PCMCIA interface is always accessed by the DMAC with the values of CHCRn, SSAn, CHCRn.DsAn, CHCRn.STC and CHCRn.DTC in the DMAC.
Page 131: Single Virtual Memory Mode And Multiple Virtual Memory Mode
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) of an access to an area other than the P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the P1 or P2 area, the physical address is uniquely determined without accessing the TLB.
Page 132: Tlb Functions
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group with a different ASID and unshared state (SH bit is 0). To avoid this, use workaround (1) or (2) below. (1) Purge the UTLB when switching the ASID values (PTEH and ASID) of the current processing.
Page 133: Figure 3.8 Relationship Between Page Size And Address Format
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) • 1-Kbyte page Virtual address Physical address 10 9 10 9 Offset Offset • 4-Kbyte page Virtual address Physical address 12 11 12 11 Offset Offset • 64-Kbyte page Virtual address...
Page 134 Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ: Page size bits Specify the page size. 00: 1-Kbyte page...
Page 135 SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1.
Page 136: Instruction Tlb (Itlb) Configuration
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB.
Page 137: Figure 3.10 Flowchart Of Memory Access Using Utlb
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area On-chip I/O access CCR.OCE?
Page 138: Figure 3.11 Flowchart Of Memory Access Using Itlb
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group Instruction access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area Access prohibited CCR.ICE?
Page 139: Mmu Functions
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) MMU Functions 3.5.1 MMU Hardware Management The SH-4 supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings.
Page 140: Hardware Itlb Miss Handling
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in figure 3.12. MMUCR 26 25 24 23 18 17 16 15...
Page 141: Avoiding Synonym Problems
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) information is not found in the UTLB search, an instruction TLB miss exception is generated and processing passes to software. 3.5.5 Avoiding Synonym Problems When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The...
Page 142: Mmu Exceptions
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception.
Page 143: Instruction Tlb Protection Violation Exception
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
Page 144: Data Tlb Multiple Hit Exception
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group The instruction TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1.
Page 145: Data Tlb Miss Exception
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Software Processing (Reset Routine): The UTLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated.
Page 146: Data Tlb Protection Violation Exception
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction.
Page 147: Initial Page Write Exception
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) 3.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted.
Page 148: Memory-Mapped Tlb Configuration
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction.
Page 149: Itlb Data Array 1
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) 10 9 8 7 Address field 1 1 1 1 0 0 1 0 10 9 9 8 7 Data field ASID Legend: ASID: Address space identifier VPN: Virtual page number...
Page 150: Itlb Data Array 2
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 10 9 8 7 Address field 1 1 1 1 0 0 30 29 28 10 9 8 7 2 1 0 Data field Legend: PPN: Physical page number Protection key data...
Page 151: Utlb Address Array
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) Address field 1 1 1 1 0 0 1 1 1 Data field Legend: Timing control bit Space attribute bits Entry Reserved bits (0 write value, undefined read value) Figure 3.15 Memory-Mapped ITLB Data Array 2 3.7.4...
Page 152: Utlb Data Array 1
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group When a write is performed with the A bit in the address field set to 1, comparison of all the UTLB entries is carried out using the VPN specified in the data field and PTEH.ASID. The usual address comparison rules are followed, but if a UTLB miss occurs, the result is no operation, and an exception is not generated.
Page 153: Utlb Data Array 2
SH7751 Group, SH7751R Group Section 3 Memory Management Unit (MMU) 1. UTLB data array 1 read PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field.
Page 154: Usage Notes
Section 3 Memory Management Unit (MMU) SH7751 Group, SH7751R Group 2. UTLB data array 2 write SA and TC specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. Address field...
Page 155: Section 4 Caches
SH7751 Group, SH7751R Group Section 4 Caches Section 4 Caches Overview 4.1.1 Features The SH7751 has an on-chip 8-Kbyte instruction cache (IC) for instructions and 16-Kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 Kbytes) can also be used as on- chip RAM.
Page 156: Register Configuration
Section 4 Caches SH7751 Group, SH7751R Group Table 4.2 Cache Features (SH7751R) Item Instruction Cache Operand Cache Capacity 16-Kbyte cache 32-Kbyte cache or 16-Kbyte cache + 16-Kbyte RAM Type 2-way set-associative 2-way set-associative Line size 32 bytes 32 bytes Entries...
Page 157: Register Descriptions
SH7751 Group, SH7751R Group Section 4 Caches Register Descriptions There are three cache and store queue related control registers, as shown in figure 4.1. 12 11 10 9 8 7 6 5 4 3 2 EMODE* ICI ICE WT OCE...
Page 158 Section 4 Caches SH7751 Group, SH7751R Group four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or U0 area should be located at least eight instructions after the CCR update instruction. • EMODE: Cache-double-mode bit Indicates whether or not cache-double-mode is used in the SH7751R.
Page 159: Operand Cache (Oc)
SH7751 Group, SH7751R Group Section 4 Caches • OCI: OC invalidation bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always returns 0 when read. • CB: Copy-back bit Indicates the P1 area cache write mode.
Page 160: Figure 4.2 Configuration Of Operand Cache (Sh7751)
Section 4 Caches SH7751 Group, SH7751R Group Figure 4.2 shows the configuration of the operand cache in the SH7751. Figure 4.3 shows the configuration of the operand cache in the SH7751R. Effective address 26 25 13 12 11 10 9...
Page 161: Figure 4.3 Configuration Of Operand Cache (Sh7751R)
SH7751 Group, SH7751R Group Section 4 Caches Effective address 26 25 13 12 RAM area Longword (LW) determination selection [12:5] [13] Entry selection Address array Data array (way 0, way 1) (way 0, way 1) 19 bits 1 bit 1 bit...
Page 162: Read Operation
Section 4 Caches SH7751 Group, SH7751R Group • U bit (dirty bit) The U bit is set to 1 if data is written to the cache line while the cache is being used in copy- back mode. That is, the U bit indicates a mismatch between the data in the cache line and the data in external memory.
Page 163: Write Operation
SH7751 Group, SH7751R Group Section 4 Caches 3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU.
Page 164 Section 4 Caches SH7751 Group, SH7751R Group 3b. Cache hit (write-through) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data field of the cache line indexed by effective address bits [13:5] and for the data indexed by effective address bits [4:0].
Page 165: Write-Back Buffer
SH7751 Group, SH7751R Group Section 4 Caches 4.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, this LSI has a write- back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss.
Page 166 Section 4 Caches SH7751 Group, SH7751R Group • When OC index mode is off (CCR.OIX = 0) H'7C00 0000 to H'7C00 0FFF (4 KB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 KB): Corresponds to RAM area 1...
Page 167: Oc Index Mode
SH7751 Group, SH7751R Group Section 4 Caches H'7C00 2000 to H'7C00 3FFF (8 KB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 5FFF (8 KB): Corresponds to RAM area 1 H'7C00 6000 to H'7C00 7FFF (8 KB): Corresponds to RAM area 2 A shadow of the RAM area occurs every 16 Kbytes up to H'7FFF FFFF.
Page 168: Notes On Using Oc Ram Mode (Sh7751R Only) When In Cache Enhanced Mode
Section 4 Caches SH7751 Group, SH7751R Group 4.3.10 Notes on Using OC RAM Mode (SH7751R Only) when in Cache Enhanced Mode When in cache enhanced mode (CCR.EMODE = 1) on the SH7751R, and the OC RAM mode, in which half of the operand cache is used as internal RAM, is selected (CCR.ORA = 1), data in RAM may be updated incorrectly.
Page 169 SH7751 Group, SH7751R Group Section 4 Caches Examples Example 1 A store instruction accessing internal RAM occurs within four instructions after an instruction generating a TLB miss exception. MOV.L #H'0C400000, R0 R0 is an address causing a TLB miss. MOV.L #H'7C000204, R1 R1 is an address mapped to internal RAM.
Page 170: Instruction Cache (Ic)
Section 4 Caches SH7751 Group, SH7751R Group Workarounds: When RAM mode is specified in cache enhanced mode, either of the following workarounds can be used to avoid the problem. Workaround 1: Use only 8 Kbytes of the 16-Kbyte internal RAM area. In this case, RAM areas for which address bits [12:0] are identical and only bit [13] differs must not be used.
Page 171: Figure 4.6 Configuration Of Instruction Cache (Sh7751)
SH7751 Group, SH7751R Group Section 4 Caches Figure 4.6 shows the configuration of the instruction cache in the SH7751. Figure 4.7 shows the configuration of the instruction cache in the SH7751R. Effective address 26 25 13 12 11 10 9...
Page 172: Figure 4.7 Configuration Of Instruction Cache (Sh7751R)
Section 4 Caches SH7751 Group, SH7751R Group Effective address 13 12 11 10 Longword (LW) selection [11:5] [12] Entry selection Address array (way 0, way 1) Data array (way 0, way 1) 19 bits 1 bit 32 bits 32 bits...
Page 173: Read Operation
SH7751 Group, SH7751R Group Section 4 Caches • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU (SH7751R only) In a 2-way set-associative system, up to two entry addresses can register the same data in cache.
Page 174: Ic Index Mode
Section 4 Caches SH7751 Group, SH7751R Group 4.4.3 IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address.
Page 175: Figure 4.8 Memory-Mapped Ic Address Array
SH7751 Group, SH7751R Group Section 4 Caches 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0.
Page 176: Ic Data Array
Section 4 Caches SH7751 Group, SH7751R Group 4.5.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 177: Oc Address Array
SH7751 Group, SH7751R Group Section 4 Caches 4.5.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 178: Oc Data Array
Section 4 Caches SH7751 Group, SH7751R Group not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine. 5 4 3 2 1 0 Address field 1 1 1 1 0 1 0 0...
Page 179: Memory-Mapped Cache Configuration (Sh7751R)
SH7751 Group, SH7751R Group Section 4 Caches 2 1 0 Address field 1 1 1 1 0 1 0 1 Entry Data field Longword data Legend: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.11 Memory-Mapped OC Data Array...
Page 180: Figure 4.12 Memory-Mapped Ic Address Array
Section 4 Caches SH7751 Group, SH7751R Group In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed.
Page 181: Ic Data Array
SH7751 Group, SH7751R Group Section 4 Caches 4.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 182: Oc Address Array
Section 4 Caches SH7751 Group, SH7751R Group 4.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 183: Oc Data Array
SH7751 Group, SH7751R Group Section 4 Caches occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine.
Page 184: Summary Of Memory-Mapped Oc Addresses
Section 4 Caches SH7751 Group, SH7751R Group 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field.
Page 185: Store Queues
SH7751 Group, SH7751R Group Section 4 Caches Store Queues Two 32-byte store queues (SQs) are supported to perform high-speed writes to external memory. When not using the SQs, the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped.
Page 186: Transfer To External Memory
Section 4 Caches SH7751 Group, SH7751R Group [4:2]: LW specification Specifies longword position in SQ0/SQ1 [1:0] Fixed at 0 4.7.3 Transfer to External Memory Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from the SQs to external memory.
Page 187: Determination Of Sq Access Exception
SH7751 Group, SH7751R Group Section 4 Caches QACR0 [4:2]: External address bits [28:26] corresponding to SQ0 QACR1 [4:2]: External address bits [28:26] corresponding to SQ1 External address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary.
Page 188: Sq Usage Notes (Sh7751 Only)
Section 4 Caches SH7751 Group, SH7751R Group 4.7.6 SQ Usage Notes (SH7751 Only) If an exception occurs within the three instructions preceding an instruction that writes to an SQ in the SH7751, a branch may be made to the exception handling routine after execution of the SQ write that should be suppressed when an exception occurs.
Page 189 SH7751 Group, SH7751R Group Section 4 Caches Example 2: When an instruction at which an exception occurs is a branch instruction and a branch is made Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.
Page 190 Section 4 Caches SH7751 Group, SH7751R Group Page 136 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 191: Section 5 Exceptions
SH7751 Group, SH7751R Group Section 5 Exceptions Section 5 Exceptions Overview 5.1.1 Features Exception handling is processing handled by a special routine, separate from normal program processing, that is executed by the CPU in case of abnormal events. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing.
Page 192: Register Descriptions
Section 5 Exceptions SH7751 Group, SH7751R Group Register Descriptions There are three registers related to exception handling. Addresses are allocated for these, and can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12- bit exception code.
Page 193: Exception Handling Functions
SH7751 Group, SH7751R Group Section 5 Exceptions Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR) and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register 15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.
Page 194: Exception Types And Priorities
Section 5 Exceptions SH7751 Group, SH7751R Group Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level...
Page 195 SH7751 Group, SH7751R Group Section 5 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Nonmaskable interrupt — (VBR) H'600 H'1C0 type External IRL3–IRL0 (VBR) H'600 H'200 interrupts H'220 H'240 H'260 H'280...
Page 196 Section 5 Exceptions SH7751 Group, SH7751R Group Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Peripheral H-UDI H-UDI (VBR) H'600 H'600 type module GPIO GPIOI H'620 interrupt DMAC DMTE0 H'640 (module/ source)
Page 197: Exception Flow
SH7751 Group, SH7751R Group Section 5 Exceptions Exception Flow 5.5.1 Exception Flow Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one.
Page 198: Exception Source Acceptance
Section 5 Exceptions SH7751 Group, SH7751R Group 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—the general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the...
Page 199: Figure 5.3 Example Of General Exception Acceptance Order
SH7751 Group, SH7751R Group Section 5 Exceptions Pipeline flow: TLB miss (data access) Instruction n Instruction n+1 General illegal instruction exception TLB miss (instruction access) Instruction n+2 Legend: Instruction fetch ID: Instruction decode Instruction n+3 EX: Instruction execution MA: Memory access...
Page 200: Exception Requests And Bl Bit
Section 5 Exceptions SH7751 Group, SH7751R Group 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, general exceptions and interrupts are accepted. When the BL bit in SR is 1 and a general exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their post-reset state, and the CPU branches to the same address as in a reset (H'A000 0000).
Page 201: Resets
SH7751 Group, SH7751R Group Section 5 Exceptions 5.6.1 Resets (1) Power-On Reset • Sources: ⎯ RESET pin low level ⎯ When the watchdog timer overflows while the WT/IT bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits.
Page 202: Table 5.3 Types Of Reset
Section 5 Exceptions SH7751 Group, SH7751R Group (2) Manual Reset • Sources: ⎯ MRESET pin low level and RESET pin high level ⎯ When a general exception other than a user break occurs while the BL bit is set to 1 in SR ⎯...
Page 203 SH7751 Group, SH7751R Group Section 5 Exceptions (3) H-UDI Reset • Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000.
Page 204 Section 5 Exceptions SH7751 Group, SH7751R Group (4) Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 205 SH7751 Group, SH7751R Group Section 5 Exceptions (5) Data TLB Multiple-Hit Exception • Source: Multiple UTLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 206: General Exceptions
Section 5 Exceptions SH7751 Group, SH7751R Group 5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 207 SH7751 Group, SH7751R Group Section 5 Exceptions (2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 208 Section 5 Exceptions SH7751 Group, SH7751R Group (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 209 SH7751 Group, SH7751R Group Section 5 Exceptions (4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible...
Page 210 Section 5 Exceptions SH7751 Group, SH7751R Group (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible •...
Page 211 SH7751 Group, SH7751R Group Section 5 Exceptions (6) Data Address Error • Sources: ⎯ Word data access from other than a word boundary (2n +1) ⎯ Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) ⎯...
Page 212 Section 5 Exceptions SH7751 Group, SH7751R Group (7) Instruction Address Error • Sources: ⎯ Instruction fetch from other than a word boundary (2n +1) ⎯ Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 •...
Page 213 SH7751 Group, SH7751R Group Section 5 Exceptions (8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'0000 0100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.
Page 214 Section 5 Exceptions SH7751 Group, SH7751R Group (9) General Illegal Instruction Exception • Sources: ⎯ Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD ⎯...
Page 215 SH7751 Group, SH7751R Group Section 5 Exceptions (10) Slot Illegal Instruction Exception • Sources: ⎯ Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD ⎯...
Page 216 Section 5 Exceptions SH7751 Group, SH7751R Group (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
Page 217 SH7751 Group, SH7751R Group Section 5 Exceptions (12) Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.
Page 218 Section 5 Exceptions SH7751 Group, SH7751R Group (13) User Breakpoint Trap • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'0000 0100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 219 SH7751 Group, SH7751R Group Section 5 Exceptions (14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR .
Page 220: Interrupts
Section 5 Exceptions SH7751 Group, SH7751R Group 5.6.3 Interrupts (1) NMI • Source: NMI pin edge detection • Transition address: VBR + H'0000 0600 • Transition operations: The PC and SR contents for the instruction at which this exception is accepted are saved in SPC and SSR.
Page 221 SH7751 Group, SH7751R Group Section 5 Exceptions (2) IRL Interrupts • Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit in SR is 0 (accepted at instruction boundary). • Transition address: VBR + H'0000 0600 •...
Page 222 Section 5 Exceptions SH7751 Group, SH7751R Group (3) Peripheral Module Interrupts • Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI, GPIO, DMAC, PCIC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary).
Page 223: Priority Order With Multiple Exceptions
SH7751 Group, SH7751R Group Section 5 Exceptions 5.6.4 Priority Order with Multiple Exceptions With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order.
Page 224: Usage Notes
Section 5 Exceptions SH7751 Group, SH7751R Group If the delay slot instruction has a second data transfer, two checks are performed in step b, as in 1 above. If the accepted exception (the highest-priority exception) is a delay slot instruction re- execution type exception, the branch instruction PR register write operation (PC →...
Page 225: Restrictions
SH7751 Group, SH7751R Group Section 5 Exceptions Restrictions 1. Restrictions on first instruction of exception handling routine ⎯ Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR + H'400, or VBR + H'600.
Page 226 Section 5 Exceptions SH7751 Group, SH7751R Group Page 172 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 227: Section 6 Floating-Point Unit
SH7751 Group, SH7751R Group Section 6 Floating-Point Unit Section 6 Floating-Point Unit Overview The floating-point unit (FPU) has the following features: • Conforms to IEEE754 standard • 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) • Two rounding modes: Round to Nearest and Round to Zero •...
Page 228: Figure 6.2 Format Of Double-Precision Floating-Point Number
Section 6 Floating-Point Unit SH7751 Group, SH7751R Group 52 51 Figure 6.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is E – 1 to E + 1.
Page 229: Non-Numbers (Nan)
SH7751 Group, SH7751R Group Section 6 Floating-Point Unit Table 6.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFFFFFF to H'7FC00000 H'7FFFFFFF FFFFFFFF to H'7FF80000 00000000 Quiet non-number H'7FBFFFFF to H'7F800001 H'7FF7FFFF FFFFFFFF to H'7FF00000 00000001 Positive infinity H'7F800000 H'7FF00000 00000000...
Page 230: Denormalized Numbers
Section 6 Floating-Point Unit SH7751 Group, SH7751R Group 23 22 11111111 Nxxxxxxxxxxxxxxxxxxxxxx N = 1: sNaN N = 0: qNaN Figure 6.3 Single-Precision NaN Bit Pattern An sNAN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point value.
Page 231: Registers
SH7751 Group, SH7751R Group Section 6 Floating-Point Unit Registers 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers, referenced by specifying FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0– XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0–FPR15_BANK0...
Page 232: Figure 6.4 Floating-Point Registers
Section 6 Floating-Point Unit SH7751 Group, SH7751R Group 7. Single-precision floating-point extended register matrix: XMTRX XMTRX comprises all 16 XF registers XMTRX = XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0 _BANK0 XMTRX FPR1_BANK0 FPR2_BANK0...
Page 233: Floating-Point Status/Control Register (Fpscr)
SH7751 Group, SH7751R Group Section 6 Floating-Point Unit 6.3.2 Floating-Point Status/Control Register (FPSCR) Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved.
Page 234: Floating-Point Communication Register (Fpul)
Section 6 Floating-Point Unit SH7751 Group, SH7751R Group • Flag: FPU exception flag field Invalid Division Overflow Underflow Inexact Error (E) Operation (V) by Zero (Z) Cause FPU exception Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12...
Page 235: Rounding
SH7751 Group, SH7751R Group Section 6 Floating-Point Unit Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC, FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL.
Page 236 Section 6 Floating-Point Unit SH7751 Group, SH7751R Group The FPSCR FPU exception cause field contains bits corresponding to all of above E, V, Z, O, U, and I, and the FPSCR flag and enable fields contain bits corresponding to V, Z, O, U, and I, but not E.
Page 237: Graphics Support Functions
In future version of SuperH RISC engine Family, the above error is guaranteed, but the same result as SH7751 Group is not guaranteed. FIPR FVm, FVn (m, n: 0, 4, 8, 12): Examples of the use of this instruction are given below.
Page 238: Pair Single-Precision Data Transfer
Section 6 Floating-Point Unit SH7751 Group, SH7751R Group FTRV XMTRX, FVn (n: 0, 4, 8, 12): Examples of the use of this instruction are given below. • Matrix (4 × 4) ⋅ vector (4): This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional).
Page 239: Usage Notes
SH7751 Group, SH7751R Group Section 6 Floating-Point Unit • FSCHG This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use and non-use of pair single-precision data transfer. Programming Note: When FPSCR.SZ = 1 and big-endian mode is used, FMOV can be used for a double-precision floating-point load or store.
Page 240: Setting Of Overflow Flag By Fipr Or Ftrv Instruction
Section 6 Floating-Point Unit SH7751 Group, SH7751R Group b. FPU Operation result: H'00800000 FPSCR: H'00041004 • Double-precision When FPSCR.RM = 00 (Round to Nearest) and FPSCR.PR = 1 (double-precision), and the FDIV instruction (H'001FFFFF FFFFFFFF / H'40000000 00000000) is executed.
Page 241: Sign Of Operation Result When Using Fipr Or Ftrv Instruction
SH7751 Group, SH7751R Group Section 6 Floating-Point Unit 6.7.3 Sign of Operation Result when Using FIPR or FTRV Instruction When two or more data items used in an operation by the FIPR or FTRV instruction are infinity, and all of the infinity items in the multiplication results have the same sign, the sign of the operation result may be incorrect.
Page 242 Section 6 Floating-Point Unit SH7751 Group, SH7751R Group Example: If the double-precision FSUB instruction (FSUB DR0, DR2) is executed with input data DR0 = H'C1F00000 80000000, DR2 = H'C4B250D2 0CC1FB74, and FPSCR = H'000C0001, the correct operation result is DR2 = H'C4B250D2 0CC1F973, and FPSCR.Flag.I and FPSCR.Cause.I should be set to 1.
Page 243: Section 7 Instruction Set
SH7751 Group, SH7751R Group Section 7 Instruction Set Section 7 Instruction Set Execution Environment PC: PC indicates the address of the instruction itself. Data sizes and data types: The SH-4 instruction set is implemented with 16-bit fixed-length instructions. The SH-4 can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64- bit) data sizes for memory access.
Page 244 Section 7 Instruction Set SH7751 Group, SH7751R Group T Bit: The T bit in the status register (SR) is used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is shown below.
Page 245: Addressing Modes
SH7751 Group, SH7751R Group Section 7 Instruction Set Addressing Modes Addressing modes and effective address calculation methods are shown in table 7.1. When a location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated into a physical address. If multiple virtual memory space systems are selected (MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 246 Section 7 Instruction Set SH7751 Group, SH7751R Group Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Rn) Effective address is register Rn contents with Byte: Rn + disp → EA indirect with 4-bit displacement disp added. After disp is...
Page 247 SH7751 Group, SH7751R Group Section 7 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative @(disp:8, PC) Effective address is PC+4 with 8-bit displacement Word: PC + 4 + disp × 2 → with disp added. After disp is zero-extended, it is...
Page 248 Section 7 Instruction Set SH7751 Group, SH7751R Group Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative disp:12 Effective address is PC+4 with 12-bit displacement PC + 4 + disp × 2 → Branch- disp added after being sign-extended and multiplied by 2.
Page 249: Instruction Set
SH7751 Group, SH7751R Group Section 7 Instruction Set Instruction Set Table 7.2 shows the notation used in the following SH instruction list. Table 7.2 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size...
Page 250: Table 7.3 Fixed-Point Transfer Instructions
Section 7 Instruction Set SH7751 Group, SH7751R Group Table 7.3 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit imm → sign extension → Rn #imm,Rn — — 1110nnnniiiiiiii (disp × 2 + PC + 4) → sign MOV.W @(disp,PC),Rn —...
Page 251 SH7751 Group, SH7751R Group Section 7 Instruction Set Instruction Operation Instruction Code Privileged T Bit R0 → (disp + GBR) MOV.B R0,@(disp,GBR) 11000000dddddddd — — R0 → (disp × 2 + GBR) MOV.W R0,@(disp,GBR) 11000001dddddddd — — R0 → (disp × 4 + GBR) MOV.L...
Page 252: Table 7.4 Arithmetic Operation Instructions
Section 7 Instruction Set SH7751 Group, SH7751R Group Table 7.4 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn + Rm → Rn Rm,Rn 0011nnnnmmmm1100 — — Rn + imm → Rn #imm,Rn 0111nnnniiiiiiii — — Rn + Rm + T → Rn, carry → T...
Page 253 SH7751 Group, SH7751R Group Section 7 Instruction Set Instruction Operation Instruction Code Privileged T Bit EXTS.W Rm,Rn Rm sign-extended from 0110nnnnmmmm1111 — — word → Rn EXTU.B Rm,Rn Rm zero-extended from 0110nnnnmmmm1100 — — byte → Rn EXTU.W Rm,Rn Rm zero-extended from 0110nnnnmmmm1101 —...
Page 254: Table 7.5 Logic Operation Instructions
Section 7 Instruction Set SH7751 Group, SH7751R Group Table 7.5 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn & Rm → Rn Rm,Rn 0010nnnnmmmm1001 — — R0 & imm → R0 #imm,R0 11001001iiiiiiii — — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + 11001101iiiiiiii —...
Page 255: Table 7.6 Shift Instructions
SH7751 Group, SH7751R Group Section 7 Instruction Set Table 7.6 Shift Instructions Instruction Operation Instruction Code Privileged T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 — LSB → Rn → T ROTR 0100nnnn00000101 — T ← Rn ← T ROTCL 0100nnnn00100100 —...
Page 256: Table 7.7 Branch Instructions
Section 7 Instruction Set SH7751 Group, SH7751R Group Table 7.7 Branch Instructions Instruction Operation Instruction Code Privileged T Bit When T = 0, disp × 2 + PC + label 10001011dddddddd — — 4 → PC When T = 1, nop...
Page 257: Table 7.8 System Control Instructions
SH7751 Group, SH7751R Group Section 7 Instruction Set Table 7.8 System Control Instructions Instruction Operation Instruction Code Privileged T Bit 0 → MACH, MACL CLRMAC 0000000000101000 — — 0 → S CLRS 0000000001001000 — — 0 → T CLRT 0000000000001000 —...
Page 258 Section 7 Instruction Set SH7751 Group, SH7751R Group Instruction Operation Instruction Code Privileged T Bit Delayed branch, SSR/SPC → 0000000000101011 Privileged — SR/PC 1 → S SETS 0000000001011000 — — 1 → T SETT 0000000000011000 — SLEEP Sleep or standby 0000000000011011 Privileged —...
Page 259: Table 7.9 Floating-Point Single-Precision Instructions
SH7751 Group, SH7751R Group Section 7 Instruction Set Table 7.9 Floating-Point Single-Precision Instructions Instructio Operation Instruction Code Privileged T Bit H'00000000 → FRn FLDI0 1111nnnn10001101 — — H'3F800000 → FRn FLDI1 1111nnnn10011101 — — FRm → FRn FMOV FRm,FRn 1111nnnnmmmm1100 —...
Page 260: Table 7.10 Floating-Point Double-Precision Instructions
Section 7 Instruction Set SH7751 Group, SH7751R Group Table 7.10 Floating-Point Double-Precision Instructions Instructio Operation Instruction Code Privileged T Bit FABS DRn & H'7FFF FFFF FFFF 1111nnn001011101 — — FFFF → DRn DRn + DRm → DRn FADD DRm,DRn 1111nnn0mmm00000 —...
Page 261: Usage Notes
SH7751 Group, SH7751R Group Section 7 Instruction Set Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit DRm → XDn FMOV DRm,XDn 1111nnn1mmm01100 — — XDm → DRn FMOV XDm,DRn 1111nnn0mmm11100 — — XDm → XDn...
Page 262 Section 7 Instruction Set SH7751 Group, SH7751R Group b. A TRAPA instruction or undefined instruction code H'FFFD in a cache-enabled area (U0, P0, P1, or P3 area) is executed. c. The four words of data following the TRAPA instruction or undefined instruction code H'FFFD mentioned in b.
Page 263 SH7751 Group, SH7751R Group Section 7 Instruction Set executed in 4xIck. The maximum number of instructions that can be executed in 2xIck or 4xIck is four or eight, respectively. Therefore, the affected codes are those occurring in “the four words (or eight words) of data following the instruction.”...
Page 264 Section 7 Instruction Set SH7751 Group, SH7751R Group Page 210 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 265: Section 8 Pipelining
SH7751 Group, SH7751R Group Section 8 Pipelining Section 8 Pipelining This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Core models other than this LSI.
Page 266: Figure 8.1 Basic Pipelines
Section 8 Pipelining SH7751 Group, SH7751R Group 1. General Pipeline • Instruction fetch • Instruction • Operation • Non-memory • Write-back decode data access • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline •...
Page 267: Figure 8.2 Instruction Execution Patterns
SH7751 Group, SH7751R Group Section 8 Pipelining 1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT,...
Page 268 Section 8 Pipelining SH7751 Group, SH7751R Group 10. OCBI: 1 issue cycle 11. OCBP, OCBWB: 1 issue cycle 12. MOVCA.L: 1 issue cycle 13. TRAPA: 7 issue cycles 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle 15. LDC to GBR: 3 issue cycles 16.
Page 269 SH7751 Group, SH7751R Group Section 8 Pipelining 19. LDC.L to SR: 4 issue cycles 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 21. STC.L from SGR: 3 issue cycles 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 23. STC.L from SGR: 3 issue cycles 24.
Page 270 Section 8 Pipelining SH7751 Group, SH7751R Group 31. STS.L from MACH/L: 1 issue cycle 32. LDS to FPSCR: 1 issue cycle 33. LDS.L to FPSCR: 1 issue cycle 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W (CPU) (FPU) 35.
Page 271 SH7751 Group, SH7751R Group Section 8 Pipelining 40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT 42. FIPR: 1 issue cycle 43. FTRV: 1 issue cycle Notes: : Cannot overlap a stage of the same kind, except when two instructions are executed in parallel.
Page 272: Parallel-Executability
Section 8 Pipelining SH7751 Group, SH7751R Group Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel.
Page 273 SH7751 Group, SH7751R Group Section 8 Pipelining 3. BR Group disp disp disp BF/S disp disp BT/S disp 4. LS Group FABS FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR) FABS FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn) FLDI0 FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn) FLDI1 FMOV.S FRm,@Rn MOV.L...
Page 274 Section 8 Pipelining SH7751 Group, SH7751R Group 5. FE Group FADD DRm,DRn FIPR FVm,FVn FSQRT FADD FRm,FRn FLOAT FPUL,DRn FSQRT FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL FCNVSD FPUL,DRn...
Page 275 SH7751 Group, SH7751R Group Section 8 Pipelining 6. CO Group AND.B #imm,@(R0,GBR) LDS Rm,FPSCR SR,Rn BRAF Rm,MACH SSR,Rn BSRF Rm,MACL VBR,Rn CLRMAC Rm,PR STC.L DBR,@-Rn CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L...
Page 276: Execution Cycles And Pipeline Stalling
Section 8 Pipelining SH7751 Group, SH7751R Group Table 8.2 Parallel-Executability 2nd Instruction Instruction Legend: O: Can be executed in parallel X: Cannot be executed in parallel Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: •...
Page 277 SH7751 Group, SH7751R Group Section 8 Pipelining The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction;...
Page 278 Section 8 Pipelining SH7751 Group, SH7751R Group point operation, never occurs. For example, when FADD follows FDIV with no dependency between floating-point registers, FADD is not stalled even if both instructions update the cause field of FPSCR. Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS.
Page 279: Figure 8.3 Examples Of Pipelined Execution
SH7751 Group, SH7751R Group Section 8 Pipelining (a) Serial execution: non-parallel-executable instructions 1 issue cycle SHAD R0,R1 EX-group SHAD and EX-group ADD R2,R3 cannot be executed in parallel. Therefore, next SHAD is issued first, and the following 1 stall cycle ADD is recombined with the next instruction.
Page 280 Section 8 Pipelining SH7751 Group, SH7751R Group (e) Flow dependency Zero-cycle latency The following instruction, ADD, is not R0,R1 stalled when executed after an instruction R2,R1 with zero-cycle latency, even if there is dependency. 1-cycle latency ADD and MOV.L are not executed in R2,R1 parallel, since MOV.L references the result...
Page 281 SH7751 Group, SH7751R Group Section 8 Pipelining (e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions R0,FPUL FLOAT FPUL,FR0 R1,FPUL FLOAT FPUL,FR1 Effectively 1-cycle latency for consecutive FTRC FR0,FPUL FTRC/STS instructions FPUL,R0 FTRC FR1,FPUL FPUL,R1 (f) Output dependency...
Page 282 Section 8 Pipelining SH7751 Group, SH7751R Group (h) Resource conflict ..........Latency 1 cycle/issue FDIV FR6,FR7 F1 stage locked for 1 cycle FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 1 stall cycle (F1 stage resource conflict) FIPR FV8,FV0 FADD FR15,FR4 1 stall cycle LDS.L @R15+,PR...
Page 283: Table 8.3 Execution Cycles
SH7751 Group, SH7751R Group Section 8 Pipelining Table 8.3 Execution Cycles Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Data EXTS.B Rm,Rn — — — transfer EXTS.W Rm,Rn — — — instructions EXTU.B...
Page 284 Section 8 Pipelining SH7751 Group, SH7751R Group Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Data MOV.W R0,@(disp,Rn) — — — transfer MOV.L Rm,@(disp,Rn) — — — instructions MOV.B Rm,@(R0,Rn) — —...
Page 285 SH7751 Group, SH7751R Group Section 8 Pipelining Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Fixed-point DIV0U — — — arithmetic DIV1 Rm,Rn — — — instructions DMULS.L Rm,Rn DMULU.L Rm,Rn —...
Page 286 Section 8 Pipelining SH7751 Group, SH7751R Group Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Shift ROTL — — — instructions ROTR — — — ROTCL — — — ROTCR — —...
Page 287 SH7751 Group, SH7751R Group Section 8 Pipelining Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles System — — — control CLRMAC instructions CLRS — — — CLRT — — — SETS —...
Page 288 Section 8 Pipelining SH7751 Group, SH7751R Group Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles System GBR,Rn — — — control Rp_BANK,Rn — — — instructions SR,Rn — — — SSR,Rn —...
Page 289 SH7751 Group, SH7751R Group Section 8 Pipelining Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Single- FABS — — — precision FADD FRm,FRn — — — floating- FCMP/EQ FRm,FRn — — —...
Page 290 Section 8 Pipelining SH7751 Group, SH7751R Group Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Double- FNEG — — — precision FSQRT (23, 24)/ floating- point instructions FSUB DRm,DRn (7, 8)/9 FTRC...
Page 291 SH7751 Group, SH7751R Group Section 8 Pipelining 4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and 1 for a zero displacement. 5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR.
Page 292: Usage Notes
Section 8 Pipelining SH7751 Group, SH7751R Group Usage Notes The following are additional notes on pipeline operation and the method of calculating the number of clock cycles. The number of states (I clock cycles) required for stages where an external bus access, etc., occurs may include an increased number of cycles, in addition to the number of memory access cycles set by the bus state controller (BSC), etc.
Page 293: Section 9 Power-Down Modes
SH7751 Group, SH7751R Group Section 9 Power-Down Modes Section 9 Power-Down Modes Overview In the power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 9.1.1 Types of Power-Down Modes The following power-down modes and functions are provided: •...
Page 294: Table 9.1 Status Of Cpu And Peripheral Modules In Power-Down Modes
Section 9 Power-Down Modes SH7751 Group, SH7751R Group Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes Status Power- On-chip Down Entering On-Chip Peripheral External Exiting Mode Condition Memory Modules Pins Memory Method • Interrupt Sleep SLEEP Operating Halted...
Page 295: Register Configuration
SH7751 Group, SH7751R Group Section 9 Power-Down Modes 9.1.2 Register Configuration Table 9.2 shows the registers used for power-down mode control. Table 9.2 Power-Down Mode Registers Area 7 Access Name Abbreviation Initial Value P4 Address Address Size Standby control STBCR...
Page 296: Register Descriptions
Section 9 Power-Down Modes SH7751 Group, SH7751R Group Register Descriptions 9.2.1 Standby Control Register (STBCR) The standby control register (STBCR) is an 8-bit readable/writable register that specifies the power-down mode status. It is initialized to H'00 by a power-on reset via the RESET pin or due to watchdog timer overflow.
Page 297 SH7751 Group, SH7751R Group Section 9 Power-Down Modes Bit 4—Module Stop 4 (MSTP4): Specifies stopping of the clock supply to the DMAC among the on-chip peripheral modules. The clock supply to the DMAC is stopped when the MSTP4 bit is set to 1.
Page 298: Peripheral Module Pin High Impedance Control
Section 9 Power-Down Modes SH7751 Group, SH7751R Group Bit 0—Module Stop 0 (MSTP0): Specifies stopping of the clock supply to serial communication interface channel 1 (SCI) among the on-chip peripheral modules. The clock supply to the SCI is stopped when the MSTP0 bit is set to 1.
Page 299: Standby Control Register 2 (Stbcr2)
SH7751 Group, SH7751R Group Section 9 Power-Down Modes 9.2.4 Standby Control Register 2 (STBCR2) Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via the RESET pin or due to watchdog timer overflow.
Page 300: Clock Stop Register 00 (Clkstp00)
Section 9 Power-Down Modes SH7751 Group, SH7751R Group Bit 0—Module Stop 5 (MSTP5): Specifies stopping of the clock supply to the user break controller (UBC) among the on-chip peripheral modules. See section 20.6, User Break Controller Stop Function for how to set the clock supply.
Page 301: Clock Stop Clear Register 00 (Clkstpclr00)
SH7751 Group, SH7751R Group Section 9 Power-Down Modes Bit 1—Clock Stop 1 (CSTP1): Specifies stopping of the peripheral clock supply to timer unit (TMU) channels 3 and 4. Bit 1: CSTP1 Description Peripheral clock is supplied to TMU channels 3 and 4...
Page 302: Sleep Mode
Section 9 Power-Down Modes SH7751 Group, SH7751R Group Sleep Mode 9.3.1 Transition to Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained.
Page 303: Exit From Deep Sleep Mode
SH7751 Group, SH7751R Group Section 9 Power-Down Modes Note: * Terminate DMA transfers prior to making the transition to deep sleep mode. If you make a transition to deep sleep mode while DMA transfers are in progress, the results of those transfers cannot be guaranteed.
Page 304: Exit From Standby Mode
Section 9 Power-Down Modes SH7751 Group, SH7751R Group Table 9.4 State of Registers in Standby Mode Registers That Retain Module Initialized Registers Their Contents Interrupt controller — All registers User break controller — All registers Bus state controller — All registers On-chip oscillation circuits —...
Page 305: Clock Pause Function
SH7751 Group, SH7751R Group Section 9 Power-Down Modes The phase of the CKIO pin clock output may be unstable immediately after an interrupt is detected, until standby mode is exited. Notes: 1. Only when the RTC clock (32.768 kHz) is operating (see section 19.2.2, IRL Interrupts), standby mode can be exited by means of IRL3–IRL0 (when the IRL3–...
Page 306: Exit From Module Standby Function
Section 9 Power-Down Modes SH7751 Group, SH7751R Group Description CSTP2 Peripheral clock is supplied to PCIC Peripheral clock supply to PCIC is stopped CSTP1 Peripheral clock is supplied to TMU channels 3 and 4 Peripheral clock supply to TMU channels 3 and 4 is stopped...
Page 307: Hardware Standby Mode
SH7751 Group, SH7751R Group Section 9 Power-Down Modes The module standby function is not exited by means of a power-on reset via the RESET pin or a power-on reset caused by watchdog timer overflow. Hardware Standby Mode 9.8.1 Transition to Hardware Standby Mode Setting the CA pin level low effects a transition to hardware standby mode.
Page 308: Usage Notes
Section 9 Power-Down Modes SH7751 Group, SH7751R Group 9.8.3 Usage Notes 1. The CA pin level must be kept high when the RTC power supply is started (figure 9.15). 2. On the SH7751R, supply power to the V , and V power supply −...
Page 309: In Reset
SH7751 Group, SH7751R Group Section 9 Power-Down Modes 9.9.1 In Reset Power-On Reset CKIO PLL stabilization time RESET Normal Reset Normal STATUS 0–30 Bcyc 0–5 Bcyc Figure 9.1 STATUS Output in Power-On Reset Manual Reset CKIO RESET (High) Must be asserted for...
Page 310: In Exit From Standby Mode
Section 9 Power-Down Modes SH7751 Group, SH7751R Group 9.9.2 In Exit from Standby Mode Standby → Interrupt Oscillation stops Interrupt request WDT overflow CKIO WDT count Normal Standby Normal STATUS Figure 9.3 STATUS Output in Standby → Interrupt Sequence Standby → Power-On Reset...
Page 311: In Exit From Sleep Mode
SH7751 Group, SH7751R Group Section 9 Power-Down Modes Standby → Manual Reset Oscillation stops Reset CKIO RESET (High) MRESET * Normal Standby Undefined Reset Normal STATUS 0–30 Bcyc 0–20 Bcyc Note: * When standby mode is exited by means of a manual reset, a WDT count is not performed.
Page 312: Figure 9.7 Status Output In Sleep → Power-On Reset Sequence
Section 9 Power-Down Modes SH7751 Group, SH7751R Group Sleep → Power-On Reset Reset CKIO RESET * Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: 1. When sleep mode is exited by means of a power-on reset, hold RESET low for the oscillation stabilization time.
Page 313: Figure 9.8 Status Output In Sleep → Manual Reset Sequence
SH7751 Group, SH7751R Group Section 9 Power-Down Modes Sleep → Manual Reset Reset CKIO RESET (High) MRESET * Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–30 Bcyc Note: * Hold MRESET low until STATUS = reset. Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence R01UH0457EJ0301 Rev.
Page 314: In Exit From Deep Sleep Mode
Section 9 Power-Down Modes SH7751 Group, SH7751R Group 9.9.4 In Exit from Deep Sleep Mode Deep Sleep → Interrupt Interrupt request CKIO Sleep STATUS Normal Normal Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence Deep Sleep → Power-On Reset...
Page 315: Figure 9.11 Status Output In Deep Sleep → Manual Reset Sequence
SH7751 Group, SH7751R Group Section 9 Power-Down Modes Deep Sleep → Manual Reset Reset CKIO RESET (High) MRESET * Normal Reset Normal STATUS Sleep 0–30 Bcyc 0–30 Bcyc Note: * Hold MRESET low until STATUS = reset. Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence R01UH0457EJ0301 Rev.
Page 316: Hardware Standby Mode Timing
Section 9 Power-Down Modes SH7751 Group, SH7751R Group 9.9.5 Hardware Standby Mode Timing Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode. The CA pin level must be kept low while in hardware standby mode.
Page 317: Figure 9.13 Hardware Standby Mode Timing (When Ca = Low In Wdt Operation)
SH7751 Group, SH7751R Group Section 9 Power-Down Modes Interrupt request WDT overflow CKIO RESET (High) Standby * Standby Normal STATUS 0–10 Bcyc WDT count Note: * High impedance when STBCR2. STHZ = 0 Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation)
Page 318: Usage Notes
Section 9 Power-Down Modes SH7751 Group, SH7751R Group DD-RTC Power-on oscillation settling time Min 0s RESET Note: * V DD-PLL1/2 DD-CPG Figure 9.15 Timing When VDD-RTC Power Is Off → On 9.10 Usage Notes 9.10.1 Note on Current Consumption After a power-on reset, the current consumption may exceed the maximum value for sleep mode or standby mode during the period until one or more of the arithmetic operation or floating-point operation instructions listed below is executed.
Page 319 SH7751 Group, SH7751R Group Section 9 Power-Down Modes Example: To reduce the effect on FPSCR, arrange the following two instructions starting at H'A0000000. Address Instruction String H'A0000000 FLDI1 H'A0000002 FADD FR0, FR0 ; FLDI1 FR0 loads 1 into FR0, ; so the cause and flag bits of FPSCR are not set to 1.
Page 320 Section 9 Power-Down Modes SH7751 Group, SH7751R Group Page 266 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 321: Section 10 Clock Oscillation Circuits
SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits Section 10 Clock Oscillation Circuits 10.1 Overview The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer (WDT). The CPG generates the clocks supplied inside the processor and performs power-down mode control.
Page 322 Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group The WDT has the following features • Can be used to secure clock stabilization time Used when exiting standby mode or a temporary standby state when the clock frequency is changed.
Page 323: Overview Of Cpg
SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits 10.2 Overview of CPG 10.2.1 Block Diagram of CPG Figures 10.1(1) and 10.1(2) show a block diagram of the CPG in the SH7751 and SH7751R. Oscillator circuit Frequency divider 2 ×1 PLL circuit 1 ×1/2...
Page 324: Figure 10.1 (2) Block Diagram Of Cpg (Sh7751R)
Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group Oscillator circuit Frequency divider 2 ×1 PLL circuit 1 ×1/2 ×6 ×1/3 ×12 CPU clock (Ick) ×1/4 cycle Icyc ×1/6 ×1/8 Crystal XTAL oscillation Peripheral module circuit clock (Pck) cycle Pcyc...
Page 325 SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits The function of each of the CPG blocks is described below. PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or crystal oscillation circuit by 6 (SH7751 and SH7751R) or 12 (SH7751R). Starting and stopping is controlled by a frequency control register setting.
Page 326: Cpg Pin Configuration
Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group 10.2.2 CPG Pin Configuration Table 10.1 shows the CPG pins and their functions. Table 10.1 CPG Pins Pin Name Abbreviation Function Mode control pins Input Set clock operating mode Crystal I/O pins...
Page 327: Clock Operating Modes
SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits 10.3 Clock Operating Modes Tables 10.3 (1) and 10.3 (2) show the clock operating modes corresponding to various combinations of mode control pin (MD2–MD0) settings (initial settings such as the frequency division ratio).
Page 328: Table 10.4 Frqcr Settings And Internal Clock Frequencies
Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group 2. For the ranges input clock frequency, see the description of the EXTAL clock input frequency (f ) and the CKIO clock output (f ) in section 23.3.1, Clock and Control Signal Timing.
Page 329: Cpg Register Description
SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits 10.4 CPG Register Description 10.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock, and peripheral module clock frequency division ratios.
Page 330 Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group Bit 10—PLL Circuit 1 Enable (PLL1EN): Specifies whether PLL circuit 1 is on or off. Bit 10: PLL1EN Description PLL circuit 1 is not used PLL circuit 1 is used (Initial value) Bit 9—PLL Circuit 2 Enable (PLL2EN): Specifies whether PLL circuit 2 is on or off.
Page 331 SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits Bits 5 to 3—Bus Clock Frequency Division Ratio (BFC): These bits specify the bus clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency.
Page 332: Changing The Frequency
Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group 10.5 Changing the Frequency There are two methods of changing the internal clock frequency: by changing stopping and starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases, control is performed by software by means of the frequency control register.
Page 333: Changing Bus Clock Division Ratio (When Pll Circuit 2 Is On)
SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On) If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2 oscillation stabilization time is required.
Page 334: Output Clock Control
Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group 10.6 Output Clock Control The CKIO pin can be switched between clock output and a high-impedance state by means of the CKOEN bit in the FRQCR register. When the CKIO pin goes to the high-impedance state, it is pulled up.
Page 335: Register Configuration
SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits 10.7.2 Register Configuration The WDT has the two registers summarized in table 10.5. These registers control clock selection and timer mode switching. Table 10.5 WDT Registers Initial Area 7 Name Abbreviation R/W...
Page 336: Watchdog Timer Control/Status Register (Wtcsr)
Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group 10.8.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register containing bits for selecting the count clock and timer mode, and overflow flags. WTCSR is initialized to H'00 only by a power-on reset via the RESET pin. It retains its value in an internal reset due to WDT overflow.
Page 337 SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. Bit 4: WOVF Description No overflow (Initial value) WTCNT has overflowed in watchdog timer mode Bit 3—Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in...
Page 338: Notes On Register Access
Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group 10.8.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) differ from other registers in being more difficult to write to. The procedure for writing to these registers is given below.
Page 339: Using The Wdt
SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits 10.9 Using the WDT 10.9.1 Standby Clearing Procedure The WDT is used when clearing standby mode by means of an NMI or other interrupt. The procedure is shown below. (As the WDT does not operate when standby mode is cleared with a reset, the RESET pin should be held low until the clock stabilizes.)
Page 340: Using Watchdog Timer Mode
Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group 6. When re-setting WTCNT immediately after modifying the frequency control register (FRQCR), first read the counter and confirm that its value is as described in step 5 above. 10.9.3 Using Watchdog Timer Mode 1.
Page 341: Notes On Board Design
SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits 10.10 Notes on Board Design When Using a Crystal Resonator: Place the crystal resonator and capacitors close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, ensure that no other signal lines cross the signal lines for these pins.
Page 342: Figure 10.5 Points For Attention When Using Pll Oscillator Circuit
Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group When Using a PLL Oscillator Circuit: Separate VDD−CPG and VSS−CPG from the other VDD and VSS lines at the board power supply source, and insert resistors RCB and RB, and decoupling capacitors CPB and CB, close to the pins.
Page 343: Usage Notes
SH7751 Group, SH7751R Group Section 10 Clock Oscillation Circuits 10.11 Usage Notes 10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7751 Only) Under certain conditions the on-chip watchdog timer (WDT) may trigger an invalid manual reset. Conditions Under which Problem Occurs: The on-chip WDT triggers an invalid manual reset when all of the following four conditions are satisfied.
Page 344 Section 10 Clock Oscillation Circuits SH7751 Group, SH7751R Group Page 290 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 345: Section 11 Realtime Clock (Rtc)
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) Section 11 Realtime Clock (RTC) 11.1 Overview This LSI includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillation circuit for use by the RTC. 11.1.1 Features The RTC has the following features.
Page 346: Block Diagram
Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the RTC. RTCCLK RESET, STBY, etc 16.384 kHz RTC operation RTC crystal 32.768 kHz Prescaler oscillation circuit control unit 128 Hz...
Page 347: Pin Configuration
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) 11.1.3 Pin Configuration Table 11.1 shows the RTC pins. Table 11.1 RTC Pins Pin Name Abbreviation I/O Function RTC oscillation circuit EXTAL2 Input Connects crystal to RTC oscillation circuit crystal pin...
Page 348 Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group Initialization Abbrevia- Power- Manual Standby Initial Area 7 Access Name tion On Reset Reset Mode Value P4 Address Address Size Month RMONCN R/W Counts Counts Counts Undefined H'FFC80018 H'1FC80018 8 counter...
Page 349: Register Descriptions
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) 11.2 Register Descriptions 11.2.1 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read.
Page 350: Second Counter (Rseccnt)
Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group 11.2.2 Second Counter (RSECCNT) RSECCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded second value in the RTC. It counts on the carry (transition of the R69CNT.1Hz bit from 0 to 1) generated once per second by the 64 Hz counter.
Page 351: Hour Counter (Rhrcnt)
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) 11.2.4 Hour Counter (RHRCNT) RHRCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded hour value in the RTC. It counts on the carry generated once per hour by the minute counter.
Page 352: Day Counter (Rdaycnt)
Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group Day-of-week code Day of week 11.2.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter.
Page 353: Year Counter (Ryrcnt)
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) Bits 7 to 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: — — — 10-month 1-month units...
Page 354: Second Alarm Register (Rsecar)
Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group 11.2.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value.
Page 355: Hour Alarm Register (Rhrar)
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) 11.2.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value.
Page 356: Day Alarm Register (Rdayar)
Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group Bits 6 to 3 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: — — — — Day-of-week code...
Page 357: Month Alarm Register (Rmonar)
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) 11.2.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD- coded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value.
Page 358 Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group Bit 7—Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again.
Page 359: Rtc Control Register 2 (Rcr2)
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values.
Page 360 Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated. Bit 7: PEF Description Interrupt is not generated at interval specified by bits PES2–PES0...
Page 361 SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) Bit 2—30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute.
Page 362: Rtc Control Register (Rcr3) And Year-Alarm Register (Ryrar) (Sh7751R Only)
Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group 11.2.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR) (SH7751R Only) RCR3 and RYRAR are readable/writable registers. RYRAR is the alarm register for the RTC's BCD-coded year-value counter RYRCNT. When the YENB bit of RCR3 is set to 1, the RYRCNT value is compared with the RYRAR value.
Page 363: Operation
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) 11.3 Operation Examples of the use of the RTC are shown below. 11.3.1 Time Setting Procedures Figure 11.2 shows examples of the time setting procedures. Set RCR2.RESET to 1 Stop clock Clear RCR2.START to 0...
Page 364 Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group The procedure for setting the time while the clock is running is shown in figure 11.2 (b). This method is useful for modifying only certain counter values (for example, only the second data or hour data).
Page 365: Time Reading Procedures
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) 11.3.2 Time Reading Procedures Figure 11.3 shows examples of the time reading procedures. Clear RCR1.CIE to 0 Disable carry interrupts Clear RCR1.CF to 0 Clear carry flag (Write 1 to RCR1.AF so that alarm flag...
Page 366: Alarm Function
Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group 11.3 (a), and the procedure using carry interrupts in figure 11.3 (b). The method without using interrupts is normally used to keep the program simple. 11.3.3 Alarm Function The use of the alarm function is illustrated in figure 11.4.
Page 367: Interrupts
SH7751 Group, SH7751R Group Section 11 Realtime Clock (RTC) 11.4 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1.
Page 368: Figure 11.5 Example Of Crystal Oscillation Circuit Connection
Section 11 Realtime Clock (RTC) SH7751 Group, SH7751R Group This LSI EXTAL2 VDD-RTC XTAL2 VSS-RTC XTAL Noise filter 3.3 V Notes: 1. Select either the C or C side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc.
Page 369: Section 12 Timer Unit (Tmu)
SH7751 Group, SH7751R Group Section 12 Timer Unit (TMU) Section 12 Timer Unit (TMU) 12.1 Overview This LSI includes an on-chip 32-bit timer unit (TMU) comprising five 32-bit timer channels (channels 0 to 4). 12.1.1 Features The TMU has the following features.
Page 370: Block Diagram
Section 12 Timer Unit (TMU) SH7751 Group, SH7751R Group 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. TICPI2 TUNI0,1 Pck/4, 16, 64 * RESET, STBY, TUNI2 TCLK RTCCLK TUNI3, TUNI4 etc. TCLK Prescaler operation control unit...
Page 371: Register Configuration
SH7751 Group, SH7751R Group Section 12 Timer Unit (TMU) 12.1.4 Register Configuration Table 12.2 summarizes the TMU registers. Table 12.2 TMU Registers Initialization Power- Stand- Chan- Abbre- Manual Area 7 Access Name viation R/W Reset Reset Mode Initial Value P4 Address...
Page 372: Register Descriptions
Section 12 Timer Unit (TMU) SH7751 Group, SH7751R Group Initialization Power- Stand- Chan- Abbre- Manual Area 7 Access Name viation R/W Reset Reset Mode Initial Value P4 Address Address Size Timer TCOR3 R/W Ini- Held Held H'FFFFFFFF H'FE100008 H'1E100008 32...
Page 373: Timer Start Register (Tstr)
SH7751 Group, SH7751R Group Section 12 Timer Unit (TMU) Bit 0—Timer Clock Pin Control (TCOE): Specifies whether timer clock pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin.
Page 374: Timer Start Register 2 (Tstr2)
Section 12 Timer Unit (TMU) SH7751 Group, SH7751R Group Bit 1—Counter Start 1 (STR1): Specifies whether timer counter 1 (TCNT1) is operated or stopped. Bit 1: STR1 Description TCNT1 count operation is stopped (Initial value) TCNT1 performs count operation Bit 0—Counter Start 0 (STR0): Specifies whether timer counter 0 (TCNT0) is operated or stopped.
Page 375: Timer Constant Registers (Tcor)
SH7751 Group, SH7751R Group Section 12 Timer Unit (TMU) Bit 0—Counter Start 3 (STR3): Specifies whether timer counter 3 (TCNT3) is operated or stopped. Bit 0: STR3 Description TCNT3 count operation is stopped (Initial value) TCNT3 performs count operation 12.2.4 Timer Constant Registers (TCOR) The TCOR registers are 32-bit readable/writable registers.
Page 376: Timer Control Registers (Tcr)
Section 12 Timer Unit (TMU) SH7751 Group, SH7751R Group The TCNT registers in channels 3 and 4 are initialized to H'FFFFFFFF by a power-on reset, but are not initialized and retain their contents by a manual reset or in standby mode.
Page 377 SH7751 Group, SH7751R Group Section 12 Timer Unit (TMU) 1. Channel 0 and 1 TCR bit configuration Bit: — — — — — — — Initial value: R/W: Bit: — — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value: R/W: 2.
Page 378 Section 12 Timer Unit (TMU) SH7751 Group, SH7751R Group Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)—Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0.
Page 379 SH7751 Group, SH7751R Group Section 12 Timer Unit (TMU) The TCNT2 value is set in TCPR2 only when the TCR2.ICPF bit is 0. When the TCR2.ICPF bit is 1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer request is generated regardless of the value of the TCR2.ICPF bit.
Page 380: Input Capture Register 2 (Tcpr2)
Section 12 Timer Unit (TMU) SH7751 Group, SH7751R Group Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2–TPSC0): In channels 0 to 2, these bits select the TCNT count clock. When the on-chip RTC output clock is selected as the count clock for a channel, that channel can operate even in module standby mode.
Page 381: Operation
SH7751 Group, SH7751R Group Section 12 Timer Unit (TMU) 12.3 Operation Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32- bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting.
Page 382: Figure 12.2 Example Of Count Operation Setting Procedure
Section 12 Timer Unit (TMU) SH7751 Group, SH7751R Group Operation selection Select count clock Underflow interrupt generation setting When input capture function is used Input capture interrupt generation setting Timer constant register setting Set initial timer counter value Start count Note: When an interrupt is generated, clear the source flag in the interrupt handler.
Page 383: Figure 12.3 Tcnt Auto-Reload Operation
SH7751 Group, SH7751R Group Section 12 Timer Unit (TMU) Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation. TCNT value TCOR value set in TCNT on underflow TCOR H'00000000 Time STR0–STR4 Figure 12.3 TCNT Auto-Reload Operation TCNT Count Timing: •...
Page 384: Input Capture Function
Section 12 Timer Unit (TMU) SH7751 Group, SH7751R Group • Operating on external clock In channels 0 to 2, external clock pin (TCLK) input can be selected as the timer clock by means of the TPSC2–TPSC0 bits in TCR. The detected edge (rising, falling, or both edges) can be selected with the CKEG1 and CKEG0 bits in TCR.
Page 385: Figure 12.7 Operation Timing When Using Input Capture Function
SH7751 Group, SH7751R Group Section 12 Timer Unit (TMU) 4. Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK signal is to be used to set the timer counter (TCNT) value in the input capture register (TCPR2).
Page 386: Interrupts
Section 12 Timer Unit (TMU) SH7751 Group, SH7751R Group 12.4 Interrupts There are six TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used). Underflow interrupts are generated on channels 0 to 4, and input capture interrupts on channel 2 only.
Page 387: Tcnt Register Reads
SH7751 Group, SH7751R Group Section 12 Timer Unit (TMU) 12.5.2 TCNT Register Reads When performing a TCNT register read, processing for synchronization with the timer count operation is performed. If a timer count operation and register read processing are performed simultaneously, the TCNT counter value prior to the count-down operation is read by means of the synchronization processing.
Page 388 Section 12 Timer Unit (TMU) SH7751 Group, SH7751R Group Page 334 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 389: Section 13 Bus State Controller (Bsc)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Section 13 Bus State Controller (BSC) 13.1 Overview The functions of the bus state controller (BSC) include division of the external memory space, and output of control signals in accordance with various types of memory and bus interface specifications.
Page 390 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group ⎯ DRAM control signal timing can be controlled by register settings ⎯ Consecutive accesses to the same row address Connectable area: 3 Settable bus widths: 32, 16 • Synchronous DRAM interface ⎯...
Page 391: Block Diagram
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the BSC. interface WCR1 Wait control unit WCR2 WCR3 BCR1 CS6–CS0 Area CE2A–CE2B control unit BCR2 BCR3 * RD/WR WE3–WE0...
Page 392: Pin Configuration
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group 13.1.3 Pin Configuration Table 13.1 shows the BSC pin configuration. Table 13.1 BSC Pins Name Signals Description Address bus A25–A0 Address output Data bus D31–D0 Data input/output Bus cycle start...
Page 393 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Name Signals Description CAS0/DQM0 When setting DRAM interface: CAS signal for Column address strobe 0 D7–D0 When setting synchronous DRAM interface: selection signal for D7–D0 CAS1/DQM1 When setting DRAM interface: CAS signal for...
Page 394: Register Configuration
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Notes: 1. MD3/CE2A input/output switching is performed by BCR1.A56PCM. Output is selected when BCR1.A56PCM = 1. 2. MD4/CE2B input/output switching is performed by BCR1.A56PCM. Output is selected when BCR1.A56PCM = 1.
Page 395: Overview Of Areas
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.1.5 Overview of Areas Space Divisions: The architecture of this LSI provides a 32-bit virtual address space. The virtual address space is divided into five areas according to the upper address value. External memory space comprises a 29-bit address space, divided into eight areas.
Page 396: Table 13.3 External Memory Space Map
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Table 13.3 External Memory Space Map External Connectable Settable Bus Access Area Addresses Size Memory Widths Size H'00000000– 64 Mbytes SRAM 8, 16, 32* 8, 16, 32, H'03FFFFFF bits, Burst ROM...
Page 397: Figure 13.3 External Memory Space Allocation
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 6. A 64-bit access size applies only to transfer by the DMAC (CHCRn.TS = 000). In the case of access to external memory by means of FMOV (FPSCR.SZ = 1), two 32-bit access size transfers are performed.
Page 398: Pcmcia Support
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group interface is used, a bus width of 16, or 32 bits can be selected with the memory control register (MCR). For the synchronous DRAM interface, set a bus width of 32 bit in the MCR register.
Page 399: Table 13.5 Pcmcia Support Interfaces
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Table 13.5 PCMCIA Support Interfaces IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name I/O Function Name I/O Function LSI Pin Ground Ground — I/O Data I/O Data...
Page 400 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name I/O Function Name I/O Function LSI Pin Address Address Address Address I/O Data I/O Data I/O Data I/O Data...
Page 401 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name I/O Function Name I/O Function LSI Pin Reserved Reserved — RESET Reset RESET Reset Output from port WAIT WAIT...
Page 402: Register Descriptions
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group 13.2 Register Descriptions 13.2.1 Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus cycle status, etc., of each area.
Page 403 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bit 31—Endian Flag (ENDIAN): Samples the value of the endian specification external pin (MD5) in a power-on reset by means of the RESET pin. The endian mode of all spaces is determined by this bit.
Page 404 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bit 26—Data pin Pullup Resistor Control (DPUP): Controls the pullup resistance of the data pins (D31 to D0). It is initialized at a power-on reset. The pins are not pulled up when access is performed or when the bus is released, even if the ON setting is selected.
Page 405 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bit 20—Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an MPX interface is set. This bit is initialized by a power-on reset. Bit 20: A4MBC Description...
Page 406 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bit 15—High Impedance Control (HIZMEM): Specifies the state of address and other signals (A[25:0], BS, CSn, RD/WR, CE2A, CE2B) in standby mode. Bit 15: HIZMEM Description The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B signals go to high-...
Page 407 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bits 13 to 11—Area 0 Burst ROM Control (A0BST2–A0BST0): These bits specify whether burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the number of accesses in a burst.
Page 408 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 10 to 8—Area 5 Burst Enable (A5BST2–A5BST0): These bits specify whether burst ROM interface is used in area 5. When burst ROM interface is used, they also specify the number of accesses in a burst.
Page 409 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM interface is used in area 6. When burst ROM is used, they also specify the number of accesses in a burst.
Page 410 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as SRAM interface.
Page 411: Bus Control Register 2 (Bcr2)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 32-bit readable/writable register that specifies the bus width for each area, and whether a 16-bit port is used.
Page 412 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 2n + 1, 2n—Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify the bus width of area n (n = 1 to 6). (Bit 0): PORTEN Bit 2n + 1: AnSZ1...
Page 413: Bus Control Register 3 (Bcr3) (Sh7751R Only)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.2.3 Bus Control Register 3 (BCR3) (SH7751R Only) Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of either the MPX interface or the SRAM interface and specifies the burst length when the synchronous DRAM interface is used.
Page 414 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 14 and 13⎯MPX-Interface Specification for Area 1 and 4 (A1MPX, A4MPX): These bits specify the types of memory connected to areas 1 and 4. These settings are validated by MEMMODE.
Page 415: Bus Control Register 4 (Bcr4) (Sh7751R Only)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.2.4 Bus Control Register 4 (BCR4) (SH7751R Only) Bus control register 4 (BCR4) is a register that enables asynchronous input for pins corresponding to individual bits. The BCR4 register is a 32-bit readable/writable register. It is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 416: Figure 13.4 Example Of Rdy Sampling Timing At Which Bcr4 Is Set
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 4 to 0—Asynchronous Input: These bits enable asynchronous input for the corresponding pins. Bit 4–0: ASYNCn Description Corresponding pin is synchronous input with respect to CKIO (Initial value) Asynchronous input with respect to CKIO is enabled for corresponding pin...
Page 417: Wait Control Register 1 (Wcr1)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.2.5 Wait Control Register 1 (WCR1) Wait control register 1 (WCR1) is a 32-bit readable/writable register that specifies the number of idle state insertion cycles for each area. With some kinds of memory, data bus drive does not go off immediately after the read signal from off-chip goes off.
Page 418 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 30 to 28— DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2– DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when switching from a DACK device to another space, or from a read access to a write access on the same device.
Page 419: Table 13.6 Idle Insertion Between Accesses
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Table 13.6 Idle Insertion between Accesses Following Cycle Same Different Same Area Different Area Area Area Read Write Read Write Preceding Address Address Cycle CPU DMA CPU DMA CPU DMA...
Page 420: Wait Control Register 2 (Wcr2)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group 13.2.6 Wait Control Register 2 (WCR2) Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of wait states to be inserted for each area. It also specifies the data access pitch when performing burst memory access.
Page 421 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bits 31 to 29—Area 6 Wait Control (A6W2–A6W0): These bits specify the number of wait states to be inserted for area 6. For the case where an MPX interface setting is made, see table 13.7.
Page 422 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait states to be inserted for area 5. For the case where an MPX interface setting is made, see table 13.7.
Page 423 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait states to be inserted for area 4. For the case where an MPX interface setting is made, see table 13.7.
Page 424 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group • When DRAM or Synchronous DRAM Interface is Set* Note: * External wait input is always ignored Description DRAM CAS Synchronous DRAM CAS Latency Cycles Bit 15: A3W2 Bit 14: A3W1...
Page 425 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) • When Synchronous DRAM Interface is Set * Description Synchronous DRAM CAS Latency Cycles Bit 11: A2W2 Bit 10: A2W1 Bit 9: A2W0 Inhibited Inhibited Inhibited Notes: 1. External wait input is always ignored 2.
Page 426 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait states to be inserted for area 0. For the case where an MPX interface setting is made, see table 13.7.
Page 427: Table 13.7 When Mpx Interface Is Set (Areas 0 To 6)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Table 13.7 When MPX Interface Is Set (Areas 0 to 6) Description Inserted Wait States 1st Data 2nd Data RDY Pin Onward AnW2 AnW1 AnW0 Read Write Enabled Enabled Enabled...
Page 428: Wait Control Register 3 (Wcr3)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group 13.2.7 Wait Control Register 3 (WCR3) Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles inserted in the setup time from the address until assertion of the write strobe, and the data hold time from negation of the strobe, for each area.
Page 429 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles inserted in the setup time from the address until assertion of the read/write strobe. Valid only for...
Page 430: Memory Control Register (Mcr)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group 13.2.8 Memory Control Register (MCR) The memory control register (MCR) is a 32-bit readable/writable register that specifies RAS and CAS timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address multiplexing, and refresh control.
Page 431 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bit 31—RAS Down (RASD): Sets RAS down mode. When RAS down mode is used, set BE to 1. Do not set RAS down mode in slave mode or when areas 2 and 3 are both designated as synchronous DRAM interface.
Page 432 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bit 23—CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set. Bit 23: TCAS CAS Negation Period (Initial value) Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the DRAM interface is selected, these bits specify the minimum number of cycles until RAS is asserted again after being negated.
Page 433 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bits 15 to 13—Write Precharge Delay (TRWL2–TRWL0): These bits set the synchronous DRAM write precharge delay time. In auto-precharge mode, they specify the time until the next bank active command is issued after a write cycle. After a write cycle, the next active command is not issued for a period set by TPC[2:0] and TRWL[2:0] bits*.
Page 434 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 12 to 10—CAS-Before-RAS Refresh RAS Assertion Period (TRAS2–TRAS0): When the DRAM interface is set, these bits set the RAS assertion period in CAS-before-RAS refreshing. When the synchronous DRAM interface is set, the bank active command is not issued for a period set by TPC[2:0] and TRAS[2:0] bits after an auto-refresh command is issued.
Page 435 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and synchronous DRAM. This setting has priority over the BCR2 register setting. Description Bit 8: SZ1...
Page 436 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group • For Synchronous DRAM Interface: Example Synchronous DRAM AMXEXT Configurations BANK (16M: 512K × 16 bits × 2) × 2 a[21]* (16M: 512K × 16 bits × 2) × 2 a[20]* (16M: 1M ×...
Page 437: Pcmcia Control Register (Pcr)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CAS- before-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR.
Page 438 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 15 and 14—PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Page 439 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bits 8 to 6—Address-OE/WE Assertion Delay (A6TED2–A6TED0): These bits set the delay time from address output to OE/WE assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Page 440: Synchronous Dram Mode Register (Sdmr)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bits 2 to 0—OE/WE Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O card read.
Page 441 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) A2 of this LSI, and A1 of the synchronous DRAM is connected to A3 of this LSI, the value actually written to the synchronous DRAM is the value of “X” shifted 2 bits to the right.
Page 442: Refresh Timer Control/Status Register (Rtcsr)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group LMODE 000: Reserved 000: Reserved 001: Reserved 001: 1 010: 4 010: 2 011: 8* 011: 3 100: Reserved 100: Reserved 101: Reserved 101: Reserved 110: Reserved 110: Reserved 111: Reserved...
Page 443 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Bit 7—Compare-Match Flag (CMF): Status flag that indicates a match between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR) values. Bit 7: CMF Description RTCNT and RTCOR values do not match...
Page 444: Refresh Timer Counter (Rtcnt)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified by the LMTS bit in RTCSR.
Page 445: Refresh Time Constant Register (Rtcor)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) RTCNT is initialized to H'0000 by a power-on reset, but continues to count when a manual reset is performed. In standby mode, RTCNT is not initialized, and retains its contents.
Page 446: Refresh Count Register (Rfcr)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group 13.2.14 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of refreshes by being incremented each time the RTCOR register and RTCNT counter values match.
Page 447: Operation
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) RTCSR, RTCNT, Write data RTCOR Write data RFCR Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR Reading RTCSR, RTCNT, RTCOR, and RFCR: A 16-bit access must always be used when reading RTCSR, RTCNT, RTCOR, or RFCR.
Page 448: Table 13.8 32-Bit External Device/Big-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Data Configuration Byte Data 7–0 Word Data 15–8 Data 7–0 Longword Data 31–24 Data 23–16 Data 15–8 Data 7–0 Quadword Data Data Data Data Data Data Data Data 63–56 55–48 47–40...
Page 449: Table 13.9 16-Bit External Device/Big-Endian Access And Data Alignment
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0...
Page 450: Table 13.10 8-Bit External Device/Big-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0...
Page 451: Table 13.11 32-Bit External Device/Little-Endian Access And Data Alignment
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0...
Page 452: Table 13.12 16-Bit External Device/Little-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0...
Page 453: Table 13.13 8-Bit External Device/Little-Endian Access And Data Alignment
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0...
Page 454: Areas
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group 13.3.2 Areas Area 0: For area 0, external address bits 28 to 26 are 000. SRAM, MPX, and burst ROM can be set for this area. A bus width of 8, 16, or 32 bits can be selected in a power-on reset by means of external pins MD4 and MD3.
Page 455 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Area 2: For area 2, external address bits 28 to 26 are 010. SRAM, MPX, and synchronous DRAM can be set to this area. When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A2SZ1 and A2SZ0 in the BCR2 register.
Page 456 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A3W2 to A3W0 in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (RDY).
Page 457 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Area 5: For area 5, external address bits 28 to 26 are 101. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A5SZ1 and A5SZ0 in the BCR2 register.
Page 458 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Area 6: For area 6, external address bits 28 to 26 are 110. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A6SZ1 and A6SZ0 in the BCR2 register.
Page 459: Sram Interface
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.3.3 SRAM Interface Basic Timing: The SRAM interface of this LSI uses strobe signal output in consideration of the fact that mainly SRAM will be connected. Figure 13.6 shows the SRAM timing of normal space accesses.
Page 460: Figure 13.6 Basic Timing Of Sram Interface
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group CKIO A25–A0 RD/WR D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Legend: Single address DMA Dual address DMA Figure 13.6 Basic Timing of SRAM Interface Page 406 of 1128 R01UH0457EJ0301 Rev.
Page 461: Figure 13.7 Example Of 32-Bit Data Width Sram Connection
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Figures 13.7, 13.8, and 13.9 show examples of connection to 32-, 16-, and 8-bit data width SRAM. 128K × 8-bit SH7751/SH7751R SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 13.7 Example of 32-Bit Data Width SRAM Connection...
Page 462: Figure 13.8 Example Of 16-Bit Data Width Sram Connection
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group 128K × 8-bit SH7751/SH7751R SRAM I/O7 I/O0 I/O7 I/O0 Figure 13.8 Example of 16-Bit Data Width SRAM Connection Page 408 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 463: Figure 13.9 Example Of 8-Bit Data Width Sram Connection
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 128K × 8-bit SH7751/SH7751R SRAM I/O7 I/O0 Figure 13.9 Example of 8-Bit Data Width SRAM Connection Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2 settings.
Page 464: Figure 13.10 Sram Interface Wait Timing (Software Wait Only)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group CKIO A25–A0 RD/WR D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 465: Figure 13.11 Sram Interface Wait State Timing (Wait State Insertion By Rdy Signal)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) When software wait insertion is specified by WCR2, the external wait input RDY signal is also sampled. RDY signal sampling is shown in figure 13.11. A single-cycle wait is specified as a software wait.
Page 466: Figure 13.12 Sram Interface Read Strobe Negate Timing (Ans = 1, Anw = 4, And Anh = 2)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Read-Strobe Negate Timing (Setting Only Possible in the SH7751R): When the SRAM interface is used, timing for the negation of the strobe during read operations can be specified by the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this setting, see the description of the WCR3 register.
Page 467: Dram Interface
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.3.4 DRAM Interface Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to 100, area 3 becomes DRAM interface. The DRAM interface function can then be used to connect DRAM to this LSI.
Page 468: Table 13.14 Relationship Between Amxext And Amx2-0 Bits And Address Multiplexing
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Address Multiplexing: When area 3 is designated as DRAM interface, address multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row and column address multiplexing, to be connected to this LSI without using an external address multiplexer circuit.
Page 469: Figure 13.14 Basic Dram Access Timing
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in figure 13.14. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and Tc2 the read data latch cycle.
Page 470: Figure 13.15 Dram Wait State Timing
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR.
Page 471: Figure 13.16 Dram Burst Access Timing
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Burst Access: In addition to the normal DRAM access mode in which a row address is output in each data access, a fast page mode is also provided for the case where consecutive accesses are made to the same row.
Page 472: Figure 13.17 Dram Bus Cycle (Edo Mode, Rcd = 0, Anw = 0, Tpc = 1)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only while the CAS signal is asserted in a data read cycle, an EDO (extended data out) mode is also provided in which, once the CAS signal is asserted while the RAS signal is asserted, even if the CAS signal is negated, data is output to the data bus until the CAS signal is next asserted.
Page 473: Figure 13.18 Burst Access Timing In Dram Edo Mode
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) CKIO Address RD/WR CASn D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.18 Burst Access Timing in DRAM EDO Mode RAS Down Mode: This LSI has an address comparator for detecting row address matches in burst mode.
Page 474: Figure 13.19 (1) Dram Burst Bus Cycle, Ras Down Mode Start (Fast Page Mode, Rcd = 0, Anw = 0)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group CKIO Address RD/WR CASn D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 475: Figure 13.19 (2) Dram Burst Bus Cycle, Ras Down Mode Continuation (Fast Page Mode, Rcd = 0, Anw = 0)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Tnop CKIO Address RD/WR End of RAS down mode CASn D31–D0 (read) D31–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 476: Figure 13.19 (3) Dram Burst Bus Cycle, Ras Down Mode Start (Edo Mode, Rcd = 0, Anw = 0)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group CKIO Address RD/WR CASn D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.19 (3) DRAM Burst Bus Cycle, RAS Down Mode Start...
Page 477: Figure 13.19 (4) Dram Burst Bus Cycle, Ras Down Mode Continuation (Edo Mode, Rcd = 0, Anw = 0)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Tnop CKIO Address RD/WR End of RAS down mode CASn D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 478: Figure 13.20 Cas-Before-Ras Refresh Operation
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Refresh: The bus state controller includes a function for controlling DRAM refreshing. Distributed refreshing using a CAS-before-RAS cycle can be performed for DRAM by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. Self-refresh mode is also supported.
Page 479: Figure 13.21 Dram Cas-Before-Ras Refresh Cycle Timing (Tras = 0, Trc = 1)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) TRr1 TRr2 TRr3 TRr4 TRr5 CKIO A25–A0 RD/WR D31–D0 Figure 13.21 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) • Self-Refresh The self-refreshing supported by this LSI is shown in figure 13.22.
Page 480: Figure 13.22 Dram Self-Refresh Cycle Timing
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group • Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus...
Page 481: Synchronous Dram Interface
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time (at least 100 μs or 200 μs) during which no access can be performed be provided, followed by at least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles.
Page 482: Figure 13.23 Example Of 32-Bit Data Width Synchronous Dram Connection (Area 3)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Commands for synchronous DRAM are specified by RAS, CASS, RD/WR, and specific address signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL), precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register setting (MRS).
Page 483: Table 13.15 Example Of Correspondence Between Lsi And Synchronous Dram Address Pins (32-Bit Bus Width, Amx2-Amx0 = 000, Amxext = 0)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Address Multiplexing: Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2– AMX0 in MCR. Table 13.15 shows the relationship between the address multiplex specification bits and the bits output at the address pins.
Page 484 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group the READA command inside the synchronous DRAM; no new access command can be issued to the same bank during this cycle. In this LSI, the number of Tpc cycles is determined by the specification of bits TPC2–TPC0 in MCR, and commands are not issued for the synchronous...
Page 485: Figure 13.24 Basic Timing For Synchronous Dram Burst Read
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Figure 13.24 Basic Timing for Synchronous DRAM Burst Read R01UH0457EJ0301 Rev. 3.01 Page 431 of 1128 Sep 24, 2013...
Page 486 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the beginning of each data transfer cycle that is in response to a READ or READA command. Data are accessed in the following sequence: in the fill operation for a cache miss, the data between 64-bit boundaries that include the missing data are first read by the initial READ command;...
Page 487: Figure 13.25 Basic Timing For Synchronous Dram Single Read
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Tc3 Tc4/Td1 Td2 CKIO Bank Precharge-sel Address RD/WR CASS DQMn D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 488: Figure 13.26 Basic Timing For Synchronous Dram Burst Write
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. Access starts from 16-byte boundary data, and 32-byte boundary data is written in wraparound mode. DACK is asserted two cycles before the data write cycle.
Page 489 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Single Write: The basic timing chart for write access is shown in figure 13.27. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle.
Page 490: Figure 13.27 Basic Timing For Synchronous Dram Single Write
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Trwl Trwl CKIO Bank Precharge-sel Address RD/WR CASS DQMn D31–D0 (write) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 491 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT).
Page 492: Figure 13.28 Burst Read Timing
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group bank active state, after this is detected the bus cycle in figure 13.30 or 13.33 is executed instead of that in figure 13.29 or 13.32. In RAS down mode, too, a PALL command is issued before a refresh cycle or before bus release due to bus arbitration.
Page 493: Figure 13.29 Burst Read Timing (Ras Down, Same Row Address)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Tc3 Tc4/Td1 CKIO Bank Precharge-sel Address RD/WR CASS DQMn D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 494: Figure 13.30 Burst Read Timing (Ras Down, Different Row Addresses)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Figure 13.30 Burst Read Timing (RAS Down, Different Row Addresses) Page 440 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 495: Figure 13.31 Burst Write Timing
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Figure 13.31 Burst Write Timing R01UH0457EJ0301 Rev. 3.01 Page 441 of 1128 Sep 24, 2013...
Page 496: Figure 13.32 Burst Write Timing (Same Row Address)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Figure 13.32 Burst Write Timing (Same Row Address) Page 442 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 497: Figure 13.33 Burst Write Timing (Different Row Addresses)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Figure 13.33 Burst Write Timing (Different Row Addresses) R01UH0457EJ0301 Rev. 3.01 Page 443 of 1128 Sep 24, 2013...
Page 498 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the DMAC, to provide faster access to synchronous DRAM.
Page 499: Table 13.16 Cycles In Which Pipelined Access Can Be Used
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Table 13.16 Cycles in Which Pipelined Access Can Be Used Following Access DMAC Dual DMAC Single Preceding Access Read Write Read Write Read Write Read Write DMAC dual Read Write...
Page 500: Figure 13.34 Burst Read Cycle For Different Bank And Row Address Following Preceding
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle Page 446 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 501 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1.
Page 502: Figure 13.35 Auto-Refresh Operation
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group RTCNT cleared to 0 when RTCNT value RTCNT = RTCOR RTCOR-1 Time H'00000000 ≠ 000 RTCSR.CKS2–0 = 000 Refresh request Refresh request cleared by start of refresh cycle External bus Auto-refresh cycle Figure 13.35 Auto-Refresh Operation...
Page 503 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) • Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1.
Page 504: Figure 13.37 Synchronous Dram Self-Refresh Timing
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group TRs1 TRs2 TRs3 TRs4 TRs5 CKIO RD/WR CASS DQMn D31–D0 Figure 13.37 Synchronous DRAM Self-Refresh Timing • Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed.
Page 505 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the RAS, CAS, and RD/WR signals.
Page 506: Figure 13.38 (1) Synchronous Dram Mode Write Timing (Pall)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group auto-refreshing has been executed at least the prescribed number of times, a mode register setting command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and performing a write to address H'FF900000 + X or H'FF940000 + X.
Page 507: Figure 13.38 (2) Synchronous Dram Mode Write Timing (Mode Register Setting)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address RD/WR CASS D31–D0 (High) Figure 13.38 (2) Synchronous DRAM Mode Write Timing (Mode Register Setting) Changing the Burst Length (SH7751R Only): When synchronous DRAM is connected with the 32-bit memory bus of the SH7751R, a burst length of either 4 or 8 can be selected by the setting of the SDBL bit of the BCR3 register.
Page 508 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group (CKIO). Tpc is the cycle used to wait for auto-precharging, which is triggered by the READA command, to be completed in the synchronous DRAM. During this cycle, no new command that accesses the same bank can be issued.
Page 509: Figure 13.39 Basic Timing Of A Burst Read From Synchronous Dram (Burst Length = 8)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Tc4/Td1 CKIO Bank Precharge-sel Address RD/WR CASS DQMn D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 510: Figure 13.40 Basic Timing Of A Burst Write To Synchronous Dram
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group • Burst Write Figure 13.40 is the timing chart for a burst-write operation with a burst length of 8. In this LSI, a burst write takes place when a copy-back of the cache or a 32-byte transfer of data by the DMAC takes place.
Page 511: Burst Rom Interface
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.3.6 Burst ROM Interface Setting bits A0BST2–A0BST0, A5BST2–A5BST0, and A6BST2–A6BST0 in BCR1 to a non- zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a burst access function.
Page 512: Figure 13.41 Burst Rom Basic Access Timing
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group CKIO A25–A5 A4–A0 RD/WR D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.41 Burst ROM Basic Access Timing Page 458 of 1128 R01UH0457EJ0301 Rev.
Page 513: Figure 13.42 Burst Rom Wait Access Timing
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) CKIO A25–A5 A4–A0 RD/WR D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.42 Burst ROM Wait Access Timing R01UH0457EJ0301 Rev.
Page 514: Pcmcia Interface
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group CKIO A25–A5 A4–A0 RD/WR D31–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.43 Burst ROM Wait Access Timing 13.3.7...
Page 515 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Description Reserved (Setting prohibited) Dynamic I/O bus sizing 8-bit I/O space 16-bit I/O space 8-bit common memory 16-bit common memory 8-bit attribute memory 16-bit attribute memory When the MMU is on, wait cycles in a bus access can be set in MMU page units. See section 3, Memory Management Unit (MMU), for details of the setting method.
Page 516: Table 13.17 Relationship Between Address And Ce When Using Pcmcia Interface
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Table 13.17 Relationship between Address and CE When Using PCMCIA Interface Access Width Read/ Size Odd/ (Bits) Write (Bits)* Even IOIS16 Access CE2 D15–D8 D7–D0 Read Even Don't — Invalid...
Page 517 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Access Width Read/ Size Odd/ (Bits) Write (Bits)* Even IOIS16 Access CE2 D15–D8 D7–D0 Dynamic Read Even — Invalid Read data — Read data Invalid sizing* Even — Upper read data Lower read data —...
Page 518: Figure 13.44 Example Of Pcmcia Interface
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group A25–A0 A25–A0 D15–D0 D7–D0 RD/WR CE1B/(CS6) D15–D0 CE1A/(CS5) CE2B PC card CE2A D15–D8 (memory I/O) SH7751/ SH7751R WE/PGM (IORD) ICIORD (IOWR) ICIOWR WAIT IOIS16 (IOIS16) Card detection CD1, CD2 circuit A25–A0...
Page 519: Figure 13.45 Basic Timing For Pcmcia Memory Card Interface
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Memory Card Interface Basic Timing: Figure 13.45 shows the basic timing for the PCMCIA memory card interface, and figure 13.46 shows the wait timing for the PCMCIA memory card interface.
Page 520: Figure 13.46 Wait Timing For Pcmcia Memory Card Interface
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25–A0 CExx RD/WR (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 521: Figure 13.47 Pcmcia Space Allocation
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Common memory (64 MB) Virtual Access address space by CS5 wait External I/O controller addresses 1 KB IO 1 Virtual Access page address space by CS6 wait IO 1 controller...
Page 522: Figure 13.48 Basic Timing For Pcmcia I/O Card Interface
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Tpci1 Tpci2 CKIO A25–A0 CExx RD/WR ICIORD (read) D15–D0 (read) ICIOWR (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 523: Figure 13.49 Wait Timing For Pcmcia I/O Card Interface
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25–A0 CExx RD/WR ICIORD (read) D15–D0 (read) ICIOWR (write) D15–D0 (write) IOIS16 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 524: Figure 13.50 Dynamic Bus Sizing Timing For Pcmcia I/O Card Interface
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Tpci2 Tpci2w Tpci0 Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w CKIO A25–A1 CExx RD/WR IORD (WE2) (read) D15–D0 (read) IOWR (WE3) (write) D15–D0 (write) IOIS16 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Page 525: Mpx Interface
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.3.8 MPX Interface If the MD6 pin is cleared to 0 in a power-on reset by means of the RESET pin, the MPX interface is selected for area 0. The MPX interface is selected for areas 1 to 6 by means of the MPX bit in BCR1 and MEMMODE, A4MPX, and A1MPX in BCR3.
Page 526: Figure 13.51 Example Of 32-Bit Data Width Mpx Connection
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group SH7751/SH7751R MPX device CKIO RD/FRAME FRAME RD/WR D31–D0 I/O31–I/O0 Figure 13.51 Example of 32-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1 to 6, a bus size of 32 bit should be specified in BCR2.
Page 527: Figure 13.52 Mpx Interface Timing 1 (Single Read Cycle, Anw = 0, No External Wait)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Tmd1w Tmd1 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.52 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait) R01UH0457EJ0301 Rev.
Page 528: Figure 13.53 Mpx Interface Timing 2 (Single Read, Anw = 0, One External Wait Inserted)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Tmd1w Tmd1w Tmd1 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.53 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted) Page 474 of 1128 R01UH0457EJ0301 Rev.
Page 529: Figure 13.54 Mpx Interface Timing 3 (Single Write Cycle, Anw = 0, No External Wait)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Tmd1 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait) R01UH0457EJ0301 Rev.
Page 530: Figure 13.55 Mpx Interface Timing 4 (Single Write, Anw = 1, One External Wait Inserted)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Tmd1w Tmd1w Tmd1 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.55 MPX Interface Timing 4...
Page 531: Figure 13.56 Mpx Interface Timing 5 (Burst Read Cycle, Anw = 0, No External Wait)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait) R01UH0457EJ0301 Rev. 3.01 Page 477 of 1128 Sep 24, 2013...
Page 532: Figure 13.57 Mpx Interface Timing 6 (Burst Read Cycle, Anw = 0, External Wait Control)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control) Page 478 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 533: Figure 13.58 Mpx Interface Timing 7 (Burst Write Cycle, Anw = 0, No External Wait)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait) R01UH0457EJ0301 Rev. 3.01 Page 479 of 1128 Sep 24, 2013...
Page 534: Figure 13.59 Mpx Interface Timing 8 (Burst Write Cycle, Anw = 1, External Wait Control)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control) Page 480 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 535: Figure 13.60 Mpx Interface Timing 9 (Burst Read Cycle, Anw = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Tmd1w Tmd1 Tmd2 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.60 MPX Interface Timing 9...
Page 536: Figure 13.61 Mpx Interface Timing 10 (Burst Read Cycle, Anw = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Tmd1w Tmd1w Tmd1 Tmd2 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.61 MPX Interface Timing 10...
Page 537: Figure 13.62 Mpx Interface Timing 11 (Burst Write Cycle, Anw = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) Tmd1 Tmd2 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.62 MPX Interface Timing 11...
Page 538: Figure 13.63 Mpx Interface Timing 12 (Burst Write Cycle, Anw = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Tmd1w Tmd1w Tmd1 Tmd2 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.63 MPX Interface Timing 12...
Page 539: Byte Control Sram Interface
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.3.9 Byte Control SRAM Interface The byte control SRAM interface is a memory interface that outputs a byte select strobe (WEn) in both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has an upper byte select strobe and lower byte select strobe function such as UB and LB.
Page 540: Figure 13.65 Byte Control Sram Basic Read Cycle (No Wait)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group CKIO A25–A0 RD/WR D31–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.65 Byte Control SRAM Basic Read Cycle (No Wait) Page 486 of 1128 R01UH0457EJ0301 Rev.
Page 541: Figure 13.66 Byte Control Sram Basic Read Cycle (One Internal Wait Cycle)
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) CKIO A25–A0 RD/WR D31–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.66 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) R01UH0457EJ0301 Rev.
Page 542: Figure 13.67 Byte Control Sram Basic Read Cycle (One Internal Wait + One External Wait)
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group CKIO A25–A0 RD/WR D31–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.67 Byte Control SRAM Basic Read Cycle...
Page 543: 13.3.10 Waits Between Access Cycles
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.3.10 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and so resulting in lower reliability or incorrect operation.
Page 544: 13.3.11 Bus Arbitration
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group Twait Twait CKIO A25–A0 RD/WR D31–D0 Area m space read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 13.68 Waits between Access Cycles 13.3.11 Bus Arbitration...
Page 545 SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) occur simultaneously, priority is given, in high-to-low order, to a bus request from an external device, a refresh request, the DMAC, and the CPU. See section 13.3.15, Notes on Usage.
Page 546: Figure 13.69 Arbitration Sequence
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group CKIO BREQ Asserted for at least 2 cycles * BACK Negated within 2 cycles Hi-Z A25–A0 Hi-Z Hi-Z RD/WR Hi-Z Hi-Z Master mode device access BACK/BSREQ Asserted for at least 2 cycles...
Page 547: 13.3.12 Master Mode
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.3.12 Master Mode The master mode processor holds the bus itself unless it receives a bus request. On receiving an assertion (low level) of the bus request signal (BREQ) from off-chip, the master mode processor releases the bus and asserts (drives low) the bus use permission signal (BACK) as soon as the currently executing bus cycle ends.
Page 548: 13.3.13 Slave Mode
Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group If a refresh request is generated when BACK has been asserted and the bus has been released, the BACK signal is negated even while the BREQ signal is asserted to request the slave to relinquish the bus.
Page 549: 13.3.14 Cooperation Between Master And Slave
SH7751 Group, SH7751R Group Section 13 Bus State Controller (BSC) 13.3.14 Cooperation between Master and Slave To enable system resources to be controlled in a harmonious fashion by master and slave, their respective roles must be clearly defined. Before DRAM or synchronous DRAM is used, initialization operations must be carried out.
Page 550 Section 13 Bus State Controller (BSC) SH7751 Group, SH7751R Group • When a BREQ signal is input from the external device while DRAM/synchronous DRAM is set to CAS-before-RAS refresh and auto-refresh in master mode (MD7 = 1), assertion of the BACK signal (low-level) in response to the BREQ signal may be for only one cycle at CKIO.
Page 551: Section 14 Direct Memory Access Controller (Dmac)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Section 14 Direct Memory Access Controller (DMAC) 14.1 Overview The SH7751 includes an on-chip four-channel direct memory access controller (DMAC). The SH7751R has an on-chip eight-channel DMAC. The DMAC can be used in place of the CPU to...
Page 552 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group • The following kinds of DMAC transfer activation requests are provided ⎯ External request (1) Normal DMA mode Two DREQ pins. Low level detection or falling edge detection can be specified.
Page 553 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) • Channel 6 (SH7751R only): Single or dual address mode. External requests are accepted. • Channel 7 (SH7751R only): Single or dual address mode. External requests are accepted. • In DDT mode, data transfer is carried out by the SH7751 using the DBREQ, BAVL,...
Page 554: Block Diagram (Sh7751)
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.1.2 Block Diagram (SH7751) Figure 14.1 shows a block diagram of the DMAC. DMAC module Count SARn control Register DARn control DMATCRn Activation On-chip control peripheral CHCRn module DMAOR...
Page 555: Pin Configuration (Sh7751)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.1.3 Pin Configuration (SH7751) Tables 14.1 and 14.2 show the DMAC pins. Table 14.1 DMAC Pins Channel Pin Name Abbreviation Function DREQ0 DMA transfer Input DMA transfer request input from...
Page 556: Register Configuration (Sh7751)
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Table 14.2 DMAC Pins in DDT Mode Pin Name Abbreviation Function DBREQ Data bus request Input Data bus release request from external (DREQ0) device for DTR format input BAVL...
Page 557: Table 14.3 Dmac Registers
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Table 14.3 DMAC Registers Chan- Abbre- Read/ Initial Area 7 Access Name viation Write Value P4 Address Address Size SAR0 DMA source Undefined H'FFA00000 H'1FA00000 32 address register 0...
Page 558: Register Descriptions
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.2 Register Descriptions 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) Bit: Initial value: — — — — — — — — R/W: Bit: · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·...
Page 559: Dma Destination Address Registers 0-3 (Dar0-Dar3)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) Bit: Initial value: — — — — — — — — R/W: Bit: · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·...
Page 560: Dma Transfer Count Registers 0-3 (Dmatcr0-Dmatcr3)
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) Bit: Initial value: R/W: Bit: Initial value: — — — — — — — — R/W: Bit: Initial value: — — —...
Page 561: Dma Channel Control Registers 0-3 (Chcr0-Chcr3)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) Bit: SSA2 SSA1 SSA0 DSA2 DSA1 DSA0 Initial value: R/W: Bit: — — — — Initial value: — — — — R/W:...
Page 562 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify the space attribute for PCMCIA interface area access. Bit 31: SSA2 Bit 30: SSA1 Bit 29: SSA0...
Page 563 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits specify the space attribute for PCMCIA interface area access. Bit 27: DSA2 Bit 26: DSA1 Bit 25: DSA0...
Page 564 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Bit 19—DREQ Select (DS): Specifies either low level detection or falling edge detection as the sampling method for the DREQ pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR3.
Page 565 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or active-low. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. It is invalid in DDT mode.
Page 566 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source. Bit 11: Bit 10: Bit 9: Bit 8: Description External request, dual address mode* (external address space →...
Page 567 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. Bit 7: TM Description Cycle steal mode (Initial value) Burst mode Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. In access to external memory, the specification is treated as an access size as described in section 13.3,...
Page 568 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated.
Page 569: Dma Operation Register (Dmaor)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.2.5 DMA Operation Register (DMAOR) Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — — Initial value: R/W: Bit: —...
Page 570 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Bits 14 to 10—Reserved: These bits are always read as 0, and should only be written with 0. Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously.
Page 571: Operation
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer.
Page 572 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Figure 14.2 shows a flowchart of this procedure. Note: If a transfer request is issued while transfer is disabled, the transfer enable wait state (transfer suspended state) is entered. Transfer is started when subsequently enabled (by setting DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0).
Page 573: Figure 14.2 Dmac Transfer Flowchart
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1? Illegal address check (reflected in AE bit) NMIF, AE, TE = 0? Transfer request issued? Bus mode,...
Page 574: Dma Transfer Requests
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.3.2 DMA Transfer Requests DMA transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination.
Page 575: Table 14.4 Selecting External Request Mode With Rs Bits
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Table 14.4 Selecting External Request Mode with RS Bits Address Mode Transfer Source Transfer Destination Dual address External memory, External memory, mode memory-mapped memory-mapped external device, or external device, or...
Page 576: Table 14.5 Selecting On-Chip Peripheral Module Request Mode With Rs Bits
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit...
Page 577: Channel Priorities
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Notes: SCI/SCIF burst transfer setting is prohibited. If input capture interrupt acceptance is set for multiple channels and DE =1 for each channel, processing will be executed on the highest-priority channel in response to a single input capture interrupt.
Page 578: Figure 14.3 Round Robin Mode
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Transfer on channel 0 Channel 0 is given the lowest CH0 > CH1 > CH2 > CH3 Initial priority order priority. CH1 > CH2 > CH3 > CH0 Priority order after transfer...
Page 579: Figure 14.4 Example Of Changes In Priority Order In Round Robin Mode
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby).
Page 580: Types Of Dma Transfer
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.3.4 Types of DMA Transfer The DMAC supports the transfers shown in table 14.6. It can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output.
Page 581: Figure 14.5 Data Flow In Single Address Mode
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Address Modes Single Address Mode: In single address mode, both the transfer source and the transfer destination are external; one is accessed by the DACK signal and the other by an address. In this...
Page 582: Figure 14.6 Dma Transfer Timing In Single Address Mode
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group CKIO Address output to external memory A28–A0 space Data output from external device D63–D0 with DACK DACK DACK signal to external device with DACK WE signal to external memory space...
Page 583: Figure 14.7 Operation In Dual Address Mode
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Dual Address Mode: Dual address mode is used to access both the transfer source and the transfer destination by address. The transfer source and destination can be accessed by either on- chip peripheral module or external address.
Page 584: Figure 14.8 Example Of Transfer Timing In Dual Address Mode
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group CKIO Transfer source Transfer destination A28–A0 address address D63–D0 DACK Data read cycle Data write cycle (1st cycle) (2nd cycle) Transfer from external memory space to external memory space Figure 14.8 Example of Transfer Timing in Dual Address Mode...
Page 585: Figure 14.9 Example Of Dma Transfer In Cycle Steal Mode
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer conditions in this example are dual address mode and DREQ level detection. DREQ Bus returned to CPU...
Page 586: Table 14.7 Relationship Between Dma Transfer Type, Request Mode, And Bus Mode
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Relationship between DMA Transfer Type, Request Mode, and Bus Mode Table 14.7 shows the relationship between the type of DMA transfer, the request mode, and the bus mode. Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode...
Page 587: Table 14.8 External Request Transfer Sources And Destinations In Normal Dma Mode
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 5. When the transfer request is an external request, only channels 0 and 1 can be used. 6. In DDT mode, transfer requests can be accepted for all channels from external devices capable of DTR format output.
Page 588: Table 14.9 External Request Transfer Sources And Destinations In Ddt Mode
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group (b) DDT Mode Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by this LSI in DDT mode.
Page 589: Number Of Bus Cycle States And Dreq Pin Sampling Timing
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or round robin mode is set for the priority order, the bus is not released to the CPU until channel 1 transfer ends.
Page 590 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Operation: Figures 14.12 to 14.22 show the timing in each mode. 1. Cycle Steal Mode In cycle steal mode, The DREQ sampling timing differs for dual address mode and single address mode, and for level detection and edge detection of DREQ.
Page 591 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation, and the second sampling operation begins one cycle after the start of the first DMAC transfer bus cycle.
Page 592: Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) Page 538 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 593: Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) R01UH0457EJ0301 Rev. 3.01 Page 539 of 1128 Sep 24, 2013...
Page 594: Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/Dreq
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) Page 540 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 595: Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/Dreq
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) R01UH0457EJ0301 Rev. 3.01 Page 541 of 1128 Sep 24, 2013...
Page 596: Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip Sci (Level Detection) → External Bus
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → External Bus Page 542 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 597: Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip Sci
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI (Level Detection) R01UH0457EJ0301 Rev. 3.01 Page 543 of 1128 Sep 24, 2013...
Page 598: Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection) Page 544 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 599: Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection) R01UH0457EJ0301 Rev. 3.01 Page 545 of 1128 Sep 24, 2013...
Page 600: Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/Dreq
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection) Page 546 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 601: Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/Dreq
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection) R01UH0457EJ0301 Rev. 3.01 Page 547 of 1128 Sep 24, 2013...
Page 602: Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/Dreq
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM: Row Hit Write) Page 548 of 1128 R01UH0457EJ0301 Rev. 3.01...
Page 603: Ending Dma Transfer
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.3.6 Ending DMA Transfer The conditions for ending DMA transfer are different for ending on individual channels and for ending on all channels together. Except for the case where transfer ends when the value in the DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending transfer.
Page 604 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding channel when either of the following conditions is satisfied: • The value in the DMA transfer count register (DMATCR) reaches 0.
Page 605 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 2. End of transfer when NMIF = 1 in DMAOR If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is...
Page 606: Examples Of Use
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.4 Examples of Use 14.4.1 Examples of Transfer between External Memory and an External Device with DACK Examples of transfer of data in external memory to an external device with DACK using DMAC channel 1 are considered here.
Page 607: On-Demand Data Transfer Mode (Ddt Mode)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.5 On-Demand Data Transfer Mode (DDT Mode) 14.5.1 Operation Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT mode). In DDT mode, it is possible to transfer to channel 0 to 3 via the data bus and DDT module, and simultaneously issue a transfer request, using the DBREQ, BAVL, TR, TDACK, ID [1:0], DTR.ID, and DTR.MD signals between an external device and the DMAC.
Page 608 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 1. Normal data transfer mode (channel 0) BAVL (the data bus available signal) is asserted in response to DBREQ (the data bus request signal) from an external device. Two CKIO-synchronous cycles after BAVL is asserted, the external data bus drives the data transfer setting command (DTR command) in synchronization with TR (the transfer request signal).
Page 609: Pins In Ddt Mode
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.5.2 Pins in DDT Mode Figure 14.24 shows the system configuration in DDT mode. DBREQ/DREQ0 BAVL/DRAK0 TR/DREQ1 TDACK/DACK0 SH7751/SH7751R ID1, ID0/DRAK1, DACK1 External device CKIO D31–D0 = DTR A25–A0, RAS, CAS, WE, DQMn, CKE...
Page 610: Figure 14.25 Data Transfer Request Format
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group • TDACK: Reply strobe signal for external device from DMAC The assertion timing is the same as the DACKn assertion timing for each memory interface. However, note that TDACK is an active-low signal.
Page 611: Table 14.11 Usable Sz, Id, And Md Combination In Ddt Mode
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) • 11: Channel 3 Bits 25 and 24: Transfer Request Mode (MD1, MD0) • 00: Handshake protocol (data bus used) • 01: Setting prohibited • 10: Request queue clear specification •...
Page 612: Transfer Request Acceptance On Each Channel
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.5.3 Transfer Request Acceptance on Each Channel On channel 0, a DMA data transfer request can be made by means of the DTR format. No further transfer requests are accepted between DTR format acceptance and the end of the data transfer.
Page 613 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.26 Single Address Mode/Synchronous DRAM → External Device Longword Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD = 1, CAS latency = 3, TPC = 3) R01UH0457EJ0301 Rev. 3.01...
Page 614: Figure 14.27 Single Address Mode/External Device → Synchronous Dram Longword
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Figure 14.27 Single Address Mode/External Device → Synchronous DRAM Longword Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD = 1, TRWL = 2, TPC = 1) Page 560 of 1128 R01UH0457EJ0301 Rev.
Page 615: Figure 14.28 Dual Address Mode/Synchronous Dram → Sram Longword Transfer
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer R01UH0457EJ0301 Rev. 3.01 Page 561 of 1128 Sep 24, 2013...
Page 616: Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer CKIO...
Page 617: Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, WE DQMn TDACK ID1, ID0 Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer R01UH0457EJ0301 Rev. 3.01...
Page 618: Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, WE DQMn TDACK ID1, ID0 Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer Page 564 of 1128 R01UH0457EJ0301 Rev.
Page 619: Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ BAVL A25–A0 D31–D0 MD = 00 MD = 00 TDACK ID1, ID0 Next transfer request Start of data transfer Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) R01UH0457EJ0301 Rev.
Page 620: Figure 14.34 Handshake Protocol Without Use Of Data Bus (Channel 0 On-Demand Data Transfer)
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group CKIO DBREQ BAVL A25–A0 D31–D0 MD = 00 TDACK ID1, ID0 Next transfer request Start of data transfer Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer) Page 566 of 1128 R01UH0457EJ0301 Rev.
Page 621: Figure 14.35 Read From Synchronous Dram Precharge Bank
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ BAVL A25–A0 D31–D0 D2 D3 RAS, CAS, Figure 14.35 Read from Synchronous DRAM Precharge Bank CKIO DBREQ Transfer requests can be accepted BAVL A25–A0 D31–D0 D2 D3 RAS, CAS, Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss)
Page 622: Figure 14.37 Read From Synchronous Dram (Row Hit)
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group CKIO DBREQ BAVL A25–A0 D31–D0 D2 D3 RAS, CAS, Figure 14.37 Read from Synchronous DRAM (Row Hit) CKIO DBREQ BAVL A25–A0 D2 D3 D31–D0 RAS, CAS, Figure 14.38 Write to Synchronous DRAM Precharge Bank Page 568 of 1128 R01UH0457EJ0301 Rev.
Page 623: Figure 14.39 Write To Synchronous Dram Non-Precharge Bank (Row Miss)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ Transfer requests can be accepted BAVL A25–A0 D31–D0 D2 D3 RAS, CAS, Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, Figure 14.40 Write to Synchronous DRAM (Row Hit)
Page 624: Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Page 570 of 1128 R01UH0457EJ0301 Rev.
Page 625: Figure 14.42 Ddt Mode Setting
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) DMA Operation Register (DMAOR) PR[1:0] NMIF Note: DDT: 0: Normal DMA mode 1: On-demand data transfer mode Figure 14.42 DDT Mode Setting CKIO DBREQ BAVL No DMA request sampling A25–A0...
Page 626: Figure 14.44 Single Address Mode/Burst Mode/Level Detection/External Bus → External Device Data Transfer
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group CKIO DBREQ BAVL Wait for next DMA request A25–A0 D31–D0 D1 D2 D3 D0 D1 D2 D3 TDACK ID1, ID0 Start of data transfer Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus →...
Page 627: Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ BAVL A25–A0 D31–D0 DQMn Idle cycle Idle cycle Idle cycle TDACK ID1, ID0 Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer R01UH0457EJ0301 Rev.
Page 628: Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/Dma Transfer Request To Channels 1-3 Using Data Bus
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group CKIO DBREQ BAVL A25–A0 D31–D0 ID = 1, 2, or 3 RAS, CAS, WE TDACK ID1, ID0 01 or 10 or 11 Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1–3 Using Data Bus...
Page 629: Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/External Bus → External Device Data Transfer/Direct Data Transfer Request To Channel 2 Without Using Data Bus
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ BAVL A25–A0 D31–D0 RAS, CAS, WE TDACK ID1, ID0 No DTR cycle, so requests can be made at any time Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus →...
Page 630 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Four requests can be queued Handshaking is necessary to send additional requests CKIO 1st 2nd DBREQ BAVL No more requests A25–A0 D31–D0 RAS, CAS, TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.49 Single Address Mode/Burst Mode/External Bus →...
Page 631 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Four requests can be queued Handshaking is necessary to send additional requests CKIO 1st 2nd DBREQ BAVL A25–A0 D31–D0 RAS, CAS, TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.50 Single Address Mode/Burst Mode/External Device →...
Page 632: Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Handshaking is necessary Four requests can be queued to send additional requests CKIO 1st 2nd DBREQ BAVL A25–A0 D31–D0 RAS, CAS, TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.51 Single Address Mode/Burst Mode/External Bus →...
Page 633: Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Four requests can be queued Handshaking is necessary to send additional requests CKIO 1st 2nd DBREQ BAVL A25–A0 D31–D0 RAS, CAS, TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.52 Single Address Mode/Burst Mode/External Device →...
Page 634: Notes On Use Of Ddt Module
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.5.4 Notes on Use of DDT Module 1. Normal data transfer mode (channel 0) Set DTR.ID = 00 and DTR.MD = 00. If a setting of MD = 01, 10, or 11 is made, the DMAC will halt with an address error.
Page 635 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 6. Request queue transfer request acceptance a. The DDT has four request queues for each of channels 1 to 3. When these request queues are full, a DMA transfer request from an external device will be ignored.
Page 636 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group c. It takes one cycle for DBREQ to be accepted by the DMAC after being asserted by an external device. If a row address miss occurs at this time in a read or write in the non- precharged bank during synchronous DRAM access, and BAVL is asserted, the DBREQ signal asserted by the external device is ignored.
Page 637: Configuration Of The Dmac (Sh7751R)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.6 Configuration of the DMAC (SH7751R) 14.6.1 Block Diagram of the DMAC Figure 14.53 is a block diagram of the DMAC in the SH7751R. DMAC module Count control SAR0–7 DAR0–7...
Page 638: Pin Configuration (Sh7751R)
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.6.2 Pin Configuration (SH7751R) Tables 14.12 and 14.13 show the pin configuration of the DMAC. Table 14.12 DMAC Pins Channel Pin Name Abbreviation Function DREQ0 DMA transfer Input DMA transfer request input from...
Page 639: Register Configuration (Sh7751R)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Table 14.13 DMAC Pins in DDT Mode Pin Name Abbreviation Function DBREQ Data bus request Input Data bus release request from external (DREQ0) device for DTR format input BAVL/ID2...
Page 640: Table 14.14 Register Configuration
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Table 14.14 Register Configuration Chan- Abbre- Read/ Initial Area 7 Access Name viation Write Value P4 Address Address Size DMA source SAR0 Undefined H'FFA00000 H'1FA00000 32 address register 0...
Page 641 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Chan- Abbre- Read/ Initial Area 7 Access Name viation Write Value P4 Address Address Size DMA source SAR4 Undefined H'FFA00050 H'1FA00050 32 address register 4 DMA destination DAR4 Undefined...
Page 642: Register Descriptions (Sh7751R)
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.7 Register Descriptions (SH7751R) 14.7.1 DMA Source Address Registers 0−7 (SAR0−SAR7) Bit: Initial value: — — — — — — — — — — — — — — —...
Page 643: Dma Transfer Count Registers 0−7 (Dmatcr0−Dmatcr7)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.7.3 DMA Transfer Count Registers 0−7 (DMATCR0−DMATCR7) Bit: Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: —...
Page 644 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group No function is assigned to bits 18 and 16 of the CHCR2–CHCR7 registers. Writing to these bits of the CHCR2–CHCR7 registers is invalid. If, however, a value is written to these bits, it should always be 0.
Page 645 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the data read cycle or write cycle. In single address mode, DACK is always output regardless of the setting of this bit.
Page 646 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Bit 3⎯Request Queue Clear (QCL): Writing a 1 to this bit clears the request queues of the corresponding channel as well as any external requests that have already been accepted. This bit is only functional when DMAOR.DDT = 1 and DMAOR.DBL = 1.
Page 647: Dma Operation Register (Dmaor)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.7.5 DMA Operation Register (DMAOR) Bit: — — — — — — — — — — — — — — — — Initial value: R/W: Bit: DDT DBL —...
Page 648: Figure 14.54 Dtr Format (Transfer Request Format) (Sh7751R)
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Table 14.15 Channel Selection by DTR Format (DMAOR.DBL = 1) DTR.SZ[2:0] ≠ 101 DTR.ID[1:0] DTR.SZ[2:0] = 101 29 28 27 26 25 24 23 COUNT * (Reserved) Reserved Note: * These bits are valid when request queue clear is specified (with no transfer count function).
Page 649: Operation (Sh7751R)
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended.
Page 650: Transfer Channel Notification In Ddt Mode
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.8.3 Transfer Channel Notification in DDT Mode When the DMAC is set up for four-channel external request acceptance in DDT mode (DMAOR.DBL = 0), the ID [1:0] bits are used to notify the external device of the DMAC channel that is to be used.
Page 651: Clearing Request Queues By Dtr Format
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 14.8.4 Clearing Request Queues by DTR Format In DDT mode, the request queues of any channel can be cleared by using DTR.ID, DTR.MD, DTR.SZ, and DTR.COUNT [7:4] in a DTR format. This function is only available when DMAOR.DBL = 1.
Page 652: Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Table 14.19 DMAC Interrupt-Request Codes Source of the Interrupt Description INTEVT Code Priority DMTE0 CH0 transfer-end interrupt H'640 High DMTE1 CH1 transfer-end interrupt H'660 DMTE2 CH2 transfer-end interrupt H'680...
Page 653: Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus → External Device
SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ BAVL/ID2 A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus → External Device/32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 R01UH0457EJ0301 Rev.
Page 654: Usage Notes
Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group 14.9 Usage Notes 1. When modifying SAR0–SAR3, DAR0–DAR3, DMATCR0–DMATCR3, and CHCR0– CHCR3 in the SH7751 or when modifying SAR0–SAR7, DAR0–DAR7, DMATCR0– DMATCR7, and CHCR0–CHCR7 in the SH7751R, first clear the DE bit for the relevant channel to 0.
Page 655 SH7751 Group, SH7751R Group Section 14 Direct Memory Access Controller (DMAC) 7. When falling edge detection is used for external requests, keep the external request pin high when making DMAC settings. 8. When using the DMAC in single address mode, set an external address as the address. All channels will halt due to an address error if an on-chip peripheral module address is set.
Page 656 Section 14 Direct Memory Access Controller (DMAC) SH7751 Group, SH7751R Group Page 602 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 657: Section 15 Serial Communication Interface (Sci)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) 15.1 Overview This LSI is equipped with a single-channel serial communication interface (SCI) and a single- channel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF).
Page 658 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group ⎯ Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. There is a single serial data transfer format.
Page 659: Block Diagram
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the SCI. Internal Module data bus data bus SCBRR1 SCRDR1 SCSSR1 SCTDR1 SCSCR1 SCSMR1 SCRSR1 SCTSR1 Baud rate Pck/4 SCSPTR1...
Page 660: Pin Configuration
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group 15.1.3 Pin Configuration Table 15.1 shows the SCI pin configuration. Table 15.1 SCI Pins Pin Name Abbreviation Function Serial clock pin Clock input/output Receive data pin Input Receive data input...
Page 661: Register Descriptions
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 15.2 Register Descriptions 15.2.1 Receive Shift Register (SCRSR1) Bit: R/W: — — — — — — — — SCRSR1 is the register used to receive serial data. The SCI sets serial data input from the RxD pin in SCRSR1 in the order received, starting with the LSB (bit 0), and converts it to parallel data.
Page 662: Transmit Shift Register (Sctsr1)
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group 15.2.3 Transmit Shift Register (SCTSR1) Bit: R/W: — — — — — — — — SCTSR1 is the register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from SCTDR1 to SCTSR1, then sends the data to the TxD pin starting with the LSB (bit 0).
Page 663: Serial Mode Register (Scsmr1)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 15.2.5 Serial Mode Register (SCSMR1) Bit: STOP CKS1 CKS0 Initial value: R/W: SCSMR1 is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source.
Page 664 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit setting.
Page 665: Serial Control Register (Scscr1)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character.
Page 666 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group SCSCR1 can be read or written to by the CPU at all times. SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state.
Page 667 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4: RE Description Reception disabled* (Initial value) Reception enabled* Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states.
Page 668 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial clock input pin.
Page 669: Serial Status Register (Scssr1)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 15.2.7 Serial Status Register (SCSSR1) Bit: TDRE RDRF ORER TEND MPBT Initial value: — R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Only 0 can be written, to clear the flag.
Page 670 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Bit 6—Receive Data Register Full (RDRF): Indicates that the received data has been stored in SCRDR1. Bit 6: RDRF Description There is no valid receive data in SCRDR1 (Initial value) [Clearing conditions] •...
Page 671 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4: FER Description Reception in progress, or reception has ended normally*...
Page 672 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Bit 2—Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified.
Page 673: Serial Port Register (Scsptr1)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 15.2.8 Serial Port Register (SCSPTR1) Bit: — — — SPB1IO SPB1DT SPB0IO SPB0DT Initial value: — — R/W: — — — SCSPTR1 is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins.
Page 674 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details).
Page 675: Figure 15.2 Sck Pin
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) SCI I/O port block diagrams are shown in figures 15.2 to 15.4. Reset SPB1IO Internal data bus SPTRW Reset SPB1DT SPTRW Clock output enable signal Serial clock output signal Serial clock input signal...
Page 676: Figure 15.3 Txd Pin
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Reset SPB0IO Internal data bus SPTRW Reset SPB0DT Transmit enable signal SPTRW Serial transmit data Legend: SPTRW: Write to SPTR Figure 15.3 TxD Pin Serial receive data Internal data bus...
Page 677: Bit Rate Register (Scbrr1)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 15.2.9 Bit Rate Register (SCBRR1) Bit: Initial value: R/W: SCBRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR1.
Page 678 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group The bit rate error in asynchronous mode is found from the following equation: Pck × 10 × 100 Error (%) = – 1 (N + 1) × B × 64 × 2 2n –...
Page 679: Table 15.3 Examples Of Bit Rates And Scbrr1 Settings In Asynchronous Mode
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode Pck (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.00 0.16...
Page 680 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Pck (MHz) 6.144 7.37288 Bit Rate Error Error Error Error (bits/s) –0.44 0.08 –0.07 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 1200 0.16 0.00 0.00...
Page 681 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Pck (MHz) 14.7456 19.6608 Bit Rate Error Error Error Error (bits/s) 0.70 0.03 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00...
Page 682: Table 15.4 Examples Of Bit Rates And Scbrr1 Settings In Synchronous Mode
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode Pck (MHz) 28.7 Bit Rate (bits/s) — — — — — — — — — — — —...
Page 683: Table 15.5 Maximum Bit Rate For Various Frequencies With Baud Rate Generator (Asynchronous Mode)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator...
Page 684: Table 15.6 Maximum Bit Rate With External Clock Input (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pck (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864...
Page 685: Operation
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 15.3 Operation 15.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses.
Page 686: Table 15.8 Scsmr1 Settings For Serial Transfer Format Selection
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection SCSMR1 Settings SCI Transfer Format Multi- Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: Data processor Parity Stop Bit...
Page 687: Operation In Asynchronous Mode
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection SCSMR1 SCSCR1 Setting SCI Transmit/Receive Clock Bit 7: Bit 1: Bit 0: Clock CKE1 CKE0 Mode Source SCK Pin Function...
Page 688: Figure 15.5 Data Format In Asynchronous Communication (Example With 8-Bit Data, Parity, Two Stop Bits)
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Idle state (mark state) (LSB) (MSB) Serial data Start Parity Stop bit(s) Transmit/receive data 1 bit 7 or 8 bits 1 bit, 1 or or none 2 bits One unit of transfer data (character or frame) Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data,...
Page 689: Table 15.10 Serial Transfer Formats (Asynchronous Mode)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Table 15.10 Serial Transfer Formats (Asynchronous Mode) SCSMR1 Settings Serial Transfer Format and Frame Length CHR PE MP STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data...
Page 690: Figure 15.6 Relation Between Output Clock And Transfer Data Phase
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group MPB: Multiprocessor bit Note: An asterisk in the table means “Don't care.” Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1.
Page 691: Figure 15.7 Sample Sci Initialization Flowchart
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 1. Set the clock selection in SCSCR1. Initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits...
Page 692: Figure 15.8 Sample Serial Transmission Flowchart
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group 1. SCI status check and transmit data Start of transmission write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear Read TDRE flag in SCSSR1 the TDRE flag to 0.
Page 693 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
Page 694: Figure 15.9 Example Of Transmit Operation In Asynchronous Mode (Example With 8-Bit Data, Parity, One Stop Bit)
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Start Data Parity Stop Start Data Parity Stop Serial Idle state data (mark state) TDRE TEND TXI interrupt TXI interrupt request request TEI interrupt Data written to SCTDR1 request and TDRE flag cleared to...
Page 695: Figure 15.10 Sample Serial Reception Flowchart (1)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 1. Receive error handling and Start of reception break detection: If a receive error occurs, read the ORER, PER, and FER flags in Read ORER, PER, and FER flags SCSSR1 to identify the error.
Page 696 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCSCR1 to 0 PER = 1? Parity error handling Clear ORER, PER, and FER flags in SCSSR1 to 0 Figure 15.10 Sample Serial Reception Flowchart (2)
Page 697: Table 15.11 Receive Error Conditions
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception.
Page 698: Multiprocessor Communication Function
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Start Data Parity Stop Start Data Parity Stop Serial data RDRF RXI interrupt request SCRDR1 data read and ERI interrupt request RDRF flag cleared to 0 generated by framing One frame...
Page 699: Figure 15.12 Example Of Inter-Processor Communication Using Multiprocessor Format (Transmission Of Data H'aa To Receiving Station A)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Figure 15.12 shows an example of inter-processor communication using a multiprocessor format. Note: Even when this LSI has received data with a 0 multiprocessor bit that was meant to be sent to another station, the RDRF flag in SCSSR1 is set to 1.
Page 700 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Data Transfer Formats There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 15.10. Clock See the description under Clock in section 15.3.2, Operation in Asynchronous Mode.
Page 701: Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Start of transmission 1. SCI status check and ID data write: Read SCSSR1 and check that the Read TEND flag in SCSSR1 TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1.
Page 702 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
Page 703: Figure 15.14 Example Of Sci Transmit Operation (Example With 8-Bit Data, Multiprocessor Bit, One Stop Bit)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Multi- Multi- Multi- Start Data Stop Start Data Stop Start Data Stop proces- proces- proces- sor bit sor bit sor bit Serial Idle state D0 D1 D0 D1 D0 D1...
Page 704 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group When using software processing to determine whether received data is ID (MPB = 1) or data (MPB = 0), use a procedure such as saving a user-defined flag in memory to indicate receive start.
Page 705: Figure 15.15 Sample Flowchart Of Multiprocessor Serial Reception With Interrupt
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Receive data full interrupt generated User-defined receive start flag = 1? Read ORER and FER flags in SCSSR1 FER or ORER = 1 ? Read RDRF flag in SCSSR1 MPIE = 0 ?
Page 706: Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (1)
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Start of reception Set MPIE bit to 1 RXI = 1 ? User-defined receive start flag = 1? Read ORER and FER flags in SCSSR1 FER or ORER = 1 ?
Page 707: Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (2)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCSCR1 to 0 Clear ORER and FER flags in SCSSR1 to 0 Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (2)
Page 708: Figure 15.17 Example Of Sci Receive Operation (Example With 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Figure 15.17 shows an example of SCI operation for multiprocessor format reception. Data Start Stop Start Stop Data (ID1) (Data1) Serial Idle state data (mark state) MPIE RDRF SCRDR1 value...
Page 709: Operation In Synchronous Mode
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) In multiprocessor mode serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception.
Page 710 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group In synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock.
Page 711: Figure 15.19 Sample Sci Initialization Flowchart
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 1. Set the clock selection in SCSCR1. Initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Clear TE and RE bits 2. Set the data transfer format in in SCSCR1 to 0 SCSMR1.
Page 712: Figure 15.20 Sample Serial Transmission Flowchart
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Serial Data Transmission (Synchronous Mode): Figure 15.20 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. 1. SCI status check and transmit...
Page 713 SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
Page 714: Figure 15.21 Example Of Sci Transmit Operation
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Transfer direction Serial clock Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Serial data TDRE TEND Data written to SCTDR1 TXI interrupt TEI interrupt...
Page 715: Figure 15.22 Sample Serial Reception Flowchart (1)
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 1. Receive error handling: If a Start of reception receive error occurs, read the ORER flag in SCSSR1 , and after performing the appropriate Read ORER flag in SCSSR1 error handling, clear the ORER flag to 0.
Page 716 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Error handling ORER = 1? Overrun error handling Clear ORER flag in SCSSR1 to 0 Figure 15.22 Sample Serial Reception Flowchart (2) In serial reception, the SCI operates as described below.
Page 717: Figure 15.23 Example Of Sci Receive Operation
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER Data read from RXI interrupt ERI interrupt RXI interrupt...
Page 718: Figure 15.24 Sample Flowchart For Serial Data Transmission And Reception
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group 1. SCI status check and transmit data Start of transmission/reception write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear Read TDRE flag in SCSSR1 the TDRE flag to 0.
Page 719: Sci Interrupt Sources And Dmac
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) 15.4 SCI Interrupt Sources and DMAC The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request.
Page 720: Usage Notes
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Table 15.12 SCI Interrupt Sources Interrupt DMAC Priority on Source Description Activation Reset Release Receive error (ORER, FER, or PER) Not possible High Receive data register full (RDRF) Possible Transmit data register empty (TDRE)
Page 721: Table 15.13 Scssr1 Status Flags And Transfer Of Receive Data
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data SCSSR1 Status Flags Receive Data Transfer SCRSR1 → SCRDR1 Receive Errors RDRF ORER Overrun error Framing error Parity error Overrun error + framing error...
Page 722: Figure 15.25 Receive Data Sampling Timing In Asynchronous Mode
Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group Handling of TEND Flag and TE Bit: The TEND flag is set to 1 when the stop bit of the final data segment is transmitted. If the TE bit is cleared immediately after confirming that the TEND flag was set, transmission may not complete properly because stop bit transmission processing is still underway.
Page 723: Figure 15.26 Example Of Synchronous Transmission By Dmac
SH7751 Group, SH7751R Group Section 15 Serial Communication Interface (SCI) M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
Page 724 Section 15 Serial Communication Interface (SCI) SH7751 Group, SH7751R Group • In reception, note that if RE is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK input, RDRF will be set to 1 but copying to SCRDR1 will not be possible.
Page 725: Section 16 Serial Communication Interface With Fifo (Scif)
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview This LSI is equipped with a single-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous serial communication.
Page 726 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group • Choice of serial clock source: internal clock from baud rate generator or external clock from SCK2 pin • Four interrupt sources There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error—that can issue requests independently.
Page 727: Block Diagram
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the SCIF. Internal Module data bus data bus SCSMR2 SCBRR2 SCFRDR2 SCFTDR2 (16-stage) (16-stage) SCLSR2 SCFDR2 SCFCR2 RxD2...
Page 728: Pin Configuration
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group 16.1.3 Pin Configuration Table 16.1 shows the SCIF pin configuration. Table 16.1 SCIF Pins Pin Name Abbreviation Function Serial clock pin MD0/SCK2 Clock input/output Receive data pin MD2/RxD2...
Page 729: Register Descriptions
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 16.2 Register Descriptions 16.2.1 Receive Shift Register (SCRSR2) Bit: R/W: — — — — — — — — SCRSR2 is the register used to receive serial data. The SCIF sets serial data input from the RxD2 pin in SCRSR2 in the order received, starting with the LSB (bit 0), and converts it to parallel data.
Page 730: Transmit Shift Register (Sctsr2)
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group 16.2.3 Transmit Shift Register (SCTSR2) Bit: R/W: — — — — — — — — SCTSR2 is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR2 to SCTSR2, then sends the data to the TxD2 pin starting with the LSB (bit 0).
Page 731: Serial Mode Register (Scsmr2)
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.5 Serial Mode Register (SCSMR2) Bit: — — — — — — — — Initial value: R/W: Bit: — STOP — CKS1 CKS0 Initial value: R/W: SCSMR2 is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate generator clock source.
Page 732 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking.
Page 733: Serial Control Register (Scscr2)
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the on- chip baud rate generator. The clock source can be selected from Pck, Pck/4, Pck/16, and Pck/64, according to the setting of bits CKS1 and CKS0.
Page 734 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR2 to SCTSR2, the number of data bytes in the transmit FIFO register falls to or below the transmit trigger set number, and the TDFE flag in the serial status register (SCFSR2) is set to 1.
Page 735 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF. Bit 4: RE Description Reception disabled* (Initial value) Reception enabled* Notes: 1. Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their states.
Page 736: Serial Status Register (Scfsr2)
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group 16.2.7 Serial Status Register (SCFSR2) Bit: PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value: R/W: Bit: TEND TDFE Initial value: R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*...
Page 737 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) If all 16 bytes of receive data in SCFRDR2 have framing errors, the value indicated by bits FER3 to FER0 will be 0. Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during reception.*...
Page 738 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR2 when the last bit of the transmit character is sent, and transmission has been ended.
Page 739 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and new transmit data can be written to SCFTDR2.
Page 740 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 3—Framing Error (FER): Indicates whether or not a framing error has been found in the data that is to be read from the receive FIFO data register (SCFRDR2).
Page 741 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 1—Receive FIFO Data Full (RDF): Indicates that the received data has been transferred from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2).
Page 742: Bit Rate Register (Scbrr2)
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop bit of the last data received.
Page 743: Fifo Control Register (Scfcr2)
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) The SCBRR2 setting is found from the following equation. Asynchronous mode: × 10 – 1 64 × 2 × B 2n – 1 Where B: Bit rate (bits/s) N: SCBRR2 setting for baud rate generator (0 ≤...
Page 744 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR2 can be read or written to by the CPU at all times.
Page 745 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR2).
Page 746: Fifo Data Count Register (Scfdr2)
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive input pin (RxD2), and the RTS2 pin and CTS2 pin, enabling loopback testing. Bit 0: LOOP...
Page 747: Serial Port Register (Scsptr2)
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.11 Serial Port Register (SCSPTR2) Bit: — — — — — — — — Initial value: R/W: Bit: RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPB2IO SPB2DT Initial value: —...
Page 748 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port RTS2 pin input/output data. Input or output is specified by the RTSIO bit (see the description of bit 7, RTSIO, for details).
Page 749 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Bit 2—Serial Port Clock Port Data (SCKDT): Specifies the I/O data for the SCK2 pin serial port. The SCKIO bit specified input or output. (See bit 3: SCKIO, for details.) When set for output, the value of the SCKDT bit is output to the SCK2 pin.
Page 750: Figure 16.2 Md8/Rts2 Pin
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group SCIF I/O port block diagrams are shown in figures 16.2 to 16.6. Reset RTSIO Internal data bus SPTRW Reset MD8/RTS2 RTSDT SCIF Modem control SPTRW enable signal* RTS2 signal...
Page 751: Figure 16.3 Md7/Cts2 Pin
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Reset CTSIO Internal data bus SPTRW Reset MD7/CTS2 CTSDT SCIF SPTRW Mode setting register CTS2 signal Modem control enable signal* SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2.
Page 752: Figure 16.4 Md1/Txd2 Pin
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Reset SPB2IO Internal data bus SPTRW Reset MD1/TxD2 SPB2DT SCIF Transmit enable SPTRW signal Mode setting register Serial transmit data Legend: SPTRW: Write to SPTR Figure 16.4 MD1/TxD2 Pin...
Page 753: Figure 16.6 Md0/Sck2 Pin
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Reset SCKIO Internal data bus SPTRW Reset MD0/SCK2 SCKDT SCIF SPTRW Clock output enable signal Serial clock output signal Mode setting register Serial clock input signal Clock input enable signal...
Page 754: Line Status Register (Sclsr2)
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group 16.2.12 Line Status Register (SCLSR2) Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — ORER Initial value:...
Page 755: Operation
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 16.3 Operation 16.3.1 Overview The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character. See section 15.3.2, Operation in Asynchronous Mode, for details.
Page 756: Table 16.3 Scsmr2 Settings For Serial Transfer Format Selection
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection SCSMR2 Settings SCIF Transfer Format Bit 6: Bit 5: Bit 3: Data Multiprocessor Parity Stop Bit STOP Mode Length...
Page 757: Serial Operation
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.2 Serial Operation Data Transfer Format Table 16.5 shows the data transfer formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR2 settings.
Page 758 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK2 pin can be selected as the SCIF's serial clock, according to the setting of the CKE1 bit in SCSCR2.
Page 759: Figure 16.7 Sample Scif Initialization Flowchart
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 1. Set the clock selection in SCSCR2. Initialization Be sure to clear bits RIE and TIE, and bits TE and RE, to 0. Clear TE and RE bits 2.
Page 760: Figure 16.8 Sample Serial Transmission Flowchart
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Serial Data Transmission: Figure 16.8 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. SCIF status check and transmit data...
Page 761 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR2, the SCIF transfers the data from SCFTDR2 to SCTSR2 and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR2) is set to 1 before writing transmit data to SCFTDR2.
Page 762: Figure 16.9 Example Of Transmit Operation (Example With 8-Bit Data, Parity, One Stop Bit)
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Start Data Parity Stop Start Data Parity Stop Serial Idle state data (mark state) TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR2 and TDFE flag read as 1...
Page 763: Figure 16.11 Sample Serial Reception Flowchart (1)
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Reception: Figure 16.11 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception 1.
Page 764: Figure 16.11 Sample Serial Reception Flowchart (2)
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group 1. Whether a framing error or parity error Error handling has occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in ORER = 1? SCFSR2.
Page 765 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception.
Page 766: Figure 16.12 Example Of Scif Receive Operation
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Figure 16.12 shows an example of the operation for reception. Start Data Parity Stop Start Data Parity Stop Serial data RXI interrupt request Data read and RDF flag...
Page 767: Scif Interrupt Sources And The Dmac
SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) 16.4 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receive- error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request.
Page 768: Usage Notes
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Table 16.6 SCIF Interrupt Sources Interrupt DMAC Priority on Source Description Activation Reset Release Interrupt initiated by receive error flag (ER) Not possible High Interrupt initiated by receive FIFO data full flag...
Page 769 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the FIFO data count register (SCFDR2). Break Detection and Processing: Break signals can be detected by reading the RxD2 pin directly when a framing error (FER) is detected.
Page 770: Figure 16.14 Receive Data Sampling Timing In Asynchronous Mode
Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks...
Page 771 SH7751 Group, SH7751R Group Section 16 Serial Communication Interface with FIFO (SCIF) When Using the DMAC: When using the DMAC for transmission/reception, inhibit output of RXI and TXI interrupt requests to the interrupt controller. If interrupt request output is enabled, interrupt requests to the interrupt controller will be cleared by the DMAC without regard to the interrupt handler.
Page 772 Section 16 Serial Communication Interface with FIFO (SCIF) SH7751 Group, SH7751R Group Page 718 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 773: Section 17 Smart Card Interface
SH7751 Group, SH7751R Group Section 17 Smart Card Interface Section 17 Smart Card Interface 17.1 Overview The serial communication interface (SCI) supports a subset of the ISO/IEC 7816-3 (identification cards) standard as an extended function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting.
Page 774: Block Diagram
Section 17 Smart Card Interface SH7751 Group, SH7751R Group 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCBRR1 SCRDR1 SCSCMR1 SCTDR1 SCSSR1 SCSCR1 SCRSR1 SCTSR1 Baud rate SCSMR1...
Page 775: Pin Configuration
SH7751 Group, SH7751R Group Section 17 Smart Card Interface 17.1.3 Pin Configuration Table 17.1 shows the smart card interface pin configuration. Table 17.1 Smart Card Interface Pins Pin Name Abbreviation Function Serial clock pin Clock input/output Receive data pin Input...
Page 776: Register Descriptions
Section 17 Smart Card Interface SH7751 Group, SH7751R Group 17.2 Register Descriptions Only registers that have been added, and bit functions that have been modified, for the smart card interface are described here. 17.2.1 Smart Card Mode Register (SCSCMR1) SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function.
Page 777: Serial Mode Register (Scsmr1)
SH7751 Group, SH7751R Group Section 17 Smart Card Interface Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0: SMIF Description Smart card interface function is disabled (Initial value) Smart card interface function is enabled 17.2.2...
Page 778: Serial Control Register (Scscr1)
Section 17 Smart Card Interface SH7751 Group, SH7751R Group 17.2.3 Serial Control Register (SCSCR1) Bits 1 and 0 of SCSCR1 have a different function in smart card interface mode. Bit: — — CKE1 CKE0 Initial value: R/W: Bits 7 to 4: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details.
Page 779: Serial Status Register (Scssr1)
SH7751 Group, SH7751R Group Section 17 Smart Card Interface 17.2.4 Serial Status Register (SCSSR1) Bit 4 of SCSSR1 has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2 (TEND) are also different.
Page 780: Operation
Section 17 Smart Card Interface SH7751 Group, SH7751R Group Bit 2—Transmit End (TEND): The setting conditions for the TEND flag are as follows. Bit 2: TEND Description Transmission in progress [Clearing condition] When 0 is written to TDRE after reading TDRE = 1...
Page 781: Pin Connections
SH7751 Group, SH7751R Group Section 17 Smart Card Interface 17.3.2 Pin Connections Figure 17.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected outside the chip.
Page 782: Data Format
Section 17 Smart Card Interface SH7751 Group, SH7751R Group 17.3.3 Data Format Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting side to request retransmission of the data.
Page 783: Register Settings
SH7751 Group, SH7751R Group Section 17 Smart Card Interface If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor.
Page 784: Figure 17.4 Tend Generation Timing
Section 17 Smart Card Interface SH7751 Group, SH7751R Group I/O data Ds Da Db Dc Dd De Dg Dh Dp Guard time 12.5 etu GM = 0 (TEND interrupt) 11.0 etu GM = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Figure 17.4 TEND Generation Timing...
Page 785: Clock
SH7751 Group, SH7751R Group Section 17 Smart Card Interface Inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SCSMR1 is set to odd parity mode. (This applies to both transmission and reception).
Page 786: Table 17.4 Values Of N And Corresponding Cks1 And Cks0 Settings
Section 17 Smart Card Interface SH7751 Group, SH7751R Group Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings CKS1 CKS0 Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) Pck (MHz) 7.1424...
Page 787: Table 17.7 Maximum Bit Rate At Various Frequencies (Smart Card Interface Mode)
SH7751 Group, SH7751R Group Section 17 Smart Card Interface Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) Pck (MHz) Maximum Bit Rate (bits/s) 7.1424 19200 10.00 26882 10.7136 28800 16.00 43010 20.00 53763 25.0 67204 30.0 80645 33.0...
Page 788: Data Transfer Operations
Section 17 Smart Card Interface SH7751 Group, SH7751R Group Width is Width is Port value undefined undefined Port value (a) When GM = 0 Specified Specified CKE1 value width width CKE1 value (b) When GM = 1 Figure 17.6 Difference in Clock Output According to GM Bit Setting 17.3.6...
Page 789: Figure 17.7 Sample Initialization Flowchart
SH7751 Group, SH7751R Group Section 17 Smart Card Interface Initialization Clear TE and RE bits in SCSCR1 to 0 Clear FER/ERS, PER, and ORER flags in SCSCR1 to 0 In SCSMR1, set parity in O/E bit, clock in CKS1 and CKS0 bits,...
Page 790 Section 17 Smart Card Interface SH7751 Group, SH7751R Group Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17.8 shows a sample transmission processing flowchart.
Page 791: Figure 17.8 Sample Transmission Processing Flowchart
SH7751 Group, SH7751R Group Section 17 Smart Card Interface Start Initialization Start of transmission FER/ERS = 0? Error handling TEND = 1? Write transmit data to SCTDR1, and clear TDRE flag in SCSSR1 to 0 All data transmitted? FER/ERS = 0?
Page 792 Section 17 Smart Card Interface SH7751 Group, SH7751R Group Serial Data Reception: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 17.9 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above.
Page 793: Figure 17.9 Sample Reception Processing Flowchart
SH7751 Group, SH7751R Group Section 17 Smart Card Interface Start Initialization Start of reception ORER = 0 and PER = 0? Error handling RDRF = 1? Read receive data from SCRDR1 and clear RDRF flag in SCSSR1 to 0 All data received?
Page 794: Table 17.9 Smart Card Mode Operating States And Interrupt Sources
Section 17 Smart Card Interface SH7751 Group, SH7751R Group Interrupt Operation: There are three interrupt sources in smart card interface mode, generating transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request cannot be used in this mode.
Page 795: Usage Notes
SH7751 Group, SH7751R Group Section 17 Smart Card Interface When performing data transfer using the DMAC, it is essential to set and enable the DMAC before carrying out SCI settings. For details of the DMAC setting procedures, see section 14, Direct Memory Access Controller (DMAC).
Page 796 Section 17 Smart Card Interface SH7751 Group, SH7751R Group The receive margin in smart card mode can therefore be expressed as shown in the following equation. | D – 0.5 | (1 + F) × 100% M = (0.5 –...
Page 797: Figure 17.11 Retransfer Operation In Sci Receive Mode
SH7751 Group, SH7751R Group Section 17 Smart Card Interface nth transfer frame Retransferred frame Transfer frame n+1 (DE) D1 D2 D3 D4 D5 D6 D7 Dp D0 D1 D5 D6 D7 Dp RDRF Figure 17.11 Retransfer Operation in SCI Receive Mode Retransfer Operation when SCI is in Transmit Mode: Figure 17.12 illustrates the retransfer...
Page 798: Figure 17.13 Procedure For Stopping And Restarting The Clock
Section 17 Smart Card Interface SH7751 Group, SH7751R Group (3) Standby Mode and Clock When switching between smart card interface mode and standby mode, the following procedures should be used to maintain the clock duty cycle. Switching from Smart Card Interface Mode to Standby Mode: 1.
Page 799 SH7751 Group, SH7751R Group Section 17 Smart Card Interface (4) Power-On and Clock The following procedure should be used to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential.
Page 800 Section 17 Smart Card Interface SH7751 Group, SH7751R Group Page 746 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 801: Section 18 I/O Ports
SH7751 Group, SH7751R Group Section 18 I/O Ports Section 18 I/O Ports 18.1 Overview This LSI has a 32-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port. 18.1.1 Features The features of the general-purpose I/O port are as follows: •...
Page 802: Block Diagrams
Section 18 I/O Ports SH7751 Group, SH7751R Group 18.1.2 Block Diagrams Figure 18.1 is a block diagram of the 16-bit general-purpose I/O port A with interrupt function. PBnPUP Pull-up resistor PORTEN Internal bus Port 15 (input/ ADn output data output)/AD15...
Page 803: Figure 18.2 16-Bit Port B
SH7751 Group, SH7751R Group Section 18 I/O Ports Figure 18.2 is a block diagram of the 16-bit general-purpose I/O port B, which has no interrupt function. PBnPUP Pull-up resistor PORTEN Internal bus Port 31 (input/ ADn output data output)/AD31 Port 16 (input/...
Page 804: Figure 18.3 Sck Pin
Section 18 I/O Ports SH7751 Group, SH7751R Group SCI I/O port block diagrams are shown in figures 18.3 to 18.5. Reset SPB1IO Internal data bus SPTRW Reset SPB1DT SPTRW Clock output enable signal Serial clock output signal Serial clock input signal...
Page 805: Figure 18.4 Txd Pin
SH7751 Group, SH7751R Group Section 18 I/O Ports Reset SPB0IO Internal data bus SPTRW Reset SPB0DT Transmit enable signal SPTRW Serial transmit data Legend: SPTRW: Write to SPTR Figure 18.4 TxD Pin Serial receive data Internal data bus SPTRR Legend: Read SPTR Figure 18.5 RxD Pin...
Page 806: Figure 18.6 Md1/Txd2 Pin
Section 18 I/O Ports SH7751 Group, SH7751R Group SCIF I/O port block diagrams are shown in figures 18.6 to 18.10. Reset SPB2IO Internal data bus SPTRW Reset MD1/TxD2 SPB2DT SCIF Transmit enable SPTRW signal Mode setting register Serial transmit data...
Page 807: Figure 18.8 Md0/Sck2 Pin
SH7751 Group, SH7751R Group Section 18 I/O Ports Reset SCKIO Internal data bus SPTRW Reset MD0/SCK2 SCKDT SCIF SPTRW Clock output enable signal Mode setting Serial clock output signal register Serial clock input signal Clock input enable signal SPTRR Legend:...
Page 808: Figure 18.9 Md7/Cts2 Pin
Section 18 I/O Ports SH7751 Group, SH7751R Group Reset CTSIO Internal data bus SPTRW Reset MD7/CTS2 CTSDT SCIF SPTRW Mode setting register CTS2 signal Modem control enable signal* SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the CTS2 pin function.
Page 809: Pin Configuration
SH7751 Group, SH7751R Group Section 18 I/O Ports Reset RTSIO Internal data bus SPTRW Reset MD8/RTS2 RTSDT SCIF Modem control SPTRW enable signal* Mode setting register RTS2 signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the RTS2 pin function.
Page 810 Section 18 I/O Ports SH7751 Group, SH7751R Group Pin Name Signal Function Port 24 pin AD24/PORT24 I/O port Port 23 pin AD23/PORT23 I/O port Port 22 pin AD22/PORT22 I/O port Port 21 pin AD21/PORT21 I/O port Port 20 pin AD20/PORT20...
Page 811: Table 18.2 Sci I/O Port Pins
SH7751 Group, SH7751R Group Section 18 I/O Ports Table 18.2 shows the SCI I/O port pin configuration. Table 18.2 SCI I/O Port Pins Pin Name Abbreviation Function Serial clock pin Clock input/output Receive data pin Input Receive data input Transmit data pin...
Page 812: Register Configuration
Section 18 I/O Ports SH7751 Group, SH7751R Group 18.1.4 Register Configuration The 32-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port have seven registers, as shown in table 18.4. Table 18.4 I/O Port Registers Area 7 Access Name...
Page 813: Register Descriptions
SH7751 Group, SH7751R Group Section 18 I/O Ports 18.2 Register Descriptions 18.2.1 Port Control Register A (PCTRA) Port control register A (PCTRA) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port A (port 15 pin to port 0 pin). As the initial value of port data register A (PDTRA) is undefined, all the bits in the 16-bit port A should be set to output with PCTRA after writing a value to the PDTRA register.
Page 814: Port Data Register A (Pdtra)
Section 18 I/O Ports SH7751 Group, SH7751R Group Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16- bit port A is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO.
Page 815: Port Control Register B (Pctrb)
SH7751 Group, SH7751R Group Section 18 I/O Ports 18.2.3 Port Control Register B (PCTRB) Port control register B (PCTRB) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port B (port 31 pin to port 16 pin). As the initial value of port data register B (PDTRB) is undefined, each bit in the 16-bit port B should be set to output with PCTRB after writing a value to the PDTRB register.
Page 816: Port Data Register B (Pdtrb)
Section 18 I/O Ports SH7751 Group, SH7751R Group Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16- bit port B is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO.
Page 817: Gpio Interrupt Control Register (Gpioic)
SH7751 Group, SH7751R Group Section 18 I/O Ports 18.2.5 GPIO Interrupt Control Register (GPIOIC) The GPIO interrupt control register (GPIOIC) is a 16-bit readable/writable register that performs 16-bit interrupt input control. GPIOIC is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents.
Page 818: Serial Port Register (Scsptr1)
Section 18 I/O Ports SH7751 Group, SH7751R Group 18.2.6 Serial Port Register (SCSPTR1) Bit: — — — SPB1IO SPB1DT SPB0IO SPB0DT Initial value: — — R/W: — — — The serial port register (SCSPTR1) is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins.
Page 819 SH7751 Group, SH7751R Group Section 18 I/O Ports Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details).
Page 820: Serial Port Register (Scsptr2)
Section 18 I/O Ports SH7751 Group, SH7751R Group 18.2.7 Serial Port Register (SCSPTR2) Bit: — — — — — — — — Initial value: R/W: Bit: RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPB2IO SPB2DT Initial value: — — — —...
Page 821 SH7751 Group, SH7751R Group Section 18 I/O Ports Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port RTS2 pin input/output data. Input or output is specified by the RTSIO pin (see the description of bit 7, RTSIO, for details).
Page 822 Section 18 I/O Ports SH7751 Group, SH7751R Group Bit 2—Serial Port Clock Port Data (SCKDT): Specifies the I/O data for the SCK2 pin serial port. The SCKIO bit specified input or output. (See bit 3: SCKIO, for details.) When set for output, the value of the SCKDT bit is output to the SCK2 pin.
Page 823: Section 19 Interrupt Controller (Intc)
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) Section 19 Interrupt Controller (INTC) 19.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority.
Page 824: Figure 19.1 Block Diagram Of Intc
Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Input control IRL3– IRL0 (Interrupt request) Interrupt Com- (Interrupt request) Priority request parator identifier (Interrupt request) (Interrupt request) SCIF IMASK (Interrupt request) (Interrupt request) (Interrupt request) DMAC (Interrupt request) H-UDI (Interrupt request)
Page 825: Pin Configuration
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) 19.1.3 Pin Configuration Table 19.1 shows the INTC pin configuration. Table 19.1 INTC Pins Pin Name Abbreviation Function Nonmaskable interrupt Input Input of nonmaskable interrupt request input pin signal IRL3–IRL0 Interrupt input pins...
Page 826: Interrupt Sources
Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group 19.2 Interrupt Sources There are three types of interrupt sources: NMI, IRL, and on-chip peripheral modules. Each interrupt has a priority level (16–0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored.
Page 827: Irl Interrupts
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) 19.2.2 IRL Interrupts IRL interrupts are input by level at pins IRL3–IRL0. The priority level is the level indicated by pins IRL3–IRL0. An IRL3–IRL0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15).
Page 828: Table 19.3 Irl3-Irl0 Pins And Interrupt Levels
Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Table 19.3 IRL3–IRL0 Pins and Interrupt Levels IRL3 IRL2 IRL1 IRL0 Interrupt Priority Level Interrupt Request Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request...
Page 829: On-Chip Peripheral Module Interrupts
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) 19.2.3 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following ten modules: • High-performance user debug interface unit (H-UDI) • Direct memory access controller (DMAC) • Timer unit (TMU) •...
Page 830: Interrupt Exception Handling And Priority
Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group 19.2.4 Interrupt Exception Handling and Priority Table 19.4 lists the codes for the interrupt event register (INTEVT), and the order of interrupt priority. Each interrupt source is assigned a unique INTEVT code. The start address of the interrupt handler is common to each interrupt source.
Page 831: Table 19.4 Interrupt Exception Handling Sources And Priority Order
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) Table 19.4 Interrupt Exception Handling Sources and Priority Order INTEVT Interrupt Priority IPR (Bit Priority within Default Interrupt Source Code (Initial Value) Numbers) IPR Setting Unit Priority H'1C0 — — High IRL3–IRL0 = 0 H'200...
Page 832 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group INTEVT Interrupt Priority IPR (Bit Priority within Default Interrupt Source Code (Initial Value) Numbers) IPR Setting Unit Priority PCIC PCISERR H'A00 15–0 (0) INTPRI00 — High (3–0) PCIERR H'AE0 15–0 (0)
Page 833 SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) TICPI2: Input capture interrupt ATI: Alarm interrupt PRI: Periodic interrupt CUI: Carry-up interrupt ERI: Receive-error interrupt RXI: Receive-data-full interrupt TXI: Transmit-data-empty interrupt TEI: Transmit-end interrupt BRI: Break interrupt request ITI: Interval timer interrupt...
Page 834: Register Descriptions
Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group 19.3 Register Descriptions 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized to H'0000 and IPRD is to H'DA74 by a reset.
Page 835: Interrupt Control Register (Icr)
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) Table 19.5 Interrupt Request Sources and IPRA–IPRD Registers Bits Register 15–12 11–8 7–4 3–0 Interrupt priority register A TMU0 TMU1 TMU2 Interrupt priority register B REF* SCI1 Reserved* Interrupt priority register C...
Page 836 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. It cannot be modified.
Page 837: Interrupt Priority Level Settting Register 00 (Intpri00)
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) Bit 7—IRL Pin Mode (IRLM): Specifies whether pins IRL3–IRL0 are to be used as level- encoded interrupt requests or as four independent interrupt requests. Bit 7: IRLM Description IRL pins used as level-encoded interrupt requests...
Page 838: Interrupt Factor Register 00 (Intreq00)
Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group As shown in table 19.6, 8 combinations of internal peripheral modules are assigned to one register. Values of H'F (1111) to H'0 (0000) can be set in each 4 bits, allowing the order levels of the corresponding interrupts to be set.
Page 839: Interrupt Mask Clear Register 00 (Intmskclr00)
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) To clear each interrupt mask, write 1 to the corresponding bit of the INTMSKCLR00 register. The values in INTMSK00 do not change if you write 0 to it. Bit: . . .
Page 840: Intreq00, Intmsk00, And Intmskclr00 Bit Allocation
Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Bits 31 to 0—Interrupt Mask Clear: These bits indicate the existence of an interrupt request corresponding to each bit. For the correspondence between bits and interrupt sources, see section 19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation.
Page 841: Intc Operation
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) 19.4 INTC Operation 19.4.1 Interrupt Operation Sequence The sequence of operations when an interrupt is generated is described below. Figure 19.3 shows a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller.
Page 842: Figure 19.3 Interrupt Operation Flowchart
Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Register 00 (INTMSK00), and section 19.3.6, Interrupt Mask Clear Register 00 (INTMSKCLR00), for details. Program execution state Interrupt generated? (BL bit in SR = 0) or (sleep or standby mode)? NMIB in...
Page 843: Multiple Interrupts
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) 19.4.2 Multiple Interrupts When handling multiple interrupts, interrupt handling should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in the INTEVT register. The code in INTEVT can be used as a branch-offset for branching to the specific handler.
Page 844: Interrupt Response Time
Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group 19.5 Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table 19.8.
Page 845: Usage Notes
SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) 19.6 Usage Notes 19.6.1 NMI Interrupts (SH7751 Only) When multiple NMI interrupts are input to the NMI pin within a set period of time (which is dependent on the internal state of the CPU and the external bus state), subsequent interrupts may not be accepted.
Page 846 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; R0 : tmp ;; R1 : Original SR ;; R2 : Original ICR ;; R3 : ICR Address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; NMIH: ; (1) Set SR.IMASK = H'F SR, R1 ;...
Page 847 SH7751 Group, SH7751R Group Section 19 Interrupt Controller (INTC) R1, SR ; Restore SR NMIH3 NMIH1: NMIH2 NMIH3: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; R01UH0457EJ0301 Rev. 3.01 Page 793 of 1128 Sep 24, 2013...
Page 848 Section 19 Interrupt Controller (INTC) SH7751 Group, SH7751R Group Page 794 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 849: Section 20 User Break Controller (Ubc)
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Section 20 User Break Controller (UBC) 20.1 Overview The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU.
Page 850: Block Diagram
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the UBC. Access Address Data control Channel A Access BBRA comparator BARA Address BASRA comparator BAMRA Channel B Access BBRB...
Page 851: Table 20.1 Ubc Registers
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Table 20.1 shows the UBC registers. Table 20.1 UBC Registers Area 7 Access Name Abbreviation Initial Value P4 Address Address Size Break address BARA Undefined H'FF200000 H'1F200000 register A Break address...
Page 852: Register Descriptions
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group 20.2 Register Descriptions 20.2.1 Access to UBC Registers The access size must be the same as the control register size. If the sizes are different, a write will not be effected in a UBC register write operation, and a read operation will return an undefined value.
Page 853: Break Address Register A (Bara)
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) 20.2.2 Break Address Register A (BARA) Bit: BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 Initial value: R/W: Bit: BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 Initial value: R/W:...
Page 854: Break Asid Register A (Basra)
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group 20.2.3 Break ASID Register A (BASRA) Bit: BASA7 BASA6 BASA5 BASA4 BASA3 BASA2 BASA1 BASA0 Initial value: R/W: Note: Undefined Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID used in the channel A break conditions.
Page 855: Break Bus Cycle Register A (Bbra)
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Bits 3, 1, and 0—Break Address Mask A2 to A0 (BAMA2–BAMA0): These bits specify which bits of the channel A break address (BAA31–BAA0) set in BARA are to be masked.
Page 856 Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group Bits 5 and 4—Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel A break conditions.
Page 857: Break Address Register B (Barb)
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) 20.2.6 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 20.2.7 Break ASID Register B (BASRB) BASRB is the channel B break ASID register. The bit configuration is the same as for BASRA.
Page 858: Break Data Mask Register B (Bdmrb)
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31– 0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or manual reset.
Page 859: Break Bus Cycle Register B (Bbrb)
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31–BDMB0): These bits specify whether the corresponding bit of the channel B break data (BDB31–BDB0) set in BDRB is to be masked.
Page 860 Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group Bit 15—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write).
Page 861 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Bit 6—PC Break Select B (PCBB): Specifies whether a channel B instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset.
Page 862: Operation
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group 20.3 Operation 20.3.1 Explanation of Terms Relating to Accesses An instruction access is an access that obtains an instruction. For example, the fetching of an instruction from the branch destination when a branch instruction is executed is an instruction access.
Page 863: User Break Operation Sequence
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) • Example of sequence of instructions with a branch (however, the example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch...
Page 864: Instruction Access Cycle Break
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group flags to 0. See section 20.3.6, Condition Match Flag Setting, for the exact setting conditions for the condition match flags. 4. When sequential condition mode has been selected, and the channel B condition is matched after the channel A condition has been matched, a break is effected at the instruction at which the channel B condition was matched.
Page 865: Operand Access Cycle Break
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) 4. When an instruction access cycle is set for channel B, break data register B (BDRB) is ignored in judging whether there is an instruction access match. Therefore, a break condition specified by the DBEB bit in BRCR is not executed.
Page 866: Condition Match Flag Setting
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group 20.3.6 Condition Match Flag Setting 1. Instruction access with post-execution condition, or operand access The flag is set when execution of the instruction that causes the break is completed. As an...
Page 867: Contiguous A And B Settings For Sequential Conditions
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) value saved to SPC is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made).
Page 868: Usage Notes
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group 2. Instruction access match on channel A, operand access match on channel B Instruction B is 0 or 1 instruction after Sequential operation is not guaranteed instruction A Instruction B is 2 or more instructions...
Page 869 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Pre- Post- Pre- Post- Execution Execution Execution Execution Operand Instruction Instruction Instruction Instruction Access (Address/Data) SL.BL Access Access Access Access 0 → 0 1 → 0 0 → 1 1 → 1...
Page 870: User Break Debug Support Function
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group in the case of contention between a TRAPA instruction and a post-execution break, the user break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break condition.
Page 871: Figure 20.2 User Break Debug Support Function Flowchart
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Exception/interrupt generation Hardware operation SPC ← PC SSR ← SR SR.BL ← B'1 SR.MD ← B'1 SR.RB ← B'1 Exception Trap Exception/ interrupt/trap? Interrupt EXPEVT ← H'160 EXPEVT ← exception code INTEVT ←...
Page 872: Examples Of Use
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group 20.5 Examples of Use Instruction Access Cycle Break Condition Settings • Register settings: BASRA = H'80 / BARA = H'00000404 / BAMRA = H'00 / BBRA = H'0014 / BASRB = H'70 / BARB = H'00008010 / BAMRB = H'01 /...
Page 873 SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00027128 / address mask: H'00 Bus cycle: CPU, instruction access (pre-instruction-execution), write, word ⎯ Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00...
Page 874: User Break Controller Stop Function
Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group 20.6 User Break Controller Stop Function This function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating. Note that, if you use this function, you cannot use the user break controller.
Page 875: Examples Of Stopping And Restarting The User Break Controller
SH7751 Group, SH7751R Group Section 20 User Break Controller (UBC) 20.6.3 Examples of Stopping and Restarting the User Break Controller The following are example programs: ; Transition to user break controller stopped state ; (1) Initialize BBRA and BBRB to 0.
Page 876 Section 20 User Break Controller (UBC) SH7751 Group, SH7751R Group Page 822 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 877: Section 21 High-Performance User Debug Interface (H-Udi)
SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) Section 21 High-performance User Debug Interface (H-UDI) 21.1 Overview 21.1.1 Features The high-performance user debug interface (H-UDI) is a serial input/output interface supporting a subset of the JTAG, IEEE 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture.
Page 878: Figure 21.1 Block Diagram Of H-Udi Circuit
Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Interrupt/reset etc. Break ASEBRK/BRKACK control Decoder controller TRST SDIR SDINT SDBPR SDDRH SDDRL AUDSYNC AUDCK Trace control AUDATA3–0 Figure 21.1 Block Diagram of H-UDI Circuit Page 824 of 1128 R01UH0457EJ0301 Rev.
Page 879: Pin Configuration
SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) 21.1.3 Pin Configuration Table 21.1 shows the H-UDI pin configuration. Table 21.1 H-UDI Pins Pin Name Abbreviation I/O Function When Not Used Clock pin Input Same as the JTAG serial clock input Open* pin.
Page 880: Register Configuration
Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group 3. Fixed to the ground or connected to the same signal line as RESET, or to a signal line that behaves in the same way. However, there is a problem when this pin is fixed to the ground.
Page 881: Register Descriptions
SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) 21.2 Register Descriptions 21.2.1 Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is initialized by the TRST pin or in the TAP Test-Logic-Reset state.
Page 882: Data Register (Sddr)
Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group 21.2.2 Data Register (SDDR) The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and SDDRL, that can be read and written to by the CPU. The value in this register is initialized by TRST, but not by a CPU reset.
Page 883: Interrupt Factor Register (Sdint)
SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) 21.2.4 Interrupt Factor Register (SDINT) The interrupt factor register (SDINT) is a 16-bit register that can be read/written from the CPU. When a (H-UDI interrupt) command is set in the SDIR (Update-IR) via the H-UDI pin, the INTREQ bit is set to 1.
Page 884: Table 21.3 Structure Of Boundary Scan Register
Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Table 21.3 Structure of Boundary Scan Register Pin name Type to TDO WE0/REG WE0/REG Page 830 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 885 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) Pin name Type R01UH0457EJ0301 Rev. 3.01 Page 831 of 1128 Sep 24, 2013...
Page 886 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Pin name Type CAS0/DQM0 CAS0/DQM0 CAS1/DQM1 CAS1/DQM1 RD/WR RD/WR RD/CASS/FRAME RD/CASS/FRAME Page 832 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 887 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) Pin name Type CAS2/DQM2 CAS2/DQM2 CAS3/DQM3 CAS3/DQM3 R01UH0457EJ0301 Rev. 3.01 Page 833 of 1128 Sep 24, 2013...
Page 888 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Pin name Type Page 834 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 889 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) Pin name Type WE2/ICIORD WE2/ICIORD WE3/ICIOWR WE3/ICIOWR SLEEP PCIGNT4 PCIGNT4 PCIGNT3 PCIGNT3 PCIGNT2 PCIGNT2 R01UH0457EJ0301 Rev. 3.01 Page 835 of 1128 Sep 24, 2013...
Page 890 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Pin name Type PCIREQ4 PCIREQ4 PCIREQ4 PCIREQ3/MD10 PCIREQ3/MD10 PCIREQ3/MD10 PCIREQ2/MD9 PCIREQ2/MD9 PCIREQ2/MD9 IDSEL INTA INTA PCIRST PCIRST PCICLK PCIGNT1/REQOUT PCIGNT1/REQOUT PCIREQ1/GNTIN PCIREQ1/GNTIN PCIREQ1/GNTIN SERR SERR SERR AD31 AD31 AD31...
Page 891 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) Pin name Type AD28 AD28 AD27 AD27 AD27 AD26 AD26 AD26 AD25 AD25 AD25 AD24 AD24 AD24 C/BE3 C/BE3 C/BE3 AD23 AD23 AD23 AD22 AD22 AD22 AD21 AD21 AD21...
Page 892 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Pin name Type AD18 AD18 AD17 AD17 AD17 AD16 AD16 AD16 C/BE2 C/BE2 C/BE2 PCIFRAME PCIFRAME PCIFRAME IRDY IRDY IRDY TRDY TRDY TRDY DEVSEL DEVSEL DEVSEL PCISTOP PCISTOP PCISTOP...
Page 893 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) Pin name Type C/BE1 C/BE1 C/BE1 AD15 AD15 AD15 AD14 AD14 AD14 AD13 AD13 AD13 AD12 AD12 AD12 AD11 AD11 AD11 AD10 AD10 AD10 C/BE0 C/BE0 C/BE0 R01UH0457EJ0301 Rev. 3.01...
Page 894 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Pin name Type IRL0 IRL1 IRL2 IRL3 BACK/BSREQ BACK/BSREQ BREQ/BSACK MD6/IOIS16 Page 840 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 895 SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) Pin name Type MD2/RXD2 TCLK TCLK TCLK RTS2/MD8 RTS2/MD8 RTS2/MD8 MD1/TXD2 MD1/TXD2 MD1/TXD2 MD0/SCK2 MD0/SCK2 MD0/SCK2 MD7/CTS2 MD7/CTS2 MD7/CTS2 AUDSYNC AUDSYNC AUDCK AUDCK AUDATA0 AUDATA0 AUDATA1 AUDATA1 AUDATA2 AUDATA2 R01UH0457EJ0301 Rev.
Page 896 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Pin name Type AUDATA3 AUDATA3 MD3/CE2A MD3/CE2A MD3/CE2A MD4/CE2B MD4/CE2B MD4/CE2B DACK0 DACK0 DACK1 DACK1 DRAK0 DRAK0 DRAK1 DRAK1 STATUS0 STATUS0 STATUS1 STATUS1 DREQ0 DREQ1 from TDI Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set LOW.
Page 897: Operation
SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) 21.3 Operation 21.3.1 TAP Control Figure 21.2 shows the internal states of the TAP control circuit. These conform to the state transitions specified by JTAG. • The transition condition is the TMS value at the rising edge of TCK.
Page 898: H-Udi Reset
Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group 21.3.2 H-UDI Reset A power-on reset is effected by an SDIR command. A reset is effected by sending a H-UDI reset assert command, and then sending a H-UDI reset negate command, from the H-UDI pin (see figure 21.3).
Page 899: Boundary Scan (Extest, Sample/Preload, Bypass)
SH7751 Group, SH7751R Group Section 21 High-performance User Debug Interface (H-UDI) 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) In this LSI, setting a command from the H-UDI in SDIR can place the H-UDI pins in the boundary scan mode. However, the following limitations apply.
Page 900 Section 21 High-performance User Debug Interface (H-UDI) SH7751 Group, SH7751R Group Page 846 of 1128 R01UH0457EJ0301 Rev. 3.01 Sep 24, 2013...
Page 901: Section 22 Pci Controller (Pcic)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Section 22 PCI Controller (PCIC) 22.1 Overview The PCI Controller (PCIC) controls the PCI bus and transfers data between memory connected to the external bus and a PCI device connected to the PCI bus. The ability for PCI devices to be connected directly not only facilitates the design of systems using PCI buses but also enables systems to be more compact and capable of high-speed data transfer.
Page 902: Block Diagram
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.1.2 Block Diagram Figure 22.1 is a block diagram of the PCIC. PCI bus PCIC module Interrupt PCI bus interface Interrupts control Local configuration register register Internal peripheral Data transfer FIFO...
Page 903: Pin Configuration
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.1.3 Pin Configuration Table 22.1 shows the configuration of I/O pins of the PCIC. Table 22.1 Pin Configuration I/O Status in Operating Modes Standard Host Non-host Signal Pull-up No. Pin Name...
Page 904: Register Configuration
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group I/O Status in Operating Modes Standard Host Non-host Signal Pull-up No. Pin Name Name Function Type Resistor* Master Target Master Target Remarks 17 PCIREQ2/ REQ2 Bus request — — (host function)
Page 905: Table 22.2 List Of Pci Configuration Registers
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Table 22.2 List of PCI Configuration Registers Configu- ration Area 7 Access Name Abbreviation PCI R/W PP-Bus R/W Initial Value Address Address Address Size PCI configuration PCICONF0 H'00 H'FE200000 H'1E200000 32...
Page 906: Table 22.3 Pci Configuration Register Configuration
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Table 22.3 PCI Configuration Register Configuration PCI Configuration Register Configu ration Area 7 PP-Bus Address Address Address 31 to 24 23 to 16 15 to 8 7 to 0 H'00 H'FE200000...
Page 907: Table 22.4 List Of Pcic Local Registers
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Table 22.4 List of PCIC Local Registers PCI I/O Address Abbre- PP-Bus (SH7751/ Area 7 Access Name viation Initial Value SH7751R) Address Address Size PCI control register PCICR H'000000*0 H'100/ H'FE200100...
Page 908 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group PCI I/O Address Abbre- PP-Bus (SH7751/ Area 7 Access Name viation Initial Value SH7751R) Address Address Size DMA transfer count PCIDTC0 H'00000000 H'188/ H'FE200188 H'1E200188 register 0 for PCI H'88 DMA control register 0...
Page 909 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) PCI I/O Address Abbre- PP-Bus (SH7751/ Area 7 Access Name viation Initial Value SH7751R) Address Address Size Reserved — H'00000000 — H'FE2001D8 H'1E2001D8 H'FE2001DC H'1E2001DC PCI bus control register PCIBCR1 —...
Page 910: Pcic Register Descriptions
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2 PCIC Register Descriptions 22.2.1 PCI Configuration Register 0 (PCICONF0) Bit: DEVID15 DEVID14 DEVID13 DEVID12 DEVID11 DEVID10 DEVID9 DEVID8 Initial value: PCI-R/W: PP Bus-R/W: Bit: DEVID7 DEVID6 DEVID5 DEVID4 DEVID3 DEVID2...
Page 911: Pci Configuration Register 1 (Pciconf1)
Bits 15 to 0—DNVID15 to 0: These bits specify the PCI device maker (vendor ID). (H'1054*: fixed in hardware) Note: * The vendor ID H'1054 specifies Hitachi, Ltd., but the SH7751 and SH7751R are now products of Renesas Electronics Corp. For information on these products, contact Renesas Electronics Corp. 22.2.2...
Page 912 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group PCI configuration register 1 (PCICONF1) is a 32-bit read/partial-write register that includes the status and command PCI configuration registers stipulated in the PCI local bus specifications. The status is read from bits 31 to 16 (status register) in the event of an error on the PCI bus. Bits 15 to 0 (command register) contain the settings required for initiating transfers on the PCI bus.
Page 913 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 28—Target Abort Receive Status (RTA): Indicates the termination of transaction by master abort when the PCIC is operating as the master. Bit 28: RTA Description No transaction termination using target abort...
Page 914 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 23—High-Speed Back-To-Back Status (FBBC): Shows whether a high-speed back-to-back transfer to a different target can be accepted when the PCIC is operating as a target. Bit 23: FBBC Description The target does not have a high-speed back-to-back transaction function for...
Page 915 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 8—SERR Output Control (SER): Controls the SERR output. Bit 8: SER Description SERR output disabled (Hi-Z) (Initial value) SERR output enabled Bit 7—Wait Cycle Control (WCC): Controls the address/data stepping. When WCC=1, address and data are output in master write operations, only address is output in master read operations, and only data is output in target read operations, at least in two clocks.
Page 916 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 3—Special Cycle Control (SPC): Shows whether special cycles are supported when the PCIC is operating as a target. Bit 3: SPC Description Ignore special cycle (Initial value) Monitor special cycle (not supported) Bit 2—PCI Bus Master Control (BUM): Controls the bus master operation.
Page 917: Pci Configuration Register 2 (Pciconf2)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.3 PCI Configuration Register 2 (PCICONF2) Bit: CLASS23 CLASS22 CLASS21 CLASS20 CLASS19 CLASS18 CLASS17 CLASS16 Initial value: — — — — — — — PCI-R/W: PP Bus-R/W: Bit: CLASS15 CLASS14 CLASS13 CLASS12 CLASS11 CLASS10 CLASS9 CLASS8 Initial value: —...
Page 918: Table 22.5 List Of Class23 To 16 Base Class Codes (Class23 To 16)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 24—Base Class Code (CLASS23 to 16): These bits indicate the base class code. For details of setting values, refer to table 22.5. Table 22.5 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16)
Page 919: Pci Configuration Register 3 (Pciconf3)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.4 PCI Configuration Register 3 (PCICONF3) Bit: BIST7 BIST6 BIST5 BIST4 BIST3 BIST2 BIST1 BIST0 Initial value: PCI-R/W: PP Bus-R/W: Bit: HEAD7 HEAD6 HEAD5 HEAD4 HEAD3 HEAD2 HEAD1 HEAD0 Initial value:...
Page 920 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 31—BIST7: BIST function support Bit 31: BIST7 Description Function not supported (Initial value) Function supported (not supported) Bit 30—BIST6: Used to control the BIST starting. Bit 30: BIST6 Description Execution completed...
Page 921: Pci Configuration Register 4 (Pciconf4)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 15 to 8—Latency Timer Register (LAT7 to 0): These bits specify the latency time of the PCI bus when the PCIC is operating as the master. Bits 7 to 0—Cache Line Size (CACHE7 to 0): Not supported. Memory target is set cache- disabled, and SDONE and SBO are ignored.
Page 922 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group stipulated in the PCI's local-bus specifications. PCICONF4 holds the higher-order bits of the address used when a device on the PCI bus uses I/O transfer commands to access a local register in the PCIC.
Page 923: Pci Configuration Register 5 (Pciconf5)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.6 PCI Configuration Register 5 (PCICONF5) Bit: BASE031 BASE030 BASE029 BASE028 BASE027 BASE026 BASE025 BASE024 Initial value: PCI-R/W: PP Bus-R/W: Bit: BASE023 BASE022 BASE021 BASE020 BASE019 BASE018 BASE017 BASE016 Initial value:...
Page 924: Table 22.6 Memory Space Base Address Register (Base0)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Table 22.6 Memory Space Base Address Register (BASE0) PCILSR0 [28:20] Required Address BASE0[31:20] Register Value Space Valid Writable Bits B'0_0000_0000 1 MB Bits 31 to 20 B'0_0000_0001 2 MB Bits 31 to 21...
Page 925: Pci Configuration Register 6 (Pciconf6)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 0—LA0ASI: Shows whether the base address specified by this register is an I/O space or memory space. Bit 0: LA0ASI Description Memory space (Initial value) I/O space 22.2.7 PCI Configuration Register 6 (PCICONF6)
Page 926: Table 22.7 Memory Space Base Address Register (Base1)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group local bus specifications. This register contains the most significant bits (maximum 12 in bits 31 to 20) of the address used when a device on the PCI bus accesses local memory on the SH local bus using memory transfer commands.
Page 927: Pci Configuration Register 7 (Pciconf7) To Pci Configuration Register 10
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 2 and 1—Memory Type (LA1TYPE1 to 0): These bits indicate the memory type of the local address space 1. Bit 2: LA1TYPE1 Bit 1: LA1TYPE0 Description The base address can be set to 32-bit width, 32-bit...
Page 928: Pci Configuration Register 11 (Pciconf11)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.9 PCI Configuration Register 11 (PCICONF11) Bit: SSID15 SSID14 SSID13 SSID12 SSID11 SSID10 SSID9 SSID8 Initial value: — — — — — — — — PCI-R/W: PP Bus-R/W: Bit: SSID7 SSID6...
Page 929: Pci Configuration Register 12 (Pciconf12)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 15 to 0—SVID15 to 0: Specifies the PCI subsystem vendor ID. 22.2.10 PCI Configuration Register 12 (PCICONF12) Bit: . . . — — — . . . — — —...
Page 930: Pci Configuration Register 14 (Pciconf14)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group All bits are fixed in hardware. Bits 31 to 8—Reserved: These bits are always read as 0. Bits 7 to 0—CAPPTR7 to 0: These bits specify the address offset of the extended functions (power management).
Page 931: Pci Configuration Register 15 (Pciconf15)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.13 PCI Configuration Register 15 (PCICONF15) Bit: MLAT7 MLAT6 MLAT5 MLAT4 MLAT3 MLAT2 MLAT1 MLAT0 Initial value: PCI-R/W: PP Bus-R/W: Bit: MGNT7 MGNT6 MGNT5 MGNT4 MGNT3 MGNT2 MGNT1 MGNT0 Initial value:...
Page 932 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 24—Designation of Maximum Latency (MLAT7 to 0): These bits specify the maximum time from the time the PCI master device demands bus privileges and to the time it obtains the privileges (not supported).
Page 933: Pci Configuration Register 16 (Pciconf16)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.14 PCI Configuration Register 16 (PCICONF16) Bit: D2SPT D1SPT — PMESPT4 PMESPT3 PMESPT2 PMESPT1 PMESPT0 Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — PMECLK VER2 VER1 VER0 Initial value: PCI-R/W:...
Page 934 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 27—PME Support (PMESPT4 to 0): Not supported. Defines the function state supporting PME output. Bit 26—D2 Support (D2SPT): Not supported. Specifies whether D2 state is supported. Bit 25—D1 Support (D1SPT): Not supported. Specifies whether D1 state is supported.
Page 935: Pci Configuration Register 17 (Pciconf17)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.15 PCI Configuration Register 17 (PCICONF17) Bit: DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — — — — — — Initial value:...
Page 936 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group When B'11 is written to bits 1 and 0 and a transition is made to power state D3 (power down mode), PCIC operation as a master target is disabled, regardless of the setting of bits 2 to 0 of the PCICONF1 (bus master control, memory and I/O space access control) (these bits are masked).
Page 937: 22.2.16 Reserved Area
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.16 Reserved Area Reserved area. Bit: . . . — — — . . . — — — — Initial value: . . . PCI-R/W: . . . PP Bus-R/W: . . .
Page 938: Pci Control Register (Pcicr)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.17 PCI Control Register (PCICR) Bit: — — — — — — — — Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — — — — — — Initial value: PCI-R/W:...
Page 939 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) The PCICR register is initialized at a power-on reset to H'000000*0 (bits 7 and 6 are initialized to B'00, and bits 5 and 4 sample the value of mode pins 9 and 10). At a software reset, bit 1 (RSTCTL) is not initialized.
Page 940 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 6—Bus Master Arbitration (BMABT): Controls the PCI bus arbitration mode of the PCIC when the PCIC is operating as the host. When the PCIC is non-host, the value of this bit is ignored.
Page 941 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 2—INTA Output (INTA): Software control of INTA (valid only when PCIC is not host) Bit 2: INTA Description INTA pin at Hi-Z (driven to High by pull-up resistor) (Initial value) Assert INTA (Low output) Bit 1—PCIRST Output Control (RSTCTL): Controls the PCIRST output.
Page 942: Pci Local Space Register [1:0] (Pcilsr [1:0])
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.18 PCI Local Space Register [1:0] (PCILSR [1:0]) Bit: — — — PLSR28 PLSR27 PLSR26 PLSR25 PLSR24 Initial value: PCI-R/W: PP Bus-R/W: Bit: PLSR23 PLSR22 PLSR21 PLSR20 — — — —...
Page 943 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) If you specify all zeros, a 1MB space is reserved. You can specify an address space up to 512MB. Refer to table 22.6 in section 22.2.6, PCI Configuration Register 5 (PCICONF5).
Page 944: Pci Local Address Register [1:0] (Pcilar [1:0])
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.19 PCI Local Address Register [1:0] (PCILAR [1:0]) Bit: — — — LAR28 LAR27 LAR26 LAR25 LAR24 Initial value: PCI-R/W: PP Bus-R/W: Bit: LAR23 LAR22 LAR21 LAR20 — — — —...
Page 945 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) in the most significant address bit. For example, when the capacity of the local address space is set to 32MB (PCILSR: H'01F00000), bits 28 to 25 of the local address are valid. Only the value set in these bits is used as the physical address of the local address space.
Page 946: Pci Interrupt Register (Pciint)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.20 PCI Interrupt Register (PCIINT) Bit: — — — — — — — — Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — — — — — — Initial value: PCI-R/W:...
Page 947 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) When an error occurs, the bit corresponding to the error content is set to 1. Each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it. (Write clear) Note that the error detection bits can be set even when the interrupt is masked.
Page 948 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 3—Master Target Abort Interrupt (M_TGT_ABORT): When the PCIC is master. Indicates the termination of transaction by target abort. Bit 2—Master Master Abort Interrupt (M_MST_ABORT): When the PCIC is master. Indicates the termination of transaction by master abort.
Page 949: Pci Interrupt Mask Register (Pciintm)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.21 PCI Interrupt Mask Register (PCIINTM) Bit: — — — — — — — — Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — — — — — — Initial value:...
Page 950 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bit 15—Unlocked Transfer Detection Interrupt Mask (M_LOCKON) Bit 14—Target Target Abort Interrupt Mask (T_TGT_ABORT) Bits 13 to 10—Reserved: These bits always return 0 when read.
Page 951: Pci Address Data Register At Error (Pcialr)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.22 PCI Address Data Register at Error (PCIALR) Bit: ALOG31 ALOG30 ALOG29 ALOG28 ALOG27 ALOG26 ALOG25 ALOG24 Initial value: — — — — — — — — PCI-R/W: PP Bus-R/W: Bit:...
Page 952: Pci Command Data Register At Error (Pciclr)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 0—Address Log (ALOG31 to 0): PIC address data (value of A/D line) at time of error. (Initial value is undefined.) 22.2.23 PCI Command Data Register at Error (PCICLR) Bit: —...
Page 953 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) A valid value is retained only when one of the PCIINT register bits is set to 1. The error source holding circuit can only store one error source. For this reason, any second or subsequent error factors are not stored if errors occur consecutively.
Page 954: Pci Arbiter Interrupt Register (Pciaint)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.24 PCI Arbiter Interrupt Register (PCIAINT) Bit: — — — — — — — — Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — — — — — — Initial value:...
Page 955 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) When an error is detected, the bit corresponding to the error type is set to 1. Each interrupt detection bit can be cleared to its initial status (0) by writing 1 to it. (Write clear) The error detection bits are set even when the interrupts are masked.
Page 956: Pci Arbiter Interrupt Mask Register (Pciaintm)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM) Bit: — — — — — — — — Initial value: PCI-R/W: PP Bus-R/W: Bit: — — — — — — — — Initial value:...
Page 957: Pci Error Bus Master Data Register (Pcibmlr)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 13—Master Broken Interrupt Mask (MST_BRKN) Bit 12—Target Bus Timeout Interrupt Mask (TGT_BUSTO) Bit 11—Master Bus Timeout Interrupt Mask (MST_BUSTO) Bits 10 to 4—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing.
Page 958: Pci Dma Transfer Arbitration Register (Pcidmabt)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group The bus master data holding circuit can only store data for one master. For this reason, no bus master data is stored for any second or subsequent errors if errors occur consecutively.
Page 959: Pci Dma Transfer Pci Address Register [3:0] (Pcidpa [3:0])
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 31 to 1—Reserved: These bits always returns 0 when read. Always write 0 to these bits when writing. Bit 0—DMA Arbitration Mode (DMABT): Controls the DMA arbitration mode. Bit 0: DMABT Description Priority-fixed (Channel 0 >...
Page 960 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group The DMA transfer PCI address register [3:0] (PCIDPA [3:0]) specifies the starting address at the PCI when performing DMA transfers. This 32-bit read/write register can be accessed from both the PP bus and PCI bus.
Page 961: Pci Dma Transfer Local Bus Start Address Register [3:0] (Pcidla [3:0])
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.29 PCI DMA Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0]) Bit: — — — PDLA28 PDLA27 PDLA26 PDLA25 PDLA24 Initial value: PCI-R/W: PP Bus-R/W: Bit: PDLA23 PDLA22 PDLA21 PDLA20 PDLA19 PDLA18 PDLA17 PDLA16...
Page 962: Pci Dma Transfer Counter Register [3:0] (Pcidtc [3:0])
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Always write to this register prior to starting DMA transfers. After a DMA transfer starts, the register value is not retained. Always re-set this register before starting a new DMA transfer after a DMA transfer has completed.
Page 963 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) The DMA transfer counter register [3:0] (PCIDTC [3:0]) specifies the number of bytes for DMA transfers. This 32-bit read/write register can be accessed from both the PP bus and PCI bus. When read during a DMA transfer, it returns the remaining number of bytes in the DMA transfer.
Page 964: Pci Dma Control Register [3:0] (Pcidcr [3:0])
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0]) Bit: . . . — — — . . . — — — — Initial value: . . . PCI-R/W: . . .
Page 965 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 31 to 11—Reserved: These bits always return 0 when read. Always write 0 to these bits. Bits 10 and 9—Alignment Mode (ALNMD): Sets data alignment when local bus is big endian...
Page 966 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 5—Local Address Control (LAHOLD): Local address control during DMA transfer Bit 5: LAHOLD Description Incremented (Initial value) High address fixed (Address A[4:0] is incremented) Bit 4—Reserved: This bit always returns 0 when read. Always write 0 to this bit.
Page 967: Pio Address Register (Pcipar)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.32 PIO Address Register (PCIPAR) Bit: — — — — — — — CFGEN Initial value: PCI-R/W: — — — — — — — — PP Bus-R/W: Bit: BUSNO23 BUSNO22 BUSNO21 BUSNO20 BUSNO19 BUSNO18 BUSNO17 BUSNO16 Initial value: —...
Page 968 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bit 31 (CFGEN) is set in hardware and none of the other bits of the PCIPAR register are initialized at a power-on reset or software reset. Always write to this register prior to accessing the PCI configuration space. After setting a value in this register, generate the configuration cycle by reading or writing to the PIO data register (PCIPDR).
Page 969: Memory Space Base Register (Pcimbr)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.33 Memory Space Base Register (PCIMBR) Bit: MBR31 MBR30 MBR29 MBR28 MBR27 MBR26 MBR25 MBR24 Initial value: PCI-R/W: — — — — — — — — PP Bus-R/W: Bit: — —...
Page 970 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Always write to this register prior to performing memory read/write operations by PIO transfer. Bits 31 to 24—Memory Space Base Address (MBR31 to 24): Sets the base address for the PCI memory space in PIO transfers.
Page 971: I/O Space Base Register (Pciiobr)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.34 I/O Space Base Register (PCIIOBR) Bit: IOBR31 IOBR30 IOBR29 IOBR28 IOBR27 IOBR26 IOBR25 IOBR24 Initial value: PCI-R/W: — — — — — — — — PP Bus-R/W: Bit: IOBR23 IOBR22...
Page 972: Pci Power Management Interrupt Register (Pcipint)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Always write to this register prior to I/O space read and I/O space write operations by PIO transfer. Bits 31 to 18—I/O Space Base Address (IOBR31 to 18): Sets the base register for the PCI I/O space in PIO transfers.
Page 973: Pci Power Management Interrupt Mask Register (Pcipintm)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) The PCIPINT register is initialized to H'00000000 at a power-on reset. It is not initialized at a software reset. When an interrupt is detected, the bit corresponding to the content of that interrupt is set to 1.
Page 974: Pci Clock Control Register (Pciclkr)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 1—Power State D3 (DPERR_WT): Transition request to power-down mode interrupt mask for this LSI.
Page 975: 22.2.38 Pcic-Bsc Registers
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bits 31 to 2—Reserved: These bits are always read as 0. When writing, always write H'A5 to bits 31 to 24, and 0 to the other bits. Always write 0 to these bits when writing.
Page 976 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group • The PCIC-BSC performs the same operations as the slave mode of the BSC. Therefore, the MATER bit of the PCI bus control register 1 (PCIBCR1) shows the slave status. • Because the PCIC-BSC operates in slave mode, the bus privilege is handed to the BSC once per bus cycle.
Page 977: Port Control Register (Pcipctr)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.2.39 Port Control Register (PCIPCTR) Bit: — — — — — — — — Initial value: PCI-R/W: — — — — — — — — PP Bus-R/W: Bit: — — —...
Page 978 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Bits 31 to 19—Reserved: These bits always return 0 when read. Always write 0 to these bits when writing. Bit 18—Port 2 Enable (PORT2EN): Provides the enable control for the port 2.
Page 979 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 3—Port 1 Pull-up Resistance Control (PB1PUP): Controls pull-up resistance when PCIREQ3 pin is used as port. Bit 3: PB1PUP Description Pull-up PCIREQ3 pin (Initial value) Do not pull-up PCIREQ3 pin Bit 2—Port 1 Input/Output Control (PB1IO): Controls input or output when PCIREQ3 is used...
Page 980: Port Data Register (Pcipdtr)
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.2.40 Port Data Register (PCIPDTR) Bit: . . . — — — . . . — — — — Initial value: . . . PCI-R/W: — — — . . .
Page 981: Pio Data Register (Pcipdr)
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Bit 1—Port 0 Output Data (PB1DT): Output data when PCIGNT2 pin is used as port. (PCIGNT2 pin is output-only.) Bit 0—Port 0 Input/Output Data (PB0DT): Receives input data and sets output data when the PCIREQ2 pin is used as a port.
Page 982: Description Of Operation
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Always write to this register before accessing the PCI configuration space. Always read/write to this register after setting the value in the PIO address register (PCIPAR). The configuration cycle on the PCI bus can be generated by reading/writing to this register.
Page 983: Pci Commands
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.3.2 PCI Commands Table 22.9 lists the PCI commands and shows the PCIC support. Table 22.9 PCI Command Support Non-Host Host Operation Operation Command Master Target Master Target Remarks Memory read Δ...
Page 984: Pcic Initialization
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 22.3.3 PCIC Initialization After a power-on reset, the configuration register initialization bit (CFINIT) of the PCI control register (PCICR) is cleared. At this point, if the PCIC is operating as the PCI bus host, the bus privileges are permanently granted to the PCIC, and no device arbitration is performed on the PCI bus.
Page 985: Local Register Access
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) 22.3.4 Local Register Access Only longword (32-bit) access of the PCIC's internal local registers and configuration registers from the CPU is supported. (It is possible to use PIO transfers to perform byte, word, and longword access of the memory space and I/O space on the PCI bus.)
Page 986 Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Inter-PCI Device Arbitration: The PCI bus arbitration circuit in the PCIC can be used when the PCIC is operating as the host device. The arbitration circuit can be connected to up to four external PCI devices (devices that can operate as master devices) that request bus privileges.
Page 987 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Initial order of priority PCIC > device 1 > device 2 > device 3 > device 4 (transfer by device 1) Order of priority after transfer PCIC > device 2 > device 3 > device 4 > device 1...
Page 988: Pci Bus Arbitration In Non-Host Mode
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group When using the CKIO clock, please note the limitations on CKIO clock frequency, stability, and load capacitance that can be connected to the CKIO pin. Check the clock oscillation circuit and electrical characteristics in section 10, Clock Oscillation Circuits, and section 23, Electrical Characteristics.
Page 989 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) Memory Transfers: This section describes how PIO transfers are used to access memory space. 16MB between H'FD000000 and H'FDFFFFFF of area P4 (H'1D000000 to H'1DFFFFFF in area 7) is allocated as PCI memory address space. This space is used as the least significant 24 bits of the PCI address.
Page 990: Figure 22.2 Pio Memory Space Access
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group H'FD000000 PCI memory 16 Mbytes space H'FDFFFFFF 24 23 PCI memory H'FD space address 24 23 PCI address 24 23 PCIMBR LOCK identifier Figure 22.2 PIO Memory Space Access I/O Transfers: This section describes how to access I/O space using PIO transfers. The 256KB from H'FE240000 to H'FE27FFFF of area P4 (H'1E240000 to H'1E27FFFF in area 7) is allocated as PCI I/O address space.
Page 991: Target Transfers
SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) H'FE200000 PCI register space 256 Kbytes H'FE23FFFF H'FE240000 PIC I/O space 256 Kbytes H'FE27FFFF 18 17 PCI I/O space H'FE24–H'FE27 address 18 17 PCI address 18 17 PCIIOBR LOCK identifier Figure 22.3 PIO I/O Space Access PIO Transfer Error: An error on the PCI bus that occurs in a transfer during a PIO write operation is not detected.
Page 992: Figure 22.4 Local Address Space Accessing Method
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group case of memory write, the internal control allows only the writing of valid byte lane data to the local bus. Only the linear mode is supported for addressing for burst transfers, and the 2 least significant bits of the PCI address are regarded as B'00.
Page 993 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) The PCICONF5 indicates the starting address of the memory space used by the PCI device. The PCILAR0 specifies the starting address of the local address space 0. The PCILSR0 expresses the size of the memory used by the PCI device.
Page 994: Dma Transfers
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group Note: * In version 2.1 of the PCI specifications the I/O space for PCI devices is defined as being no more than 256 bytes. As a result, when the SH7751 is used in a PCI non-host device, for example on an add-in card, it may be identified as an unusable device during device configuration because it requires an I/O space larger than 256 bytes.
Page 995 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) In DMA transfers, all transferred data is handled in long word units, so the number of transfer bytes and the low 2 bits of the transfer initial address are ignored and B'0000 is always output for BE[3:0].
Page 996: Figure 22.5 Example Of Dma Transfer Control Register Settings
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group 0: Fixed priority PCIDMABT Arbitration mode 1: Pseudo round-robin External memory space H'0000 0000 Area 0: H'00000000 to H'0000 0004 H'03FFFFFF Area 1: H'04000000 to 31 28 H'07FFFFFF Local address PCIDLA...
Page 997 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) DMA Transfer End: The following describes the status on termination of a DMA transfer. • Normal termination DMA transfer ends after the set number of bytes has been transferred. In the case of normal...
Page 998: Figure 22.6 Example Of Dma Transfer Flowchart
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group DMA transfer starts when 1 is set in the DMASTRT DMA transfer start bit of the PCIDCR register. DMA transfer (⇔ FIFO) The PCIDPA and PCIDLA registers are updated Transfer address update (increment/fixed) by the LAHOLD bit of the PCIDCR register.
Page 999 SH7751 Group, SH7751R Group Section 22 PCI Controller (PCIC) • Termination by software reset When the RSTCTL bit of the PCICR is asserted, the PCIC is reset and DMA transfers are forcibly terminated. Note, however, that when transfers are terminated by a software reset, the PCIDCR is also reset and the DMA transfer control registers are all cleared.
Page 1000: 22.3.10 Transfer Contention Within Pcic
Section 22 PCI Controller (PCIC) SH7751 Group, SH7751R Group On the other hand, it checks if transfer data exists in the respective FIFOs and reads that data from the data transfer FIFO in which there is data and which has the highest priority, and outputs that data to the PCI bus.

This manual is also suitable for:

Sh7751r group