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Manuals and User Guides for Renesas SH7751R Group. We have
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Renesas SH7751R Group manual available for free PDF download: User Manual
Renesas SH7751R Group User Manual (1186 pages)
Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family / SH7750 Series
Brand:
Renesas
| Category:
Computer Hardware
| Size: 6.92 MB
Table of Contents
Table of Contents
13
Bus Timing
9
Table of Contents
47
Section 1 Overview
55
SH7751/SH7751R Group Features
55
Section 1 Overview
56
Table 1.1 SH7751/SH7751R Group Features
56
Block Diagram
63
Figure 1.1 Block Diagram of SH7751/SH7751R Group Functions
63
Pin Arrangement
64
Figure 1.2 Pin Arrangement (256-Pin QFP)
64
Figure 1.3 Pin Arrangement (256-Pin BGA)
65
Figure 1.4 Pin Arrangement (292-Pin BGA)
66
Pin Functions
67
Pin Functions (256-Pin QFP)
67
Table 1.2 Pin Functions
67
Pin Functions (256-Pin BGA)
78
Table 1.3 Pin Functions
78
Pin Functions (292-Pin BGA)
89
Table 1.4 Pin Functions
89
Section 2 Programming Model
101
Data Formats
101
Figure 2.1 Data Formats
101
Register Configuration
102
Privileged Mode and Banks
102
Figure 2.2 CPU Register Configuration in each Processor Mode
104
General Registers
105
Figure 2.3 General Registers
106
Floating-Point Registers
107
Figure 2.4 Floating-Point Registers
108
Control Registers
109
System Registers
110
Memory-Mapped Registers
112
Data Format in Registers
113
Data Formats in Memory
113
Processor States
114
Figure 2.5 Data Formats in Memory
114
Figure 2.6 Processor State Transitions
115
Processor Modes
116
Section 3 Memory Management Unit (MMU)
117
Overview
117
Features
117
Role of the MMU
117
Figure 3.1 Role of the MMU
119
Register Configuration
120
Caution
120
Table 3.1 MMU Registers
120
Register Descriptions
121
Figure 3.2 MMU-Related Registers
121
Address Space
125
Physical Address Space
125
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
125
Figure 3.4 P4 Area
126
External Memory Space
128
Figure 3.5 External Memory Space
128
Virtual Address Space
129
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
129
On-Chip RAM Space
130
Address Translation
130
Single Virtual Memory Mode and Multiple Virtual Memory Mode
131
Address Space Identifier (ASID)
131
TLB Functions
132
Unified TLB (UTLB) Configuration
132
Figure 3.7 UTLB Configuration
132
Figure 3.8 Relationship between Page Size and Address Format
133
Instruction TLB (ITLB) Configuration
136
Address Translation Method
136
Figure 3.9 ITLB Configuration
136
Figure 3.10 Flowchart of Memory Access Using UTLB
137
Figure 3.11 Flowchart of Memory Access Using ITLB
138
MMU Functions
139
MMU Hardware Management
139
MMU Software Management
139
MMU Instruction (LDTLB)
139
Hardware ITLB Miss Handling
140
Figure 3.12 Operation of LDTLB Instruction
140
Avoiding Synonym Problems
141
MMU Exceptions
142
Instruction TLB Multiple Hit Exception
142
Instruction TLB Miss Exception
142
Instruction TLB Protection Violation Exception
143
Data TLB Multiple Hit Exception
144
Data TLB Miss Exception
145
Data TLB Protection Violation Exception
146
Initial Page Write Exception
147
Memory-Mapped TLB Configuration
148
ITLB Address Array
148
ITLB Data Array 1
149
Figure 3.13 Memory-Mapped ITLB Address Array
149
ITLB Data Array 2
150
Figure 3.14 Memory-Mapped ITLB Data Array 1
150
UTLB Address Array
151
Figure 3.15 Memory-Mapped ITLB Data Array 2
151
UTLB Data Array 1
152
Figure 3.16 Memory-Mapped UTLB Address Array
152
UTLB Data Array 2
153
Figure 3.17 Memory-Mapped UTLB Data Array 1
153
Usage Notes
154
Figure 3.18 Memory-Mapped UTLB Data Array 2
154
Section 4 Caches
155
Overview
155
Features
155
Register Configuration
156
Table 4.2 Cache Features (SH7751R)
156
Table 4.3 Store Queue Features
156
Table 4.4 Cache Control Registers
156
Register Descriptions
157
Figure 4.1 Cache and Store Queue Control Registers (CCR)
157
Operand Cache (OC)
159
Configuration
159
Figure 4.2 Configuration of Operand Cache (SH7751)
160
Figure 4.3 Configuration of Operand Cache (SH7751R)
161
Read Operation
162
Write Operation
163
Write-Back Buffer
165
Write-Through Buffer
165
RAM Mode
165
Figure 4.4 Configuration of Write-Back Buffer
165
Figure 4.5 Configuration of Write-Through Buffer
165
OC Index Mode
167
Coherency between Cache and External Memory
167
Prefetch Operation
167
Notes on Using OC RAM Mode (SH7751R Only) When in Cache Enhanced Mode
168
Instruction Cache (IC)
170
Configuration
170
Figure 4.6 Configuration of Instruction Cache (SH7751)
171
Figure 4.7 Configuration of Instruction Cache (SH7751R)
172
Read Operation
173
IC Index Mode
174
Memory-Mapped Cache Configuration (SH7751)
174
IC Address Array
174
Figure 4.8 Memory-Mapped IC Address Array
175
IC Data Array
176
Figure 4.9 Memory-Mapped IC Data Array
176
OC Address Array
177
OC Data Array
178
Figure 4.10 Memory-Mapped OC Address Array
178
Memory-Mapped Cache Configuration (SH7751R)
179
IC Address Array
179
Figure 4.11 Memory-Mapped OC Data Array
179
Figure 4.12 Memory-Mapped IC Address Array
180
IC Data Array
181
Figure 4.13 Memory-Mapped IC Data Array
181
OC Address Array
182
OC Data Array
183
Figure 4.14 Memory-Mapped OC Address Array
183
Summary of Memory-Mapped OC Addresses
184
Figure 4.15 Memory-Mapped OC Data Array
184
Store Queues
185
SQ Configuration
185
SQ Writes
185
Figure 4.16 Store Queue Configuration
185
Transfer to External Memory
186
Determination of SQ Access Exception
187
SQ Read (SH7751R Only)
187
SQ Usage Notes (SH7751 Only)
188
Section 5 Exceptions
191
Overview
191
Features
191
Register Configuration
191
Table 5.1 Exception-Related Registers
191
Table 5.2 Exceptions
191
Register Descriptions
192
Figure 5.1 Register Bit Configurations
192
Exception Handling Functions
193
Exception Handling Flow
193
Exception Handling Vector Addresses
193
Exception Types and Priorities
194
Exception Flow
197
Figure 5.2 Instruction Execution and Exception Handling
197
Exception Source Acceptance
198
Figure 5.3 Example of General Exception Acceptance Order
199
Exception Requests and BL Bit
200
Return from Exception Handling
200
Description of Exceptions
200
Resets
201
Table 5.3 Types of Reset
202
General Exceptions
206
Interrupts
220
Priority Order with Multiple Exceptions
223
Usage Notes
224
Restrictions
225
Section 6 Floating-Point Unit
227
Overview
227
Data Formats
227
Floating-Point Format
227
Figure 6.1 Format of Single-Precision Floating-Point Number
227
Figure 6.2 Format of Double-Precision Floating-Point Number
228
Table 6.1 Floating-Point Number Formats and Parameters
228
Non-Numbers (Nan)
229
Table 6.2 Floating-Point Ranges
229
Denormalized Numbers
230
Figure 6.3 Single-Precision Nan Bit Pattern
230
Registers
231
Floating-Point Registers
231
Figure 6.4 Floating-Point Registers
232
Floating-Point Status/Control Register (FPSCR)
233
Floating-Point Communication Register (FPUL)
234
Rounding
235
Floating-Point Exceptions
235
Graphics Support Functions
237
Geometric Operation Instructions
237
Pair Single-Precision Data Transfer
238
Usage Notes
239
Rounding Mode and Underflow Flag
239
Setting of Overflow Flag by FIPR or FTRV Instruction
240
Sign of Operation Result When Using FIPR or FTRV Instruction
241
Notes on Double-Precision FADD and FSUB Instructions
241
Section 7 Instruction Set
243
Execution Environment
243
Addressing Modes
245
Instruction Set
249
Table 7.2 Notation Used in Instruction List
249
Table 7.3 Fixed-Point Transfer Instructions
250
Table 7.4 Arithmetic Operation Instructions
252
Table 7.5 Logic Operation Instructions
254
Table 7.6 Shift Instructions
255
Table 7.7 Branch Instructions
256
Table 7.8 System Control Instructions
257
Table 7.9 Floating-Point Single-Precision Instructions
259
Table 7.10 Floating-Point Double-Precision Instructions
260
Table 7.11 Floating-Point Control Instructions
260
Usage Notes
261
Notes on TRAPA Instruction, SLEEP Instruction, and Undefined Instruction (H'FFFD)
261
Table 7.12 Floating-Point Graphics Acceleration Instructions
261
Section 8 Pipelining
265
Pipelines
265
Figure 8.1 Basic Pipelines
266
Figure 8.2 Instruction Execution Patterns
267
Parallel-Executability
272
Table 8.1 Instruction Groups
272
Execution Cycles and Pipeline Stalling
276
Table 8.2 Parallel-Executability
276
Figure 8.3 Examples of Pipelined Execution
279
Table 8.3 Execution Cycles
283
Usage Notes
292
Section 9 Power-Down Modes
293
Overview
293
Types of Power-Down Modes
293
Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
294
Register Configuration
295
Pin Configuration
295
Table 9.2 Power-Down Mode Registers
295
Table 9.3 Power-Down Mode Pins
295
Register Descriptions
296
Standby Control Register (STBCR)
296
Peripheral Module Pin High Impedance Control
298
Peripheral Module Pin Pull-Up Control
298
Standby Control Register 2 (STBCR2)
299
Clock Stop Register 00 (CLKSTP00)
300
Clock Stop Clear Register 00 (CLKSTPCLR00)
301
Sleep Mode
302
Transition to Sleep Mode
302
Exit from Sleep Mode
302
Deep Sleep Mode
302
Transition to Deep Sleep Mode
302
Exit from Deep Sleep Mode
303
Pin Sleep Mode
303
Transition to Pin Sleep Mode
303
Exit from Pin Sleep Mode
303
Standby Mode
303
Transition to Standby Mode
303
Exit from Standby Mode
304
Table 9.4 State of Registers in Standby Mode
304
Clock Pause Function
305
Module Standby Function
305
Transition to Module Standby Function
305
Exit from Module Standby Function
306
Hardware Standby Mode
307
Transition to Hardware Standby Mode
307
Exit from Hardware Standby Mode
307
Usage Notes
308
STATUS Pin Change Timing
308
In Reset
309
Figure 9.1 STATUS Output in Power-On Reset
309
Figure 9.2 STATUS Output in Manual Reset
309
In Exit from Standby Mode
310
Figure 9.3 STATUS Output in Standby → Interrupt Sequence
310
Figure 9.4 STATUS Output in Standby → Power-On Reset Sequence
310
In Exit from Sleep Mode
311
Figure 9.5 STATUS Output in Standby → Manual Reset Sequence
311
Figure 9.6 STATUS Output in Sleep → Interrupt Sequence
311
Figure 9.7 STATUS Output in Sleep → Power-On Reset Sequence
312
Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence
313
In Exit from Deep Sleep Mode
314
Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence
314
Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence
314
Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence
315
Hardware Standby Mode Timing
316
Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation)
316
Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation)
317
Figure 9.14 Timing When Power Other than VDD-RTC Is off
317
Usage Notes
318
Note on Current Consumption
318
Figure 9.15 Timing When VDD-RTC Power Is off → on
318
Section 10 Clock Oscillation Circuits
321
Overview
321
Features
321
Overview of CPG
323
Block Diagram of CPG
323
Figure 10.1 (1) Block Diagram of CPG (SH7751)
323
Figure 10.1 (2) Block Diagram of CPG (SH7751R)
324
CPG Pin Configuration
326
CPG Register Configuration
326
Table 10.1 CPG Pins
326
Table 10.2 CPG Register
326
Clock Operating Modes
327
Table 10.3 (1) Clock Operating Modes (SH7751)
327
Table 10.3 (2) Clock Operating Modes (SH7751R)
327
Table 10.4 FRQCR Settings and Internal Clock Frequencies
328
CPG Register Description
329
Frequency Control Register (FRQCR)
329
Changing the Frequency
332
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off)
332
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)
332
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On)
333
Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off)
333
Changing CPU or Peripheral Module Clock Division Ratio
333
Output Clock Control
334
Overview of Watchdog Timer
334
Block Diagram
334
Figure 10.2 Block Diagram of WDT
334
Register Configuration
335
WDT Register Descriptions
335
Watchdog Timer Counter (WTCNT)
335
Table 10.5 WDT Registers
335
Watchdog Timer Control/Status Register (WTCSR)
336
Notes on Register Access
338
Figure 10.3 Writing to WTCNT and WTCSR
338
Using the WDT
339
Standby Clearing Procedure
339
Frequency Changing Procedure
339
Using Watchdog Timer Mode
340
Using Interval Timer Mode
340
Notes on Board Design
341
Figure 10.4 Points for Attention When Using Crystal Resonator
341
Figure 10.5 Points for Attention When Using PLL Oscillator Circuit
342
Usage Notes
343
Invalid Manual Reset Triggered by Watchdog Timer (SH7751 Only)
343
Section 11 Realtime Clock (RTC)
345
Overview
345
Features
345
Block Diagram
346
Figure 11.1 Block Diagram of RTC
346
Pin Configuration
347
Register Configuration
347
Table 11.1 RTC Pins
347
Table 11.2 RTC Registers
347
Register Descriptions
349
64 Hz Counter (R64CNT)
349
Second Counter (RSECCNT)
350
Minute Counter (RMINCNT)
350
Hour Counter (RHRCNT)
351
Day-Of-Week Counter (RWKCNT)
351
Day Counter (RDAYCNT)
352
Month Counter (RMONCNT)
352
Year Counter (RYRCNT)
353
Second Alarm Register (RSECAR)
354
Minute Alarm Register (RMINAR)
354
Hour Alarm Register (RHRAR)
355
Day-Of-Week Alarm Register (RWKAR)
355
Day Alarm Register (RDAYAR)
356
Month Alarm Register (RMONAR)
357
RTC Control Register 1 (RCR1)
357
RTC Control Register 2 (RCR2)
359
RTC Control Register (RCR3) and Year-Alarm Register (RYRAR) (SH7751R Only)
362
Operation
363
Time Setting Procedures
363
Figure 11.2 Examples of Time Setting Procedures
363
Time Reading Procedures
365
Figure 11.3 Examples of Time Reading Procedures
365
Alarm Function
366
Figure 11.4 Example of Use of Alarm Function
366
Interrupts
367
Usage Notes
367
Register Initialization
367
Carry Flag and Interrupt Flag in Standby Mode
367
Crystal Oscillation Circuit
367
Table 11.3 Crystal Oscillation Circuit Constants (Recommended Values)
367
Figure 11.5 Example of Crystal Oscillation Circuit Connection
368
Section 12 Timer Unit (TMU)
369
Overview
369
Features
369
Block Diagram
370
Pin Configuration
370
Figure 12.1 Block Diagram of TMU
370
Table 12.1 TMU Pins
370
Register Configuration
371
Table 12.2 TMU Registers
371
Register Descriptions
372
Timer Output Control Register (TOCR)
372
Timer Start Register (TSTR)
373
Timer Start Register 2 (TSTR2)
374
Timer Constant Registers (TCOR)
375
Timer Counters (TCNT)
375
Timer Control Registers (TCR)
376
Input Capture Register 2 (TCPR2)
380
Operation
381
Counter Operation
381
Figure 12.2 Example of Count Operation Setting Procedure
382
Figure 12.3 TCNT Auto-Reload Operation
383
Figure 12.4 Count Timing When Operating on Internal Clock
383
Input Capture Function
384
Figure 12.5 Count Timing When Operating on External Clock
384
Figure 12.6 Count Timing When Operating on On-Chip RTC Output Clock
384
Figure 12.7 Operation Timing When Using Input Capture Function
385
Interrupts
386
Usage Notes
386
Register Writes
386
Table 12.3 TMU Interrupt Sources
386
TCNT Register Reads
387
Resetting the RTC Frequency Divider
387
External Clock Frequency
387
Section 13 Bus State Controller (BSC)
389
Overview
389
Features
389
Block Diagram
391
Figure 13.1 Block Diagram of BSC
391
Pin Configuration
392
Table 13.1 BSC Pins
392
Register Configuration
394
Table 13.2 BSC Registers
394
Overview of Areas
395
Figure 13.2 Correspondence between Virtual Address Space and External Memory Space
395
Table 13.3 External Memory Space Map
396
Figure 13.3 External Memory Space Allocation
397
PCMCIA Support
398
Table 13.4 PCMCIA Interface Features
398
Table 13.5 PCMCIA Support Interfaces
399
Register Descriptions
402
Bus Control Register 1 (BCR1)
402
Bus Control Register 2 (BCR2)
411
Bus Control Register 3 (BCR3) (SH7751R Only)
413
Bus Control Register 4 (BCR4) (SH7751R Only)
415
Figure 13.4 Example of RDY Sampling Timing at Which BCR4 Is Set
416
Wait Control Register 1 (WCR1)
417
Table 13.6 Idle Insertion between Accesses
419
Wait Control Register 2 (WCR2)
420
Table 13.7 When MPX Interface Is Set (Areas 0 to 6)
427
Wait Control Register 3 (WCR3)
428
Memory Control Register (MCR)
430
PCMCIA Control Register (PCR)
437
Synchronous DRAM Mode Register (SDMR)
440
Refresh Timer Control/Status Register (RTCSR)
442
Refresh Timer Counter (RTCNT)
444
Refresh Time Constant Register (RTCOR)
445
Refresh Count Register (RFCR)
446
13.2.15 Notes on Accessing Refresh Control Registers
446
Operation
447
Endian/Access Size and Data Alignment
447
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR
447
Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment
448
Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment
449
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment
450
Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment
451
Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment
452
Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment
453
Areas
454
SRAM Interface
459
Figure 13.6 Basic Timing of SRAM Interface
460
Figure 13.7 Example of 32-Bit Data Width SRAM Connection
461
Figure 13.8 Example of 16-Bit Data Width SRAM Connection
462
Figure 13.9 Example of 8-Bit Data Width SRAM Connection
463
Figure 13.10 SRAM Interface Wait Timing (Software Wait Only)
464
Figure 13.11 SRAM Interface Wait State Timing (Wait State Insertion by RDY Signal)
465
Figure 13.12 SRAM Interface Read Strobe Negate Timing (Ans = 1, Anw = 4, and Anh = 2)
466
DRAM Interface
467
Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3)
467
Table 13.14 Relationship between AMXEXT and AMX2-0 Bits and Address Multiplexing
468
Figure 13.14 Basic DRAM Access Timing
469
Figure 13.15 DRAM Wait State Timing
470
Figure 13.16 DRAM Burst Access Timing
471
Figure 13.17 DRAM Bus Cycle (EDO Mode, RCD = 0, Anw = 0, TPC = 1)
472
Figure 13.18 Burst Access Timing in DRAM EDO Mode
473
Figure 13.19 (1) DRAM Burst Bus Cycle, RAS down Mode Start (Fast Page Mode, RCD = 0, Anw = 0)
474
Figure 13.19 (2) DRAM Burst Bus Cycle, RAS down Mode Continuation (Fast Page Mode, RCD = 0, Anw = 0)
475
Figure 13.19 (3) DRAM Burst Bus Cycle, RAS down Mode Start (EDO Mode, RCD = 0, Anw = 0)
476
Figure 13.19 (4) DRAM Burst Bus Cycle, RAS down Mode Continuation (EDO Mode, RCD = 0, Anw = 0)
477
Figure 13.20 CAS-Before-RAS Refresh Operation
478
Figure 13.21 DRAM CAS-Before-RAS Refresh Cycle Timing (tras = 0, TRC = 1)
479
Figure 13.22 DRAM Self-Refresh Cycle Timing
480
Synchronous DRAM Interface
481
Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)
482
Table 13.15 Example of Correspondence between LSI and Synchronous DRAM Address Pins (32-Bit Bus Width, AMX2-AMX0 = 000, AMXEXT = 0)
483
Figure 13.24 Basic Timing for Synchronous DRAM Burst Read
485
Figure 13.25 Basic Timing for Synchronous DRAM Single Read
487
Figure 13.26 Basic Timing for Synchronous DRAM Burst Write
488
Figure 13.27 Basic Timing for Synchronous DRAM Single Write
490
Figure 13.28 Burst Read Timing
492
Figure 13.29 Burst Read Timing (RAS Down, same Row Address)
493
Figure 13.30 Burst Read Timing (RAS Down, Different Row Addresses)
494
Figure 13.31 Burst Write Timing
495
Figure 13.32 Burst Write Timing (same Row Address)
496
Figure 13.33 Burst Write Timing (Different Row Addresses)
497
Table 13.16 Cycles in Which Pipelined Access Can be Used
499
Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding
500
Figure 13.35 Auto-Refresh Operation
502
Figure 13.36 Synchronous DRAM Auto-Refresh Timing
502
Figure 13.37 Synchronous DRAM Self-Refresh Timing
504
Figure 13.38 (1) Synchronous DRAM Mode Write Timing (PALL)
506
Figure 13.38 (2) Synchronous DRAM Mode Write Timing (Mode Register Setting)
507
Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8)
509
Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM
510
Burst ROM Interface
511
Figure 13.41 Burst ROM Basic Access Timing
512
Figure 13.42 Burst ROM Wait Access Timing
513
PCMCIA Interface
514
Figure 13.43 Burst ROM Wait Access Timing
514
Table 13.17 Relationship between Address and CE When Using PCMCIA Interface
516
Figure 13.44 Example of PCMCIA Interface
518
Figure 13.45 Basic Timing for PCMCIA Memory Card Interface
519
Figure 13.46 Wait Timing for PCMCIA Memory Card Interface
520
Figure 13.47 PCMCIA Space Allocation
521
Figure 13.48 Basic Timing for PCMCIA I/O Card Interface
522
Figure 13.49 Wait Timing for PCMCIA I/O Card Interface
523
Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
524
MPX Interface
525
Figure 13.51 Example of 32-Bit Data Width MPX Connection
526
Figure 13.52 MPX Interface Timing 1 (Single Read Cycle, Anw = 0, no External Wait)
527
Figure 13.53 MPX Interface Timing 2 (Single Read, Anw = 0, One External Wait Inserted)
528
Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, Anw = 0, no External Wait)
529
Figure 13.55 MPX Interface Timing 4 (Single Write, Anw = 1, One External Wait Inserted)
530
Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, Anw = 0, no External Wait)
531
Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, Anw = 0, External Wait Control)
532
Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, Anw = 0, no External Wait)
533
Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, Anw = 1, External Wait Control)
534
Figure 13.60 MPX Interface Timing 9 (Burst Read Cycle, Anw = 0, no External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)
535
Figure 13.61 MPX Interface Timing 10 (Burst Read Cycle, Anw = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)
536
Figure 13.62 MPX Interface Timing 11 (Burst Write Cycle, Anw = 0, no External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)
537
Figure 13.63 MPX Interface Timing 12 (Burst Write Cycle, Anw = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)
538
Byte Control SRAM Interface
539
Figure 13.64 Example of 32-Bit Data Width Byte Control SRAM
539
Figure 13.65 Byte Control SRAM Basic Read Cycle (no Wait)
540
Figure 13.66 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)
541
Figure 13.67 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait)
542
13.3.10 Waits between Access Cycles
543
13.3.11 Bus Arbitration
544
Figure 13.68 Waits between Access Cycles
544
Figure 13.69 Arbitration Sequence
546
13.3.12 Master Mode
547
13.3.13 Slave Mode
548
13.3.14 Cooperation between Master and Slave
549
13.3.15 Notes on Usage
549
Section 14 Direct Memory Access Controller (DMAC)
551
Overview
551
Features
551
Block Diagram (SH7751)
554
Figure 14.1 Block Diagram of DMAC
554
Pin Configuration (SH7751)
555
Table 14.1 DMAC Pins
555
Register Configuration (SH7751)
556
Table 14.2 DMAC Pins in DDT Mode
556
Table 14.3 DMAC Registers
557
Register Descriptions
558
DMA Source Address Registers 0-3 (SAR0-SAR3)
558
DMA Destination Address Registers 0-3 (DAR0-DAR3)
559
DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3)
560
DMA Channel Control Registers 0-3 (CHCR0-CHCR3)
561
DMA Operation Register (DMAOR)
569
Operation
571
DMA Transfer Procedure
571
Figure 14.2 DMAC Transfer Flowchart
573
DMA Transfer Requests
574
Table 14.4 Selecting External Request Mode with RS Bits
575
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits
576
Channel Priorities
577
Figure 14.3 Round Robin Mode
578
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode
579
Types of DMA Transfer
580
Table 14.6 Supported DMA Transfers
580
Figure 14.5 Data Flow in Single Address Mode
581
Figure 14.6 DMA Transfer Timing in Single Address Mode
582
Figure 14.7 Operation in Dual Address Mode
583
Figure 14.8 Example of Transfer Timing in Dual Address Mode
584
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode
585
Figure 14.10 Example of DMA Transfer in Burst Mode
585
Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode
586
Table 14.8 External Request Transfer Sources and Destinations in Normal DMA Mode
587
Table 14.9 External Request Transfer Sources and Destinations in DDT Mode
588
Number of Bus Cycle States and DREQ Pin Sampling Timing
589
Figure 14.11 Bus Handling with Two DMAC Channels Operating
589
Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
592
Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
593
Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/Dreq
594
Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/Dreq
595
Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → External Bus
596
Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI
597
Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
598
Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
599
Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/Dreq
600
Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/Dreq
601
Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/Dreq
602
Ending DMA Transfer
603
Examples of Use
606
Examples of Transfer between External Memory and an External Device with DACK
606
Table 14.10 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings
606
On-Demand Data Transfer Mode (DDT Mode)
607
Operation
607
Figure 14.23 On-Demand Transfer Mode Block Diagram
607
Pins in DDT Mode
609
Figure 14.24 System Configuration in On-Demand Data Transfer Mode
609
Figure 14.25 Data Transfer Request Format
610
Table 14.11 Usable SZ, ID, and MD Combination in DDT Mode
611
Transfer Request Acceptance on each Channel
612
Figure 14.27 Single Address Mode/External Device → Synchronous DRAM Longword
614
Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer
615
Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
616
Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte
616
Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit
617
Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit
618
Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer)
619
Figure 14.34 Handshake Protocol Without Use of Data Bus (Channel 0 On-Demand Data Transfer)
620
Figure 14.35 Read from Synchronous DRAM Precharge Bank
621
Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss)
621
Figure 14.37 Read from Synchronous DRAM (Row Hit)
622
Figure 14.38 Write to Synchronous DRAM Precharge Bank
622
Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss)
623
Figure 14.40 Write to Synchronous DRAM (Row Hit)
623
Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
624
Figure 14.42 DDT Mode Setting
625
Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/External Device → External Bus Data Transfer
625
Figure 14.44 Single Address Mode/Burst Mode/Level Detection/External Bus → External Device Data Transfer
626
Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus → External Device Data Transfer
626
Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer
627
Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/Dma Transfer Request to Channels 1-3 Using Data Bus
628
Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/External Bus → External Device Data Transfer/Direct Data Transfer Request to Channel 2 Without Using Data Bus
629
Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data
632
Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data
633
Notes on Use of DDT Module
634
Configuration of the DMAC (SH7751R)
637
Block Diagram of the DMAC
637
Figure 14.53 Block Diagram of the DMAC
637
Pin Configuration (SH7751R)
638
Table 14.12 DMAC Pins
638
Register Configuration (SH7751R)
639
Table 14.13 DMAC Pins in DDT Mode
639
Table 14.14 Register Configuration
640
Register Descriptions (SH7751R)
642
DMA Source Address Registers 0−7 (SAR0−SAR7)
642
DMA Destination Address Registers 0−7 (DAR0−DAR7)
642
DMA Transfer Count Registers 0−7 (DMATCR0−DMATCR7)
643
DMA Channel Control Registers 0−7 (CHCR0−CHCR7)
643
DMA Operation Register (DMAOR)
647
Figure 14.54 DTR Format (Transfer Request Format) (SH7751R)
648
Table 14.15 Channel Selection by DTR Format (DMAOR.DBL = 1)
648
Operation (SH7751R)
649
Channel Specification for a Normal DMA Transfer
649
Channel Specification for DDT-Mode DMA Transfer
649
Transfer Channel Notification in DDT Mode
650
Table 14.16 Notification of Transfer Channel in Eight-Channel DDT Mode
650
Table 14.17 Function of BAVL
650
Clearing Request Queues by DTR Format
651
Interrupt-Request Codes
651
Table 14.18 DTR Format for Clearing Request Queues
651
Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
652
Table 14.19 DMAC Interrupt-Request Codes
652
Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus → External Device
653
Usage Notes
654
Section 15 Serial Communication Interface (SCI)
657
Overview
657
Features
657
Block Diagram
659
Figure 15.1 Block Diagram of SCI
659
Pin Configuration
660
Register Configuration
660
Table 15.1 SCI Pins
660
Table 15.2 SCI Registers
660
Register Descriptions
661
Receive Shift Register (SCRSR1)
661
Receive Data Register (SCRDR1)
661
Transmit Shift Register (SCTSR1)
662
Transmit Data Register (SCTDR1)
662
Serial Mode Register (SCSMR1)
663
Serial Control Register (SCSCR1)
665
Serial Status Register (SCSSR1)
669
Serial Port Register (SCSPTR1)
673
Figure 15.2 SCK Pin
675
Figure 15.3 Txd Pin
676
Figure 15.4 Rxd Pin
676
Bit Rate Register (SCBRR1)
677
Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode
679
Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode
682
Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode)
683
Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
684
Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)
684
Operation
685
Overview
685
Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection
686
Operation in Asynchronous Mode
687
Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection
687
Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
688
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
689
Figure 15.6 Relation between Output Clock and Transfer Data Phase
690
Figure 15.7 Sample SCI Initialization Flowchart
691
Figure 15.8 Sample Serial Transmission Flowchart
692
Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
694
Figure 15.10 Sample Serial Reception Flowchart (1)
695
Table 15.11 Receive Error Conditions
697
Multiprocessor Communication Function
698
Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit)
698
Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
699
Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart
701
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
703
Figure 15.15 Sample Flowchart of Multiprocessor Serial Reception with Interrupt
705
Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (1)
706
Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (2)
707
Figure 15.17 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
708
Operation in Synchronous Mode
709
Figure 15.18 Data Format in Synchronous Communication
709
Figure 15.19 Sample SCI Initialization Flowchart
711
Figure 15.20 Sample Serial Transmission Flowchart
712
Figure 15.21 Example of SCI Transmit Operation
714
Figure 15.22 Sample Serial Reception Flowchart (1)
715
Figure 15.23 Example of SCI Receive Operation
717
Figure 15.24 Sample Flowchart for Serial Data Transmission and Reception
718
SCI Interrupt Sources and DMAC
719
Usage Notes
720
Table 15.12 SCI Interrupt Sources
720
Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data
721
Figure 15.25 Receive Data Sampling Timing in Asynchronous Mode
722
Figure 15.26 Example of Synchronous Transmission by DMAC
723
Section 16 Serial Communication Interface with FIFO (SCIF)
725
Overview
725
Features
725
Block Diagram
727
Figure 16.1 Block Diagram of SCIF
727
Pin Configuration
728
Register Configuration
728
Table 16.1 SCIF Pins
728
Table 16.2 SCIF Registers
728
Register Descriptions
729
Receive Shift Register (SCRSR2)
729
Receive FIFO Data Register (SCFRDR2)
729
Transmit Shift Register (SCTSR2)
730
Transmit FIFO Data Register (SCFTDR2)
730
Serial Mode Register (SCSMR2)
731
Serial Control Register (SCSCR2)
733
Serial Status Register (SCFSR2)
736
Bit Rate Register (SCBRR2)
742
FIFO Control Register (SCFCR2)
743
FIFO Data Count Register (SCFDR2)
746
Serial Port Register (SCSPTR2)
747
Figure 16.2 MD8/RTS2 Pin
750
Figure 16.3 MD7/CTS2 Pin
751
Figure 16.4 Md1/Txd2 Pin
752
Figure 16.5 Md2/Rxd2 Pin
752
Figure 16.6 MD0/SCK2 Pin
753
Line Status Register (SCLSR2)
754
Operation
755
Overview
755
Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection
756
Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection
756
Serial Operation
757
Table 16.5 Serial Transfer Formats
757
Figure 16.7 Sample SCIF Initialization Flowchart
759
Figure 16.8 Sample Serial Transmission Flowchart
760
Figure 16.9 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit)
762
Figure 16.10 Example of Operation Using Modem Control (CTS2)
762
Figure 16.11 Sample Serial Reception Flowchart (1)
763
Figure 16.11 Sample Serial Reception Flowchart (2)
764
Figure 16.12 Example of SCIF Receive Operation
766
Figure 16.13 Example of Operation Using Modem Control (RTS2)
766
SCIF Interrupt Sources and the DMAC
767
Usage Notes
768
Table 16.6 SCIF Interrupt Sources
768
Figure 16.14 Receive Data Sampling Timing in Asynchronous Mode
770
Section 17 Smart Card Interface
773
Overview
773
Features
773
Block Diagram
774
Figure 17.1 Block Diagram of Smart Card Interface
774
Pin Configuration
775
Register Configuration
775
Table 17.1 Smart Card Interface Pins
775
Table 17.2 Smart Card Interface Registers
775
Register Descriptions
776
Smart Card Mode Register (SCSCMR1)
776
Serial Mode Register (SCSMR1)
777
Serial Control Register (SCSCR1)
778
Serial Status Register (SCSSR1)
779
Operation
780
Overview
780
Pin Connections
781
Figure 17.2 Schematic Diagram of Smart Card Interface Pin Connections
781
Data Format
782
Figure 17.3 Smart Card Interface Data Format
782
Register Settings
783
Table 17.3 Smart Card Interface Register Settings
783
Figure 17.4 TEND Generation Timing
784
Clock
785
Figure 17.5 Sample Start Character Waveforms
785
Table 17.4 Values of N and Corresponding CKS1 and CKS0 Settings
786
Table 17.5 Examples of Bit Rate B (Bits/S) for Various SCBRR1 Settings (When N = 0)
786
Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (Bits/S) (When N = 0)
786
Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
787
Table 17.8 Register Settings and SCK Pin State
787
Data Transfer Operations
788
Figure 17.6 Difference in Clock Output According to GM Bit Setting
788
Figure 17.7 Sample Initialization Flowchart
789
Figure 17.8 Sample Transmission Processing Flowchart
791
Figure 17.9 Sample Reception Processing Flowchart
793
Table 17.9 Smart Card Mode Operating States and Interrupt Sources
794
Usage Notes
795
Figure 17.10 Receive Data Sampling Timing in Smart Card Mode
795
Figure 17.11 Retransfer Operation in SCI Receive Mode
797
Figure 17.12 Retransfer Operation in SCI Transmit Mode
797
Figure 17.13 Procedure for Stopping and Restarting the Clock
798
Section 18 I/O Ports
801
Overview
801
Features
801
Block Diagrams
802
Figure 18.1 16-Bit Port a
802
Figure 18.2 16-Bit Port B
803
Figure 18.3 SCK Pin
804
Figure 18.4 Txd Pin
805
Figure 18.5 Rxd Pin
805
Figure 18.6 Md1/Txd2 Pin
806
Figure 18.7 Md2/Rxd2 Pin
806
Figure 18.8 MD0/SCK2 Pin
807
Figure 18.9 MD7/CTS2 Pin
808
Pin Configuration
809
Figure 18.10 MD8/RTS2 Pin
809
Table 18.1 32-Bit General-Purpose I/O Port Pins
809
Table 18.2 SCI I/O Port Pins
811
Table 18.3 SCIF I/O Port Pins
811
Register Configuration
812
Table 18.4 I/O Port Registers
812
Register Descriptions
813
Port Control Register a (PCTRA)
813
Port Data Register a (PDTRA)
814
Port Control Register B (PCTRB)
815
Port Data Register B (PDTRB)
816
GPIO Interrupt Control Register (GPIOIC)
817
Serial Port Register (SCSPTR1)
818
Serial Port Register (SCSPTR2)
820
Section 19 Interrupt Controller (INTC)
823
Overview
823
Features
823
Block Diagram
823
Figure 19.1 Block Diagram of INTC
824
Pin Configuration
825
Register Configuration
825
Table 19.1 INTC Pins
825
Table 19.2 INTC Registers
825
Interrupt Sources
826
NMI Interrupt
826
IRL Interrupts
827
Figure 19.2 Example of IRL Interrupt Connection
827
Table 19.3 IRL3-IRL0 Pins and Interrupt Levels
828
On-Chip Peripheral Module Interrupts
829
Interrupt Exception Handling and Priority
830
Table 19.4 Interrupt Exception Handling Sources and Priority Order
831
Register Descriptions
834
Interrupt Priority Registers a to D (IPRA-IPRD)
834
Interrupt Control Register (ICR)
835
Table 19.5 Interrupt Request Sources and IPRA-IPRD Registers
835
Interrupt Priority Level Settting Register 00 (INTPRI00)
837
Table 19.6 Interrupt Request Sources and INTPRI00 Register
837
Interrupt Factor Register 00 (INTREQ00)
838
Interrupt Mask Register 00 (INTMSK00)
838
Interrupt Mask Clear Register 00 (INTMSKCLR00)
839
INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation
840
Table 19.7 Bit Allocation
840
INTC Operation
841
Interrupt Operation Sequence
841
Figure 19.3 Interrupt Operation Flowchart
842
Multiple Interrupts
843
Interrupt Masking with MAI Bit
843
Interrupt Response Time
844
Table 19.8 Interrupt Response Time
844
Usage Notes
845
NMI Interrupts (SH7751 Only)
845
Section 20 User Break Controller (UBC)
849
Overview
849
Features
849
Block Diagram
850
Figure 20.1 Block Diagram of User Break Controller
850
Table 20.1 UBC Registers
851
Register Descriptions
852
Access to UBC Registers
852
Break Address Register a (BARA)
853
Break ASID Register a (BASRA)
854
Break Address Mask Register a (BAMRA)
854
Break Bus Cycle Register a (BBRA)
855
Break Address Register B (BARB)
857
Break ASID Register B (BASRB)
857
Break Address Mask Register B (BAMRB)
857
Break Data Register B (BDRB)
857
Break Data Mask Register B (BDMRB)
858
Break Bus Cycle Register B (BBRB)
859
Break Control Register (BRCR)
859
Operation
862
Explanation of Terms Relating to Accesses
862
Explanation of Terms Relating to Instruction Intervals
862
User Break Operation Sequence
863
Instruction Access Cycle Break
864
Operand Access Cycle Break
865
Condition Match Flag Setting
866
Program Counter (PC) Value Saved
866
Contiguous a and B Settings for Sequential Conditions
867
Usage Notes
868
User Break Debug Support Function
870
Figure 20.2 User Break Debug Support Function Flowchart
871
Examples of Use
872
User Break Controller Stop Function
874
Transition to User Break Controller Stopped State
874
Cancelling the User Break Controller Stopped State
874
Examples of Stopping and Restarting the User Break Controller
875
Section 21 High-Performance User Debug Interface (H-UDI)
877
Overview
877
Features
877
Block Diagram
877
Figure 21.1 Block Diagram of H-UDI Circuit
878
Pin Configuration
879
Table 21.1 H-UDI Pins
879
Register Configuration
880
Table 21.2 H-UDI Registers
880
Register Descriptions
881
Instruction Register (SDIR)
881
Data Register (SDDR)
882
Bypass Register (SDBPR)
882
Interrupt Factor Register (SDINT)
883
Boundary Scan Register (SDBSR)
883
Table 21.3 Structure of Boundary Scan Register
884
Operation
897
TAP Control
897
Figure 21.2 TAP Control State Transition Diagram
897
H-UDI Reset
898
H-UDI Interrupt
898
Figure 21.3 H-UDI Reset
898
Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS)
899
Usage Notes
899
Section 22 PCI Controller (PCIC)
901
Overview
901
Features
901
Block Diagram
902
Figure 22.1 PCIC Block Diagram
902
Pin Configuration
903
Table 22.1 Pin Configuration
903
Register Configuration
904
Table 22.2 List of PCI Configuration Registers
905
Table 22.3 PCI Configuration Register Configuration
906
Table 22.4 List of PCIC Local Registers
907
PCIC Register Descriptions
910
PCI Configuration Register 0 (PCICONF0)
910
PCI Configuration Register 1 (PCICONF1)
911
PCI Configuration Register 2 (PCICONF2)
917
Table 22.5 List of CLASS23 to 16 Base Class Codes (CLASS23 to 16)
918
PCI Configuration Register 3 (PCICONF3)
919
PCI Configuration Register 4 (PCICONF4)
921
PCI Configuration Register 5 (PCICONF5)
923
Table 22.6 Memory Space Base Address Register (BASE0)
924
PCI Configuration Register 6 (PCICONF6)
925
Table 22.7 Memory Space Base Address Register (BASE1)
926
PCI Configuration Register 7 (PCICONF7) to PCI Configuration Register 10
927
(Pciconf10)
927
PCI Configuration Register 11 (PCICONF11)
928
PCI Configuration Register 12 (PCICONF12)
929
PCI Configuration Register 13 (PCICONF13)
929
PCI Configuration Register 14 (PCICONF14)
930
PCI Configuration Register 15 (PCICONF15)
931
PCI Configuration Register 16 (PCICONF16)
933
PCI Configuration Register 17 (PCICONF17)
935
22.2.16 Reserved Area
937
PCI Control Register (PCICR)
938
PCI Local Space Register [1:0] (PCILSR [1:0])
942
PCI Local Address Register [1:0] (PCILAR [1:0])
944
PCI Interrupt Register (PCIINT)
946
PCI Interrupt Mask Register (PCIINTM)
949
PCI Address Data Register at Error (PCIALR)
951
PCI Command Data Register at Error (PCICLR)
952
PCI Arbiter Interrupt Register (PCIAINT)
954
PCI Arbiter Interrupt Mask Register (PCIAINTM)
956
PCI Error Bus Master Data Register (PCIBMLR)
957
PCI DMA Transfer Arbitration Register (PCIDMABT)
958
PCI DMA Transfer PCI Address Register [3:0] (PCIDPA [3:0])
959
PCI DMA Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0])
961
PCI DMA Transfer Counter Register [3:0] (PCIDTC [3:0])
962
PCI DMA Control Register [3:0] (PCIDCR [3:0])
964
PIO Address Register (PCIPAR)
967
Memory Space Base Register (PCIMBR)
969
I/O Space Base Register (PCIIOBR)
971
PCI Power Management Interrupt Register (PCIPINT)
972
PCI Power Management Interrupt Mask Register (PCIPINTM)
973
PCI Clock Control Register (PCICLKR)
974
22.2.38 PCIC-BSC Registers
975
Port Control Register (PCIPCTR)
977
Port Data Register (PCIPDTR)
980
PIO Data Register (PCIPDR)
981
Description of Operation
982
Operating Modes
982
Table 22.8 Operating Modes
982
PCI Commands
983
Table 22.9 PCI Command Support
983
PCIC Initialization
984
Local Register Access
985
Host Functions
985
PCI Bus Arbitration in Non-Host Mode
988
PIO Transfers
988
Figure 22.2 PIO Memory Space Access
990
Target Transfers
991
Figure 22.3 PIO I/O Space Access
991
Figure 22.4 Local Address Space Accessing Method
992
DMA Transfers
994
Figure 22.5 Example of DMA Transfer Control Register Settings
996
Figure 22.6 Example of DMA Transfer Flowchart
998
22.3.10 Transfer Contention Within PCIC
1000
22.3.11 PCI Bus Basic Interface
1001
Figure 22.7 Master Write Cycle in Host Mode (Single)
1002
Figure 22.8 Master Read Cycle in Host Mode (Single)
1003
Figure 22.9 Master Memory Write Cycle in Non-Host Mode (Burst)
1004
Figure 22.10 Master Memory Read Cycle in Non-Host Mode (Burst)
1005
Figure 22.11 Target Read Cycle in Non-Host Mode (Single)
1007
Figure 22.12 Target Write Cycle in Non-Host Mode (Single)
1008
Figure 22.13 Target Memory Read Cycle in Host Mode (Burst)
1009
Figure 22.14 Target Memory Write Cycle in Host Mode (Burst)
1010
Figure 22.15 Master Memory Write Cycle in Host Mode (Burst, with Stepping)
1011
Figure 22.16 Target Memory Read Cycle in Host Mode (Burst, with Stepping)
1012
Endians
1013
Internal Bus (Peripheral Bus) Interface for Peripheral Modules
1013
Figure 22.17 Endian Conversion Modes for Peripheral Bus
1013
Figure 22.18 Peripheral Bus ↔ PCI Bus Data Alignment
1014
Table 22.10 Access Size
1014
Endian Control for Local Bus
1015
Endian Control in DMA Transfers
1015
Figure 22.19 Endian Control for Local Bus
1015
Figure 22.20 Data Alignment at DMA Transfer
1016
Table 22.11 DMA Transfer Access Size and Endian Conversion Mode
1016
Endian Control in Target Transfers (Memory Read/Memory Write)
1017
Table 22.12 Target Transfer Access Size and Endian Conversion Mode
1017
Figure 22.21 (1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus)
1018
Figure 22.21 (2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus)
1019
Endian Control in Target Transfers (I/O Read/I/O Write)
1020
Endian Control in Target Transfers (Configuration Read/Configuration Write)
1020
Figure 22.22 Data Alignment at Target I/O Transfer (both Big Endian and Little Endian)
1020
Figure 22.23 Data Alignment at Target Configuration Transfer (both Big Endian and Little Endian)
1021
Resetting
1022
Interrupts
1023
Interrupts from PCIC to CPU
1023
Table 22.13 Interrupts
1023
Interrupts from External PCI Devices
1024
Inta
1025
Error Detection
1025
PCIC Clock
1025
Power Management
1026
Power Management Overview
1026
Stopping the Clock
1027
Table 22.14 Method of Stopping Clock Per Operating Mode
1028
Compatibility with Standby and Sleep
1030
Port Functions
1030
Version Management
1031
Usage Notes
1031
Notes on Arbiter Interrupt Usage (SH7751 Only)
1031
Figure 22.24 Target Bus Timeout Interrupt Generation Example 1
1032
Figure 22.25 Target Bus Timeout Interrupt Generation Example 2
1033
Figure 22.26 Master Bus Timeout Interrupt Generation Example 1
1033
Notes on I/O Read and I/O Write Commands (SH7751 Only)
1034
Notes on Configuration-Read and Configuration-Write Commands (SH7751 Only)
1034
Notes on Target Read/Write Cycle Timing (SH7751 Only)
1034
22.12.5 Notes on Parity Error Detection During Master Access
1034
Figure 22.27 Master Bus Timeout Interrupt Generation Example 2
1034
Section 23 Electrical Characteristics
1037
Absolute Maximum Ratings
1037
Table 23.1 Absolute Maximum Ratings
1037
DC Characteristics
1038
Table 23.2 DC Characteristics (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV)
1038
Table 23.3 DC Characteristics (HD6417751RF240 (V))
1040
Table 23.4 DC Characteristics (HD6417751RBP200 (V), HD6417751RBG200 (V)
1042
Table 23.5 DC Characteristics (HD6417751RF200 (V))
1044
Table 23.6 DC Characteristics (HD6417751BP167 (V))
1046
Table 23.7 DC Characteristics (HD6417751F167 (V))
1048
AC Characteristics
1050
Table 23.8 Permissible Output Currents
1050
Table 23.9 Clock Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV)
1050
Table 23.10 Clock Timing (HD6417751RF240 (V))
1050
Table 23.11 Clock Timing (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV*)
1051
Table 23.12 Clock Timing (HD6417751RF200 (V))
1051
Table 23.13 Clock Timing (HD6417751BP167 (V), HD6417751F167 (V))
1051
Clock and Control Signal Timing
1052
Table 23.14 Clock and Control Signal Timing (HD6417751RBP240 (V), HD6417751RBG240 (V), HD6417751RBA240HV)
1052
Table 23.15 Clock and Control Signal Timing (HD6417751RF240 (V))
1054
Table 23.16 Clock and Control Signal Timing (HD6417751RBP200 (V), HD6417751RBG200 (V), HD6417751RBA240HV
1056
Table 23.17 Clock and Control Signal Timing (HD6417751RF200 (V))
1058
Table 23.18 Clock and Control Signal Timing (HD6417751BP167 (V), HD6417751F167 (V))
1060
Figure 23.1 EXTAL Clock Input Timing
1061
Figure 23.2 (1) CKIO Clock Output Timing
1061
Figure 23.2 (2) CKIO Clock Output Timing
1061
Figure 23.3 Power-On Oscillation Settling Time
1062
Figure 23.4 Standby Return Oscillation Settling Time (Return by RESET or MRESET)
1062
Figure 23.5 Power-On Oscillation Settling Time
1063
Figure 23.6 Standby Return Oscillation Settling Time (Return by RESET or MRESET)
1063
Figure 23.7 Standby Return Oscillation Settling Time (Return by NMI)
1064
Figure 23.8 Standby Return Oscillation Settling Time (Return by IRL3-IRL0)
1064
Figure 23.9 PLL Synchronization Settling Time in Case of RESET, MRESET or
1065
Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt
1065
Control Signal Timing
1066
Table 23.19 Control Signal Timing
1066
Table 23.20 Control Signal Timing
1067
Figure 23.11 Control Signal Timing
1068
Figure 23.12 (1) Pin Drive Timing for Reset or Sleep Mode
1068
Figure 23.12 (2) Pin Drive Timing for Software Standby Mode
1069
Bus Timing
1070
Table 23.21 Bus Timing (1)
1070
Table 23.22 Bus Timing (2)
1072
Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (no Wait)
1074
Figure 23.14 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)
1075
Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)
1076
Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (no Wait, Address Setup/Hold Time Insertion, Ans = 1, Anh = 1)
1077
Figure 23.17 Burst ROM Bus Cycle (no Wait)
1078
Figure 23.18 Burst ROM Bus Cycle (1St Data: One Internal Wait + One External Wait; 2Nd/3Rd/4Th Data: One Internal Wait)
1079
Figure 23.19 Burst ROM Bus Cycle (no Wait, Address Setup/Hold Time Insertion, Ans = 1, Anh = 1)
1080
Figure 23.20 Burst ROM Bus Cycle (One Internal Wait + One External Wait)
1081
Figure 23.21 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011)
1082
Figure 23.22 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011)
1083
Figure 23.23 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD [1:0] = 01, CAS Latency = 3)
1084
Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001, CAS Latency = 3)
1085
Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (RASD = 1, CAS Latency = 3)
1086
Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)
1087
Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)
1088
Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RASD = 1, RCD [1:0] = 01, TRWL [2:0] = 010)
1089
Figure 23.29 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT
1090
Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL [2:0] = 010)
1091
Figure 23.31 Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001)
1092
Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (tras = 1, TRC [2:0] = 001)
1093
Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001)
1094
Figure 23.34 (A) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL)
1095
Figure 23.34 (B) Synchronous DRAM Bus Cycle: Mode Register Setting (SET)
1096
Figure 23.35 DRAM Bus Cycles (1) RCD [1:0] = 00, Anw [2:0]
1097
Figure 23.36 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, Anw [2:0] = 000, TRC [2:0] = 001)
1098
Figure 23.37 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, Anw [2:0] = 000, TPC [2:0] = 001)
1099
Figure 23.38 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, Anw [2:0] = 001, TPC [2:0] = 001)
1100
Figure 23.39 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, Anw [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width)
1101
Figure 23.40 DRAM Burst Bus Cycle: RAS down Mode State (EDO Mode, RCD [1:0] = 00, Anw [2:0] = 000)
1102
Figure 23.41 DRAM Burst Bus Cycle: RAS down Mode Continuation (EDO Mode, RCD [1:0] = 00, Anw [2:0] = 000)
1103
Figure 23.42 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 00, Anw [2:0] = 000, TPC [2:0] = 001)
1104
Figure 23.43 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, Anw [2:0] = 001, TPC [2:0] = 001)
1105
Figure 23.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, Anw [2:0] = 001, TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width)
1106
Figure 23.45 DRAM Burst Bus Cycle: RAS down Mode State (Fast Page Mode, RCD [1:0] = 00, Anw [2:0] = 000)
1107
Figure 23.46 DRAM Burst Bus Cycle: RAS down Mode Continuation (Fast Page Mode, RCD [1:0] = 00, Anw [2:0] = 000)
1108
Figure 23.47 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (tras [2:0] = 000, TRC [2:0] = 001)
1109
Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (tras [2:0] = 001, TRC [2:0] = 001)
1110
Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001)
1111
Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, no Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait
1112
Figure 23.51 PCMCIA I/O Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000, no Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External Wait
1113
Figure 23.52 PCMCIA I/O Bus Cycle (TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait, Bus Sizing)
1114
Figure 23.53 MPX Basic Bus Cycle: Read (1) 1St Data (One Internal Wait) (2) 1St Data (One Internal Wait + One External Wait)
1115
Figure 23.54 MPX Basic Bus Cycle: Write (1) 1St Data (no Wait) (2) 1St Data (One Internal Wait) (3) 1St Data (One Internal Wait + One External Wait)
1116
Figure 23.56 MPX Bus Cycle: Burst Write (1) no Internal Wait (2) 1St Data
1118
Figure 23.57 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (no Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait)
1119
Figure 23.58 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (no Wait, Address Setup/Hold Time Insertion, Ans [0] = 1, Anh [1:0] = 01)
1120
Peripheral Module Signal Timing
1121
Table 23.23 Peripheral Module Signal Timing (1)
1121
Table 23.24 Peripheral Module Signal Timing (2)
1124
Figure 23.59 TCLK Input Timing
1126
Figure 23.60 RTC Oscillation Settling Time at Power-On
1126
Figure 23.61 SCK Input Clock Timing
1126
Figure 23.62 SCI I/O Synchronous Mode Clock Timing
1127
Figure 23.63 I/O Port Input/Output Timing
1127
Figure 23.64 (A) DREQ/DRAK Timing
1127
Figure 23.64 (B) DBREQ/TR Input Timing and BAVL Output Timing
1128
Figure 23.65 TCK Input Timing
1128
Figure 23.66 RESET Hold Timing
1129
Figure 23.67 H-UDI Data Transfer Timing
1129
Figure 23.68 Pin Break Timing
1129
Figure 23.69 NMI Input Timing
1129
Table 23.25 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1)
1130
Table 23.26 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (2)
1131
Figure 23.70 PCI Clock Input Timing
1132
Figure 23.71 Output Signal Timing
1132
Figure 23.72 Output Signal Timing
1133
Table 23.27 PCIC Signal Timing (with PCIREQ/PCIGNT Port Settings in Non-Host Mode) (1)
1133
Table 23.28 PCIC Signal Timing (with PCIREQ/PCIGNT Port Settings in Non-Host Mode) (2)
1133
Figure 23.73 I/O Port Input/Output Timing
1134
AC Characteristic Test Conditions
1135
Figure 23.74 Output Load Circuit
1135
Change in Delay Time Based on Load Capacitance
1136
Figure 23.75 Load Capacitance−Delay Time
1136
Appendix A Address List
1137
Table A.1 Address List
1137
Appendix B Package Dimensions
1145
Figure B.1 Package Dimensions (256-Pin QFP)
1145
Figure B.2 Package Dimensions (256-Pin BGA: Devices Other than HD6417751RBA240HV)
1146
Appendix C Mode Pin Settings
1149
Table C.1 Clock Operating Modes (SH7751)
1149
Table C.2 Clock Operating Modes (SH7751R)
1150
Table C.3 Area 0 Memory Map and Bus Width
1150
Table C.4 Endian
1150
Table C.5 Master/Slave
1151
Table C.6 Clock Input
1151
Table C.7 PCI Mode
1151
Appendix D Pin Functions
1153
Pin States
1153
Table D.1 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable, Disable Common)
1153
Table D.2 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable)
1155
Table D.3 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Disable)
1157
Handling of Unused Pins
1158
Note on Pin Processing
1159
Table D.4 Handling of Pins When PCI Is Not Used
1159
Appendix E Synchronous DRAM Address Multiplexing Tables
1161
Appendix F Instruction Prefetching and Its Side Effects
1173
Appendix G Power-On and Power-Off Procedures
1175
Power-On Stipulations
1175
Power-Off Stipulations
1175
Common Stipulations for Power-On and Power-Off
1178
Appendix H Product Lineup
1179
Table H.1 SH7751/SH7751R Product Lineup
1179
Appendix I Version Registers
1181
Table I.1 Register Configuration
1181
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