Page 1 REJ09B0261-0100 SH7785 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC Engine Family SH7780 Series Rev.1.00 Revision Date: Jan. 10, 2008...
Page 2 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4 Rev.1.00 Jan. 10, 2008 Page iv of xxx REJ09B0261-0100...
Page 5 This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas Technology-original RISC CPU (SH-4A) and various peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems.
Page 6 Abbreviations Arithmetic Logic Unit ASID Address Space Identifier Ball Grid Array Timer/Counter (Compare Match Timer) Clock Pulse Generator Central Processing Unit Double Data Rate DDRIF DDR-SDRAM Interface Direct Memory Access DMAC Direct Memory Access Controller FIFO First-In First-Out Floating-point Unit Audio Codec H-UDI User Debugging Interface...
Page 7 Most Significant Bit Program Counter Peripheral Component Interconnect PCIC PCI (local bus) Controller Pin Function Controller RISC Reduced Instruction Set Computer Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO Serial Sound Interface Test Access Port Translation Lookaside Buffer Timer Unit UART...
Page 8 All trademarks and registered trademarks are the property of their respective owners. Rev.1.00 Jan. 10, 2008 Page viii of xxx REJ09B0261-0100...
Page 9: Table Of Contents
Section 1 Overview ... 1 Features of the SH7785... 1 Block Diagram ... 13 Pin Arrangement Table ... 14 Pin Arrangement ... 22 Physical Memory Address Map ... 24 Section 2 Programming Model Data Formats... 25 Register Descriptions ... 26 2.2.1 Privileged Mode and Banks ...
Page 10 5.2.2 Exception Event Register (EXPEVT)... 91 5.2.3 Interrupt Event Register (INTEVT)... 92 5.2.4 Non-Support Detection Exception Register (EXPMASK) ... 93 Exception Handling Functions... 95 5.3.1 Exception Handling Flow ... 95 5.3.2 Exception Handling Vector Addresses ... 95 Exception Types and Priorities ... 96 Exception Flow ...
Page 11 7.1.1 Address Spaces ... 146 Register Descriptions ... 152 7.2.1 Page Table Entry High Register (PTEH)... 153 7.2.2 Page Table Entry Low Register (PTEL) ... 154 7.2.3 Translation Table Base Register (TTB) ... 155 7.2.4 TLB Exception Address Register (TEA) ... 156 7.2.5 MMU Control Register (MMUCR) ...
Page 12 7.8.1 Overview of 32-Bit Address Extended Mode... 199 7.8.2 Transition to 32-Bit Address Extended Mode ... 200 7.8.3 Privileged Space Mapping Buffer (PMB) Configuration ... 200 7.8.4 PMB Function... 202 7.8.5 Memory-Mapped PMB Configuration ... 203 7.8.6 Notes on Using 32-Bit Address Extended Mode ... 204 32-Bit Boot Function ...
Page 13 Store Queues ... 238 8.7.1 SQ Configuration... 238 8.7.2 Writing to SQ... 238 8.7.3 Transfer to External Memory... 239 8.7.4 Determination of SQ Access Exception... 240 8.7.5 Reading from SQ ... 240 Notes on Using 32-Bit Address Extended Mode ... 241 Section 9 On-Chip Memory Features...
Page 14 10.4 Interrupt Sources... 324 10.4.1 NMI Interrupts... 324 10.4.2 IRQ Interrupts... 324 10.4.3 IRL Interrupts ... 325 10.4.4 On-Chip Peripheral Module Interrupts ... 327 10.4.5 Priority of On-Chip Peripheral Module Interrupts... 328 10.4.6 Interrupt Exception Handling and Priority ... 329 10.5 Operation ...
Page 15 11.5.9 Bus Arbitration ... 448 11.5.10 Master Mode... 450 11.5.11 Slave Mode ... 451 11.5.12 Cooperation between Master and Slave... 451 11.5.13 Power-Down Mode and Bus Arbitration ... 451 11.5.14 Mode Pin Settings and General Input Output Port Settings about Data Bus Width...
Page 16 12.5.11 Method for Securing Time Required for Initialization, Self-Refresh Cancellation, etc..549 12.5.12 Regarding the Supported Clock Ratio ... 549 12.5.13 Regarding MCKE Signal Operation ... 550 Section 13 PCI Controller (PCIC) 13.1 Features... 551 13.2 Input/Output Pins... 554 13.3 Register Descriptions...
Page 17 14.4.2 Channel Priority... 706 14.4.3 DMA Transfer Types... 709 14.4.4 DMA Transfer Flow ... 717 14.4.5 Repeat Mode Transfer ... 719 14.4.6 Reload Mode Transfer ... 720 14.4.7 DREQ Pin Sampling Timing ... 721 14.5 DMAC Interrupt Sources ... 729 14.6 Usage Notes ...
Page 18 16.4.1 Reset Request ... 769 16.4.2 Using Watchdog Timer Mode ... 771 16.4.3 Using Interval Timer Mode ... 771 16.4.4 Time until WDT Counters Overflow... 772 16.4.5 Clearing WDT Counters ... 773 16.5 Status Pin Change Timing during Reset ... 774 Power-On Reset by PRESET Pin ...
Page 19 18.3.4 Timer Control Registers (TCRn) (n = 0 to 5) ... 807 18.3.5 Input Capture Register 2 (TCPR2) ... 809 18.4 Operation ... 810 18.4.1 Counter Operation ... 810 18.4.2 Input Capture Function ... 813 18.5 Interrupts... 814 18.6 Usage Notes ... 815 18.6.1 Register Writes ...
Page 20 19.3.26 Color Palette 4 Transparent Color Register (CP4TR) ... 887 19.3.27 Display Off Mode Output Register (DOOR)... 890 19.3.28 Color Detection Register (CDER) ... 891 19.3.29 Background Plane Output Register (BPOR)... 892 19.3.30 Raster Interrupt Offset Register (RINTOFSR) ... 894 19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6) ...
Page 21 19.4.12 Scroll Display ... 950 19.4.13 Wraparound Display ... 951 19.4.14 Upper-Left Overflow Display... 952 19.4.15 Double Buffer Control ... 953 19.4.16 Sync Mode ... 954 19.5 Display Control... 956 19.5.1 Display Timing Generation ... 956 19.5.2 CSYNC... 959 19.5.3 Scan Method ...
Page 22 20.3.21 MC Command FIFO (MCCF) ... 1000 20.3.22 MC Status Register (MCSR) ... 1003 20.3.23 MC Frame Width Setting Register (MCWR) ... 1004 20.3.24 MC Frame Height Setting Register (MCHR) ... 1005 20.3.25 MC Y Padding Size Setting Register (MCYPR) ... 1006 20.3.26 MC UV Padding Size Setting Register (MCUVPR) ...
Page 23 21.3.12 Serial Port Register n (SCSPTR) ... 1066 21.3.13 Line Status Register n (SCLSR) ... 1069 21.3.14 Serial Error Register n (SCRER) ... 1070 21.4 Operation ... 1071 21.4.1 Overview ... 1071 21.4.2 Operation in Asynchronous Mode ... 1074 21.4.3 Operation in Clocked Synchronous Mode ...
Page 24 23.2 Input/Output Pins... 1153 23.3 Register Descriptions... 1153 23.3.1 Control Register (SPCR) ... 1155 23.3.2 Status Register (SPSR) ... 1158 23.3.3 System Control Register (SPSCR) ... 1161 23.3.4 Transmit Buffer Register (SPTBR) ... 1163 23.3.5 Receive Buffer Register (SPRBR)... 1164 23.4 Operation ...
Page 25 24.4.1 Operations in MMC Mode... 1209 24.5 MMCIF Interrupt Sources... 1239 24.6 Operations when Using DMA... 1240 24.6.1 Operation in Read Sequence... 1240 24.6.2 Operation in Write Sequence ... 1250 24.7 Register Accesses with Little Endian Specification... 1261 Section 25 Audio Codec Interface (HAC) 25.1 Features...
Page 26 26.4 Operation ... 1314 26.4.1 Bus Format ... 1314 26.4.2 Non-Compressed Modes ... 1315 26.4.3 Compressed Modes... 1324 26.4.4 Operation Modes ... 1327 26.4.5 Transmit Operation... 1328 26.4.6 Receive Operation ... 1331 26.4.7 Serial Clock Control ... 1334 26.5 Usage Note... 1335 26.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation ...
Page 27 Section 28 General Purpose I/O Ports (GPIO) 28.1 Features... 1377 28.2 Register Descriptions ... 1382 28.2.1 Port A Control Register (PACR) ... 1386 28.2.2 Port B Control Register (PBCR)... 1389 28.2.3 Port C Control Register (PCCR)... 1391 28.2.4 Port D Control Register (PDCR) ... 1393 28.2.5 Port E Control Register (PECR) ...
Page 28 28.2.37 Port L Pull-Up Control Register (PLPUPR)... 1438 28.2.38 Port M Pull-Up Control Register (PMPUPR)... 1439 28.2.39 Port N Pull-Up Control Register (PNPUPR) ... 1440 28.2.40 Input-Pin Pull-Up Control Register 1 (PPUPR1) ... 1441 28.2.41 Input-Pin Pull-Up Control Register 2 (PPUPR2) ... 1441 28.2.42 Peripheral Module Select Register 1 (P1MSELR) ...
Page 29 30.3.2 Interrupt Source Register (SDINT)... 1492 30.3.3 Bypass Register (SDBPR) ... 1493 30.3.4 Boundary Scan Register (SDBSR) ... 1493 30.4 Operation ... 1503 30.4.1 Boundary-Scan TAP Controller (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS) ... 1503 30.4.2 TAP Control... 1505 30.4.3 H-UDI Reset ... 1506 30.4.4 H-UDI Interrupt ...
Page 30 Appendix ... 1627 Package Dimensions ... 1627 Mode Pin Settings... 1628 Pin Functions ... 1631 Pin States ... 1631 Handling of Unused Pins ... 1642 Turning On and Off Power Supply ... 1653 Turning On and Off Between Each Power Supply Series ... 1653 Power-On and Power-Off Sequences for Power Supplies with Different Potentials in DDR2-SDRAM Power Supply Backup Mode...
Page 31: Section 1 Overview
The SH7785 incorporates a DDR2-SDRAM interface, a PCI controller, a DMA controller, timers, serial interfaces, audio interfaces, a graphics data translation accelerator (GDTA) that supports YUV data conversion and motion compensation processing, and a display unit (DU) that supports digital RGB display. The DDR2 interface, PCI interface, and the local bus are independent, providing dedicated external bus interfaces for the transfer of large amounts of data and of streaming data.
Page 32 1. Overview Item Features • Renesas Technology original architecture • 32-bit internal data bus • General-register files: ⎯ Sixteen 32-bit general registers (eight 32-bit shadow registers) ⎯ Seven 32-bit control registers ⎯ Four 32-bit system registers • RISC-type instruction set (upward compatibility for the SH-1, SH-2, SH-3 and SH-4 processors) ⎯...
Page 33 Item Features • On-chip floating-point coprocessor • Supports single (32-bit) and double (64-bit) precisions • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation to zero or interrupt- generation for IEEE754 compliance •...
Page 34 1. Overview Item Features • Memory 4-Gbyte address space, 256 address space identifiers (8-bit ASID) management • Supports single virtual memory mode and multiple virtual memory mode unit (MMU) • Multiple page sizes: 1, 4, 8, 64, or 256 Kbytes, or 1, 4, or 64 Mbytes •...
Page 35 Item Features • URAM 128-Kbyte large-capacity memory • Three independent read/write ports • 8-/16-/32-bit access by the CPU or the FPU • 8-/16-/32-bit access by the DMAC • Interrupt controller Nine independent external interrupts: NMI and IRQ7 to IRQ0 (INTC) ⎯...
Page 36 1. Overview Item Features • Local bus state A dedicated Local-bus interface controller (LBSC) ⎯ Controls the external memory space divided into seven 64-Mbyte (max.) areas ⎯ The interface type, bus width, and wait-cycle insertion can be set for each area. •...
Page 37 Item Features • DDR2-SDRAM bus A dedicated DDR2-SDRAM bus interface controller (DBSC) ⎯ Multi-bank support: Supports multi-bank (four banks) operation ⎯ Number of banks: Supports four or eight banks (however, no more than four banks can be opened concurrently) ⎯ Selectable bus width: 32-/16-bit ⎯...
Page 38 1. Overview Item Features • PCI bus controller PCI bus controller (supports a subset of revision 2.2) (PCIC) ⎯ 32-bit bus (33 MHz or 66 MHz) • Operation as PCI master/target • Operation in PCI host/normal mode ⎯ Built-in bus arbiter (host mode) •...
Page 39 Item Features • Watchdog timer Number of channels: One (WDT) • Single-channel watchdog timer (operation in watchdog-timer or interval-timer mode is selectable) • Selectable reset function: Power-on or manual reset • Timer unit (TMU) Number of channels: Six • 6-channel auto-reloading 32-bit down-counter •...
Page 40 1. Overview Item Features • Display unit (DU) Display plane ⎯ 6 planes (a maximum number at 480 dots x 234 dots) ⎯ 4 planes (a maximum number at 854 dots x 480 dots) ⎯ 3 planes (a maximum number at 800 dots x 600 dots) •...
Page 41 Item Features • Synchronized serial Number of channels: One (max.) I/O with FIFO • Supports full-duplex operation (SIOF) • Separate 64-byte (32 bits x 16) FIFOs for transmission and reception • Supports the input and output of 8-/16-bit monaural and 16-bit stereophonic audio data •...
Page 42 1. Overview Item Features • Serial sound Number of channels: Two (max.) interface (SSI) • Supports transfer of compressed and non-compressed data • Selectable frame size • NAND flash Number of channels: One (max.) memory • Exclusively for NAND-type flash memory controller (FLCTL) •...
Page 43: Block Diagram
Block Diagram A block diagram of the SH7785 is given as figure 1.1. 32 bit/16 bit 300 MHz DDR2-SDRAM DDR2-400/600 1 GB max DDR bus 64*/32/16 /8 bit 100 MHz NOR Flash SRAM Local bus PC Card/ATA3 Note: * The PCI bus and the display unit are not available when the local bus width is 64 bits. The PCI controller and the display unit cannot be used when the local bus width is 64 bits.
Page 44: Pin Arrangement Table
1. Overview Pin Arrangement Table Table 1.2 Pin Function No. Pin Name Function MDQ0 DDR data 0 MDQ1 DDR data 1 MDQ2 DDR data 2 MDQ3 DDR data 3 MDQ4 DDR data 4 MDQ5 DDR data 5 MDQ6 DDR data 6 MDQ7 DDR data 7 MDQ8...
Page 45 No. Pin Name Function MA10 DDR address 10 MA11 DDR address 11 MA12 DDR address 12 MA13 DDR address 13 MA14 DDR address 14 MBA0 DDR bank address 0 MBA1 DDR bank address 1 MBA2 DDR bank address 2 MCK0 DDR clock 0 MCK0 DDR clock 0 (antiphase)
Page 46 1. Overview No. Pin Name Function 119 A12 Local bus address 12 120 A13 Local bus address 13 121 A14 Local bus address 14 122 A15 Local bus address 15 123 A16 Local bus address 16 124 A17 Local bus address 17 125 A18 Local bus address 18 126 A19...
Page 47 No. Pin Name Function 155 D37/AD5/DR5 IO/IO/O Local bus data 37/PCI address data 5/Digital red 5 156 D38/AD6/DG0 IO/IO/O Local bus data 38/PCI address data 6/Digital green 157 D39/AD7/DG1 IO/IO/O Local bus data 39/PCI address data 7/Digital green 158 D40/AD8/DG2 IO/IO/O Local bus data 40/PCI address data 8/Digital green 159 D41/AD9/DG3...
Page 48 1. Overview No. Pin Name Function 181 D63/AD31 IO/IO Local bus data 63/PCI address data 31 182 WE4/CBE0 O/IO Write enable 4/PCI command/byte enable 0 183 WE5/CBE1 O/IO Write enable 5/PCI command/byte enable 1 184 WE6/CBE2 O/IO Write enable 6/PCI command/byte enable 2 185 WE7/CBE3 O/IO...
Page 49 No. Pin Name Function 217 BREQ/BSACK Bus request (Master mode)/ Bus acknowledgement (Slave mode) 218 BACK/BSREQ Bus acknowledgement (Master mode)/Bus request (Slave mode) 219 DREQ0 DMA channel 0 request 220 DREQ1 DMA channel 1 request 221 DREQ2/INTB DMA channel 2 request/PCI interrupt B 222 DREQ3/INTC DMA channel 3 request/PCI...
Page 50 1. Overview No. Pin Name Function 249 SIOF_SCK/ IO/I/IO SIOF serial clock/HAC0 bit HAC0_BITCLK/ clock/SSI0 serial bit clock SSI0_CLK 250 SIOF_MCLK/ SIOF master clock/HAC HAC_RES reset 251 SIOF_SYNC/ IO/O/IO SIOF flame HAC0_SYNC/ synchronous/HAC0 flame SSI0_WS synchronous/SSI0 word select 252 SIOF_RXD/ I/I/IO SIOF receive data/HAC0 HAC0_SDIN/...
Page 51 No. Pin Name Function 269 MODE11/ I/IO/IO Mode control 11/SCIF4 SCIF4_SCK/ serial clock/NAND flash data 270 MODE12/ I/O/O Mode control 12/DMA DRAK3/CE2B channel 3 transfer request acknowledge 3/PCMCIA CE2B 271 MODE13/ I/IO/I TMU clock/PCMCIA IOIS16 TCLK/IOIS16 272 MPMD H-UDI emulator mode 273 MODE14 Mode control 14 Note:...
Page 52: Pin Arrangement
1. Overview Pin Arrangement Package: 436-pin FC-BGA, 19 mm x 19 mm, ball pitch: 0.8 mm MCK0 MCKE MBA0 MDQ1 VDD- VDD- MCK0 MCK1 MDQ2 MCK1 MBKPRST MODT MBA2 MA11 MDQ4 VDD- VDD- MBA1 MVREF MA13 MCAS MRAS MA10 VDD- MA14 MDQ22 MDQ17...
Page 53 VDDQ VDDQ SCIF5_TXD SCIF5_RXD /HAC1_ /HAC1_ SYNC/SSI1_ SDIN/SSI1_ SCIF5_SCK MODE11/ /HAC1_SD VDDQ VDDQ SCIF4_SCK OUT/SSI1_ /FD3 SDATA SIOF_SYNC SIOF_MCLK HAC1_BIT MODE9/S /HAC0_ /HAC_RES CLK/SSI1_ CIF4_TXD/ SYNC/ SSI0_WS SIOF_TXD/ SIOF_SCK HAC0_SDO /HAC0_BIT VDDQ UT/SSI0_ CLK/SSI0_ SDATA SIOF_RXD MODE10/ SCIF1_ SCIF1_ MODE6/ /HAC0_SDI VDDQ SCIF4_RXD...
Page 54: Physical Memory Address Map
1. Overview Physical Memory Address Map The SH7785 supports 32-bit virtual address space, and supports both 29-bit and 32-bit physical address spaces. For details of mappings from the virtual address space to the physical address spaces, see section 7, Memory Management Unit (MMU). Figure 1.4 shows the relationship between the AREASEL bits and the physical memory address map.
Page 55: Section 2 Programming Model
Section 2 Programming Model The programming model of this LSI is explained in this section. This LSI has registers and data formats as shown below. Data Formats The data formats supported in this LSI are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) Single-precision floating-point (32 bits)
Page 56: Register Descriptions
2. Programming Model Register Descriptions 2.2.1 Privileged Mode and Banks Processing Modes This LSI has two processing modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted.
Page 57 (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), and the program counter (PC). Access to these registers does not depend on the processing mode.
Page 58 2. Programming Model Table 2.1 Initial Register Values Type Registers General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, R8 to R15 Control registers GBR, SSR, SPC, SGR, DBR Undefined System registers MACH, MACL, PR Floating-point FR0 to FR15, XF0 to XF15, registers FPUL FPSCR...
Page 59 R0 _ BANK0* R1 _ BANK0* R2 _ BANK0* R3 _ BANK0* R4 _ BANK0* R5 _ BANK0* R6 _ BANK0* R7 _ BANK0* MACH MACL (a) Register configuration in user mode Notes: 1. R0 is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode.
Page 60: General Registers
2. Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0 to R15 in one processing mode.
Page 61: Floating-Point Registers
Note on Programming: As the user's R0 to R7 are assigned to R0_BANK0 to R7_BANK0, and after an exception or interrupt R0 to R7 are assigned to R0_BANK1 to R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0 to R7 (R0_BANK0 to R7_BANK0).
Page 62 2. Programming Model 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = FPSCR.FR = 0 DR10 FR10 FR11 FV12 DR12 FR12 FR13 DR14 FR14 FR15 XMTRX XD10 XF10 XF11 XD12 XF12 XF13 XD14 XF14 XF15 Rev.1.00 Jan.
Page 63: Control Registers
2.2.4 Control Registers Status Register (SR) BIt: Initial value: R/W: BIt: Initial value: R/W: Initial Bit Name Value — Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product. Processing Mode Selects the processing mode. 0: User mode (Some instructions cannot be executed and some resources cannot be accessed.) 1: Privileged mode...
Page 64 2. Programming Model Initial Bit Name Value 27 to 16 — All 0 14 to 10 — All 0 7 to 4 IMASK 1111 3, 2 — All 0 Rev.1.00 Jan. 10, 2008 Page 34 of 1658 REJ09B0261-0100 Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
Page 65: System Registers
Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined) The contents of SR are saved to SSR in the event of an exception or interrupt. Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value = Undefined) The address of an instruction at which an interrupt or exception occurs is saved to SPC.
Page 66 2. Programming Model Floating-Point Status/Control Register (FPSCR) BIt: Initial value: R/W: BIt: Cause Initial value: R/W: Initial Bit Name Value 31 to 22 — All 0 Rev.1.00 Jan. 10, 2008 Page 36 of 1658 REJ09B0261-0100 Enable (EN) Description Reserved For details on reading/writing this bit, see General Precautions on Handling of Product.
Page 67 Initial Bit Name Value 17 to 12 Cause 000000 11 to 7 Enable (EN) 00000 6 to 2 Flag 00000 1, 0 Description FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0.
Page 68 2. Programming Model <Big endian> Floating-point register FR (2i) Memory area <Little endian> Floating-point register FR (2i) Memory area 4n+3 Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used. 2. The bit-location of DR register is used for double precision format when PR = 1. Figure 2.5 Relationship between SZ bit and Endian Table 2.2 Bit Allocation for FPU Exception Handling...
Page 69: Memory-Mapped Registers
Memory-Mapped Registers Some control registers are mapped to the following memory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. • H'1C00 0000 to H'1FFF FFFF This area must be accessed using the address translation function of the MMU.
Page 70: Data Formats In Registers
2. Programming Model Data Formats in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. Figure 2.6 Formats of Byte Data and Word Data in Register Data Formats in Memory Memory data formats are classified into bytes, words, and longwords.
Page 71: Processing States
Address A Byte 0 Address A + 4 Word 0 Address A + 8 For the 64-bit data format, see figure 2.5. Processing States This LSI has major three processing states: the reset state, instruction execution state, and power- down state. Reset State In this state the CPU is reset.
Page 72 2. Programming Model From any state when reset/manual reset input Reset/manual reset clearance Instruction execution state Figure 2.8 Processing State Transitions Rev.1.00 Jan. 10, 2008 Page 42 of 1658 REJ09B0261-0100 Reset state Reset/manual Reset/manual reset input reset input Sleep instruction execution Power-down state Interrupt occurence...
Page 73: Usage Notes
Usage Notes 2.7.1 Notes on Self-Modifying Code To accelerate the processing speed, the instruction prefetching capability of this LSI has been significantly enhanced from that of the SH-4. Therefore, in the case when a code in memory is rewritten and attempted to be executed immediately, there is increased possibility that the code before being modified, which has already been prefetched, is executed.
Page 74 2. Programming Model Rev.1.00 Jan. 10, 2008 Page 44 of 1658 REJ09B0261-0100...
Page 75: Section 3 Instruction Set
Section 3 Instruction Set This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size.
Page 76 3. Instruction Set Table 3.1 Execution Order of Delayed Branch Instructions TARGET target-inst A slot illegal instruction exception may occur when a specific instruction is executed in a delay slot. For details, see section 5, Exception Handling. The instruction following BF/S or BT/S for which the branch is not taken is also a delay slot instruction.
Page 77: Addressing Modes
Addressing Modes Addressing modes and effective address calculation methods are shown in table 3.2. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (SV in MMUCR = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 78 3. Instruction Set Addressing Instruction Mode Format Register @–Rn indirect with pre- decrement Register @(disp:4, Rn) Effective address is register Rn contents with indirect with displacement Indexed @(R0, Rn) register indirect Rev.1.00 Jan. 10, 2008 Page 48 of 1658 REJ09B0261-0100 Effective Address Calculation Method Effective address is register Rn contents, decremented by a constant beforehand:...
Page 79 Addressing Instruction Mode Format GBR indirect @(disp:8, with displace- GBR) ment Indexed GBR @(R0, GBR) indirect PC-relative @(disp:8, PC) with displacement Effective Address Calculation Method Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size.
Page 80 3. Instruction Set Addressing Instruction Mode Format Effective Address Calculation Method PC-relative disp:8 Effective address is PC + 4 with 8-bit displacement disp added after being sign-extended and multiplied by 2. (sign-extended) PC-relative disp:12 Effective address is PC + 4 with 12-bit displacement disp added after being sign-extended and multiplied by 2.
Page 81 Addressing Instruction Mode Format Effective Address Calculation Method Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. #imm:8 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4.
Page 82: Instruction Set
3. Instruction Set Instruction Set Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13. Table 3.3 Notation Used in Instruction List Item Format Instruction OP.Sz SRC, DEST mnemonic Operation notation MSB ↔ LSB Instruction code Rev.1.00 Jan.
Page 83 Item Format Privileged mode T bit Value of T bit after instruction execution ⎯ Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand. Table 3.4 Fixed-Point Transfer Instructions Instruction Operation imm → sign extension → Rn #imm,Rn @(disp*,PC), Rn (disp ×...
Page 84 3. Instruction Set Instruction MOV.B @(disp*,Rm),R0 MOV.W @(disp*,Rm),R0 MOV.L @(disp*,Rm),Rn MOV.B Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp*,GBR) MOV.W R0,@(disp*,GBR) MOV.L R0,@(disp*,GBR) MOV.B @(disp*,GBR),R0 MOV.W @(disp*,GBR),R0 MOV.L @(disp*,GBR),R0 MOVA @(disp*,PC),R0 MOVCO.L R0,@Rn MOVLI.L @Rm,R0 MOVUA.L @Rm,R0 MOVUA.L...
Page 85 SWAP.W Rm,Rn words → Rn Rm:Rn middle 32 bits → Rn 0010nnnnmmmm1101 — XTRCT Rm,Rn The assembler of Renesas uses the value after scaling (×1, ×2, or ×4) as the Note: displacement (disp). Table 3.5 Arithmetic Operation Instructions Instruction Operation Rn + Rm →...
Page 86 3. Instruction Set Instruction Operation CMP/STR Rm,Rn When any bytes are equal, 1 → T Otherwise, 0 → T 1-step division (Rn ÷ Rm) DIV1 Rm,Rn MSB of Rn → Q, DIV0S Rm,Rn MSB of Rm → M, M^Q → 0 →...
Page 87 Instruction Operation MULU.W Rm,Rn Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 0 – Rm → Rn Rm,Rn 0 – Rm – T → Rn, NEGC Rm,Rn borrow → T Rn – Rm → Rn Rm,Rn Rn –...
Page 88 3. Instruction Set Instruction Operation R0 ∧ imm → R0 #imm,R0 (R0 + GBR) ∧ imm → XOR.B #imm, @(R0,GBR) (R0 + GBR) Table 3.7 Shift Instructions Instruction Operation T ← Rn ← MSB ROTL LSB → Rn → T ROTR T ←...
Page 89 Table 3.8 Branch Instructions Instruction Operation When T = 0, disp × 2 + PC + label 4 → PC When T = 1, nop BF/S label Delayed branch; when T = 0, disp × 2 + PC + 4 → PC When T = 1, nop When T = 1, disp ×...
Page 90 3. Instruction Set Instruction Operation Rm → SSR Rm,SSR Rm → SPC Rm,SPC Rm → DBR Rm,DBR Rm,Rn_BANK Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 (Rm) → SR, Rm + 4 → Rm LDC.L @Rm+,SR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 LDC.L @Rm+,GBR (Rm) →...
Page 91 Instruction Operation 1 → S SETS 1 → T SETT SLEEP Sleep or standby SR → Rn SR,Rn GBR → Rn GBR,Rn VBR → Rn VBR,Rn SSR → Rn SSR,Rn SPC → Rn SPC,Rn SGR → Rn SGR,Rn DBR → Rn DBR,Rn Rm_BANK,Rn Rm_BANK →...
Page 92 3. Instruction Set Instruction Operation SYNCO Data accesses invoked by the following instructions are not executed until execution of data accesses which precede this instruction has been completed. PC + 2 → SPC, TRAPA #imm SR → SSR, R15 → SGR, 1 →...
Page 93 Instruction Operation FRn + FRm → FRn FADD FRm,FRn When FRn = FRm, 1 → T FCMP/EQ FRm,FRn Otherwise, 0 → T When FRn > FRm, 1 → T FCMP/GT FRm,FRn Otherwise, 0 → T FRn/FRm → FRn FDIV FRm,FRn (float) FPUL →...
Page 94 3. Instruction Set Table 3.12 Floating-Point Control Instructions Instruction Operation Rm → FPSCR Rm,FPSCR Rm → FPUL Rm,FPUL LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm+4 → Rm 0100mmmm01100110 (Rm) → FPUL, Rm+4 → Rm LDS.L @Rm+,FPUL FPSCR → Rn FPSCR,Rn FPUL → Rn FPUL,Rn Rn –...
Page 95: Section 4 Pipelining
This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. Pipelines Figure 4.1 shows the basic pipelines. Normally, a pipeline consists of eight stages: instruction fetch (I1/I2/I3), decode and register read (ID), execution (E1/E2/E3), and write-back (WB). An instruction is executed as a combination of basic pipelines.
Page 96 4. Pipelining Figure 4.2 shows the instruction execution patterns. Representations in figure 4.2 and their descriptions are listed in table 4.1. Table 4.1 Representations of Instruction Execution Patterns Representation E1/S1 E1S1 E1s1 FE1 FE2 FE3 FE4 FE5 FE6 FS1 FS2 FS3 FS4 FS Rev.1.00 Jan.
Page 97 (1-1) BF, BF/S, BT, BT/S, BRA, BSR:1 issue cycle + 0 to 3 branch cycles E1/S1 E2/s2 E3/s3 (I1) (1-2) JSR, JMP, BRAF, BSRF: 1 issue cycle + 4 branch cycles E1/S1 E2/S2 E3/S3 (1-3) RTS: 1 issue cycle + 0 to 4 branch cycles E1/S1 E2/S2 E3/S3 (1-4) RTE: 4 issue cycles + 2 branch cycles (1-5) TRAPA: 8 issue cycles + 5 cycles + 2 branch cycle...
Page 98 4. Pipelining (2-1) 1-step operation (EX type): 1 issue cycle EXT[SU].[BW], MOVT, SWAP, XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, CLRS, CLRT, SETS, SETT Note: Except for AND#, OR#, TST#, and XOR# instructions using GBR relative addressing mode (2-2) 1-step operation (LS type): 1 issue cycle MOVA...
Page 99 (3-1) Load/store: 1 issue cycle MOV.[BWL], MOV.[BWL] @(d,GBR) (3-2) AND.B, OR.B, XOR.B, TST.B: 3 issue cycles (3-3) TAS.B: 4 issue cycles (3-4) PREF, OCBI, OCBP, OCBWB, MOVCA.L, SYNCO: 1 issue cycle (3-5) LDTLB: 1 issue cycle E1s1 (3-6) ICBI: 8 issue cycles + 5 cycles + 4 branch cycle (3-7) PREFI: 5 issue cycles + 5 cycles + 4 branch cycle E1s1 (3-8) MOVLI.L: 1 issue cycle...
Page 100 4. Pipelining (4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle (4-2) LDC to DBR/SGR: 4 issue cycles (4-3) LDC to GBR: 1 issue cycle (4-4) LDC to SR: 4 issue cycles + 4 branch cycles (4-5) LDC.L to Rp_BANK/SSR/SPC/VBR: 1 issue cycle (4-6) LDC.L to DBR/SGR: 4 issue cycles (4-7) LDC.L to GBR: 1 issue cycle (4-8) LDC.L to SR: 6 issue cycles + 4 branch cycles...
Page 101 (4-9) STC from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-10) STC from SR: 1 issue cycle (4-11) STC.L from DBR/GBR/Rp_BANK/SSR/SPC/VBR/SGR: 1 issue cycle (4-12) STC.L from SR: 1 issue cycle (4-13) LDS to PR: 1 issue cycle (4-14) LDS.L to PR: 1 issue cycle (4-15) STS from PR: 1 issue cycle (4-16) STS.L from PR: 1 issue cycle (4-17) BSRF, BSR, JSR delay slot instructions (PR set): 0 issue cycle...
Page 102 4. Pipelining (5-1) LDS to MACH/L: 1 issue cycle (5-2) LDS.L to MACH/L: 1 issue cycle (5-3) STS from MACH/L: 1 issue cycle (5-4) STS.L from MACH/L: 1 issue cycle (5-5) MULS.W, MULU.W: 1 issue cycle (5-6) DMULS.L, DMULU.L, MUL.L: 1 issue cycle (5-7) CLRMAC: 1 issue cycle (5-8) MAC.W: 2 issue cycle (5-9) MAC.L: 2 issue cycle...
Page 103 (6-1) LDS to FPUL: 1 issue cycle (6-2) STS from FPUL: 1 issue cycle (6-3) LDS.L to FPUL: 1 issue cycle (6-4) STS.L from FPUL: 1 issue cycle (6-5) LDS to FPSCR: 1 issue cycle (6-6) STS from FPSCR: 1 issue cycle (6-7) LDS.L to FPSCR: 1 issue cycle (6-8) STS.L from FPSCR: 1 issue cycle (6-9) FPU load/store instruction FMOV: 1 issue cycle...
Page 104 4. Pipelining (6-12) Single-precision FABS, FNEG/double-precision FABS, FNEG: 1 issue cycle (6-13) FLDI0, FLDI1: 1 issue cycle (6-14) Single-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG, FPCHG (6-15) Single-precision FDIV/FSQRT: 1 issue cycle (6-16) Double-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FSUB, FTRC, FCNVSD, FCNVDS (6-17) Double-precision floating-point computation: 1 issue cycle...
Page 105 (6-19) FIPR: 1 issue cycle (6-20) FTRV: 1 issue cycle (6-21) FSRRA: 1 issue cycle (6-22) FSCA: 1 issue cycle Figure 4.2 Instruction Execution Patterns (9) FEPL Function computing unit occupied cycle FEPL Function computing unit occupied cycle Rev.1.00 Jan. 10, 2008 Page 75 of 1658 4.
Page 106: Parallel-Executability
4. Pipelining Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 4.2. Table 4.3 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 4.2 Instruction Groups Instruction...
Page 107 Instruction Group FADD FSUB FCMP (S/D) FCNVDS FCNVSD AND.B #imm,@(R0,GBR) ICBI LDC Rm,DBR LDC Rm, SGR LDC Rm,SR LDC.L @Rm+,DBR LDC.L @Rm+,SGR Legend: Rm/Rn @adr: Address SR1: MACH/MACL/PR SR2: FPUL/FPSCR CR1: GBR/Rp_BANK/SPC/SSR/VBR CR2: CR1/DBR/SGR FRm/FRn/DRm/DRn/XDm/XDn The parallel execution of two instructions can be carried out under following conditions. 1.
Page 108 4. Pipelining Table 4.3 Combination of Preceding and Following Instructions Following Instruction (addr+2) Rev.1.00 Jan. 10, 2008 Page 78 of 1658 REJ09B0261-0100 Preceding Instruction (addr)
Page 109: Issue Rates And Execution Cycles
Issue Rates and Execution Cycles Instruction execution cycles are summarized in table 4.4. Instruction Group in the table 4.4 corresponds to the category in the table 4.2. Penalty cycles due to a pipeline stall are not considered in the issue rates and execution cycles in this section. 1.
Page 110 4. Pipelining Table 4.4 Issue Rates and Execution Cycles Functional Category No. Instruction Data transfer EXTS.B instructions EXTS.W EXTU.B EXTU.W MOVA MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W...
Page 111 Functional Category No. Instruction Data transfer MOV.L instructions MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVCA.L MOVCO.L MOVLI.L MOVUA.L MOVUA.L MOVT OCBI OCBP OCBWB PREF SWAP.B SWAP.W XTRCT Fixed-point arithmetic instructions ADDC ADDV CMP/EQ CMP/EQ CMP/GE Instruction Group Rm,@-Rn R0,@(disp,Rn) R0,@(disp,Rn)
Page 112 4. Pipelining Functional Category No. Instruction Fixed-point CMP/GT arithmetic CMP/HI instructions CMP/HS CMP/PL CMP/PZ CMP/STR DIV0S DIV0U DIV1 DMULS.L DMULU.L MAC.L MAC.W MUL.L MULS.W MULU.W NEGC SUBC SUBV Logical instructions AND.B OR.B TAS.B Rev.1.00 Jan. 10, 2008 Page 82 of 1658 REJ09B0261-0100 Instruction Group...
Page 113 Functional Category No. Instruction Logical instructions TST.B XOR.B Shift ROTL instructions ROTR ROTCL ROTCR 100 SHAD 101 SHAL 102 SHAR 103 SHLD 104 SHLL 105 SHLL2 106 SHLL8 107 SHLL16 108 SHLR 109 SHLR2 110 SHLR8 111 SHLR16 Branch 112 BF instructions 113 BF/S 114 BT...
Page 114 4. Pipelining Functional Category No. Instruction Branch 120 JMP instructions 121 JSR 122 RTS System 123 NOP control 124 CLRMAC instruction 125 CLRS 126 CLRT 127 ICBI 128 SETS 129 SETT 130 PREFI 131 SYNCO 132 TRAPA 133 RTE 134 SLEEP 135 LDTLB 136 LDC 137 LDC...
Page 115 Functional Category No. Instruction System 150 LDC.L control 151 LDC.L instructions 152 LDS 153 LDS 154 LDS 155 LDS.L 156 LDS.L 157 LDS.L 158 STC 159 STC 160 STC 161 STC 162 STC 163 STC 164 STC 165 STC 166 STC.L 167 STC.L 168 STC.L 169 STC.L...
Page 116 4. Pipelining Functional Category No. Instruction Single- 180 FLDI0 precision 181 FLDI1 floating-point 182 FMOV instructions 183 FMOV.S 184 FMOV.S 185 FMOV.S 186 FMOV.S 187 FMOV.S 188 FMOV.S 189 FLDS 190 FSTS 191 FABS 192 FADD 193 FCMP/EQ 194 FCMP/GT 195 FDIV 196 FLOAT 197 FMAC...
Page 117 Functional Category No. Instruction Double- 210 FABS precision 211 FADD floating-point 212 FCMP/EQ instructions 213 FCMP/GT 214 FCNVDS 215 FCNVSD 216 FDIV 217 FLOAT 218 FMUL 219 FNEG 220 FSQRT 221 FSUB 222 FTRC FPU system 223 LDS control 224 LDS instructions 225 LDS.L 226 LDS.L...
Page 118 4. Pipelining Functional Category No. Instruction Graphics 241 FRCHG acceleration 242 FSCHG instructions 243 FPCHG 244 FSRRA 245 FSCA 246 FTRV Rev.1.00 Jan. 10, 2008 Page 88 of 1658 REJ09B0261-0100 Instruction Group FPUL,DRn XMTRX,FVn Execution Execution Cycles Pattern Issue Rate 6-14 6-14 6-14...
Page 119: Section 5 Exception Handling
Section 5 Exception Handling Summary of Exception Handling Exception handling processing is handled by a special routine which is executed by a reset, general exception handling, or interrupt. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing.
Page 120: Trapa Exception Register (Tra)
5. Exception Handling Table 5.2 States of Register in Each Operating Mode Register Name TRAPA exception register Exception event register Interrupt event register Non-support detection exception register 5.2.1 TRAPA Exception Register (TRA) The TRAPA exception register (TRA) consists of 8-bit immediate data (imm) for the TRAPA instruction.
Page 121: Exception Event Register (Expevt)
5.2.2 Exception Event Register (EXPEVT) The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software. Bit: Initial value: R/W:...
Page 122: Interrupt Event Register (Intevt)
5. Exception Handling 5.2.3 Interrupt Event Register (INTEVT) The interrupt event register (INTEVT) consists of a 14-bit exception code. The exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. Bit: Initial value: R/W: Bit: Initial value:...
Page 123: Non-Support Detection Exception Register (Expmask)
5.2.4 Non-Support Detection Exception Register (EXPMASK) The non-support detection exception register (EXPMASK) is used to enable or disable the generation of exceptions in response to the use of any of functions 1 to 3 listed below. The functions of 1 to 3 are planned not to be supported in the future SuperH-family products. The exception generation functions of EXPMASK can be used in advance of execution;...
Page 124 5. Exception Handling Initial Bit Name Value ⎯ 31 to 5 All 0 MMCAW ⎯ 3, 2 All 0 BRDSSLP RTEDS Rev.1.00 Jan. 10, 2008 Page 94 of 1658 REJ09B0261-0100 Description Reserved For details on reading/writing these bits, see General Precautions on Handling of Product.
Page 125: Exception Handling Functions
Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.
Page 126: Exception Types And Priorities
5. Exception Handling Exception Types and Priorities Table 5.3 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.3 Exceptions Exception Execution Category Mode Exception Reset Abort type Power-on reset Manual reset H-UDI reset Instruction TLB multiple-hit exception Data TLB multiple-hit exception...
Page 127 Exception Execution Category Mode Exception General Completion Unconditional trap (TRAPA) exception type User break after instruction execution* Interrupt Completion Nonmaskable interrupt type General interrupt request Notes: 1. When UBDE in CBCR = 1, PC = DBR. In other cases, PC = VBR + H'100. 2.
Page 128: Exception Flow
5. Exception Handling Exception Flow 5.5.1 Exception Flow Figure 5.1 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.1 shows the relative priority order of the different kinds of exceptions (reset, general exception, and interrupt).
Page 129 Reset requested? Execute next instruction General exception requested? Interrupt requested? SSR ← SR SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.{MD,RB,BL} ← 111 SR.IMASK ← received interuupt level (*) PC ← (CBCR.UBDE=1 && User_Break? Note: * When the exception of the highest priority is an interrupt. Whether IMASK is updated or not can be set by software.
Page 130: Rej09B0261
5. Exception Handling 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline.
Page 131: Exception Requests And Bl Bit
5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, general exceptions and interrupts are accepted. When the BL bit in SR is 1 and an general exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A0000000).
Page 132: Description Of Exceptions
5. Exception Handling Description of Exceptions The various exception handling operations explained here are exception sources, transition address on the occurrence of exception, and processor operation when a transition is made. 5.6.1 Resets Power-On Reset • Condition: Power-on reset request •...
Page 133 Instruction TLB Multiple Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A0000000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 134: General Exceptions
5. Exception Handling 5.6.2 General Exceptions Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 135 Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'00000400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 136 5. Exception Handling Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'00000100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 137 Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits or EPR bits) shown in table 5.4 and table 5.5. Table 5.4 UTLB Protection Information (TLB Compatible Mode) Privileged Mode Only read access possible Read/write access possible Only read access possible Read/write access possible...
Page 138 5. Exception Handling The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
Page 139 Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits or EPR bits) shown in table 5.6 and table5.7. Table 5.6 ITLB Protection Information (TLB Compatible Mode) Privileged Mode Access possible Access possible Table 5.7 ITLB Protection Information (TLB Extended Mode)
Page 140 5. Exception Handling ITLB_protection_violation_exception() TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 00A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; Data Address Error •...
Page 141 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
Page 142 5. Exception Handling Instruction Address Error • Sources: ⎯ Instruction fetch from other than a word boundary (2n +1) ⎯ Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode Area H'E5000000 to H'E5FFFFFF can be accessed in user mode. For details, see section 9, On-Chip Memory.
Page 143 Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'00000100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.
Page 144 5. Exception Handling General Illegal Instruction Exception • Sources: ⎯ Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD ⎯ Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR •...
Page 145 (10) Slot Illegal Instruction Exception • Sources: ⎯ Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD ⎯ Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR, ICBI, PREFI ⎯...
Page 146 5. Exception Handling (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD = 1 • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR.
Page 147 (12) Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'00000100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.
Page 148 5. Exception Handling (13) Pre-Execution User Break/Post-Execution User Break • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'00000100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 149 (14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'00000100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR . The R15 contents at this time are saved in SGR. Exception code H'120 is set in EXPEVT.
Page 150: Interrupts
5. Exception Handling 5.6.3 Interrupts NMI (Nonmaskable Interrupt) • Source: NMI pin edge detection • Transition address: VBR + H'00000600 • Transition operations: The PC and SR contents for the instruction immediately after this exception is accepted are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'1C0 is set in INTEVT.
Page 151: Priority Order With Multiple Exceptions
The code corresponding to the each interrupt source is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. When the INTMU bit in CPUOPM is 1, IMASK bit in SR is changed to accepted interrupt level. For details, see section 10, Interrupt Controller (INTC).
Page 152 5. Exception Handling 8. Initial page write exception in second data transfer Indivisible Delayed Branch Instruction and Delay Slot Instruction As a delayed branch instruction and its associated delay slot instruction are indivisible, they are treated as a single instruction. Consequently, the priority order for exceptions that occur in these instructions differs from the usual priority order.
Page 153: Usage Notes
Usage Notes Return from Exception Handling A. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set the BL bit in SR to 1 before restoring them. B. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the SSR contents are saved in SR, and branch is made to the SPC address to return from the exception handling routine.
Page 154 5. Exception Handling other exceptions is determined depending on the processing mode by SR after restoring or the BL bit. The completion type exception is accepted before branching to the destination of RTE instruction. However, if the re-execution type exception is occurred, the operation cannot be guaranteed.
Page 155: Section 6 Floating-Point Unit (Fpu)
Section 6 Floating-Point Unit (FPU) Features The FPU has the following features. • Conforms to IEEE754 standard • 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) • Two rounding modes: Round to Nearest and Round to Zero •...
Page 156: Data Formats
6. Floating-Point Unit (FPU) Data Formats 6.2.1 Floating-Point Format A floating-point number consists of the following three fields: • Sign bit (s) • Exponent field (e) • Fraction field (f) This LSI can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2.
Page 157 Table 6.1 Floating-Point Number Formats and Parameters Parameter Single-Precision Total bit width 32 bits Sign bit 1 bit Exponent field 8 bits Fraction field 23 bits Precision 24 bits Bias +127 +127 –126 Floating-point number value v is determined as follows: + 1 and f ≠...
Page 158 6. Floating-Point Unit (FPU) Table 6.2 Floating-Point Ranges Type Signaling non-number Quiet non-number Positive infinity Positive normalized number Positive denormalized number Positive zero Negative zero Negative denormalized number Negative normalized number Negative infinity Quiet non-number Signaling non-number Rev.1.00 Jan. 10, 2008 Page 128 of 1658 REJ09B0261-0100 Single-Precision H'7FFF FFFF to H'7FC0 0000...
Page 159: Non-Numbers (Nan)
6.2.2 Non-Numbers (NaN) Figure 6.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case: • Sign bit: Don't care • Exponent field: All bits are 1 • Fraction field: At least one bit is 1 The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN) if the MSB is 0.
Page 160: Denormalized Numbers
6. Floating-Point Unit (FPU) See section 10, Instruction Descriptions of the SH-4A Extended Functions Software Manual for details of floating-point operations when a non-number (NaN) is input. 6.2.3 Denormalized Numbers For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value.
Page 161: Register Descriptions
Register Descriptions 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers comprised with two banks: FPR0_BANK0 to FPR15_BANK0, and FPR0_BANK1 to FPR15_BANK1. These thirty-two registers are referenced as FR0 to FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0 to XF15, XD0/2/4/6/8/10/12/14, and XMTRX. Corresponding registers to FPR0_BANK0 to FPR15_BANK0, and FPR0_BANK1 to FPR15_BANK1 are determined according to the FR bit of FPSCR.
Page 162 6. Floating-Point Unit (FPU) 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = FPSCR.FR = 0 DR10 FR10 FR11 FV12 DR12 FR12 FR13 DR14 FR14 FR15 XMTRX XD10 XD12 XD14 Rev.1.00 Jan. 10, 2008 Page 132 of 1658 REJ09B0261-0100 XF12 XF13...
Page 163: Floating-Point Status/Control Register (Fpscr)
6.3.2 Floating-Point Status/Control Register (FPSCR) bit: Initial value: R/W: bit: Cause Initial value: R/W: Initial Bit Name Value 31 to 22 — All 0 Enable (EN) Description Reserved These bits are always read as 0. The write value should always be 0. Floating-Point Register Bank 0: FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1...
Page 164 6. Floating-Point Unit (FPU) Initial Bit Name Value 17 to 12 Cause All 0 11 to 7 Enable All 0 6 to 2 Flag All 0 Rev.1.00 Jan. 10, 2008 Page 134 of 1658 REJ09B0261-0100 Description FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field Each time an FPU operation instruction is executed, the...
Page 165 <Big endian> Floating-point register DR (2i) FR (2i) FR (2i+1) 32 31 Memory area 8n+3 8n+4 <Little endian> Floating-point register DR (2i) FR (2i) FR (2i+1) 32 31 Memory area 4n+3 4m+3 (1) SZ = 0 Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used. 2.
Page 166: Floating-Point Communication Register (Fpul)
6. Floating-Point Unit (FPU) Table 6.3 Bit Allocation for FPU Exception Handling Field Name Error (E) Cause FPU exception Bit 17 cause field Enable FPU exception None enable field Flag FPU exception None flag field 6.3.3 Floating-Point Communication Register (FPUL) Information is transferred between the FPU and CPU via FPUL.
Page 167: Rounding
Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC, FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL.
Page 168: Floating-Point Exceptions
6. Floating-Point Unit (FPU) Floating-Point Exceptions 6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions FPU-related exceptions are occurred when an FPU instruction is executed with SR.FD set to 1. When the FPU instruction is in other than delayed slot, the general FPU disable exception is occurred.
Page 169: Fpu Exception Handling
6.5.3 FPU Exception Handling FPU exception handling is initiated in the following cases: • FPU error (E): FPSCR.DN = 0 and a denormalized number is input • Invalid operation (V): FPSCR.Enable.V = 1 and (instruction = FTRV or invalid operation) •...
Page 170: Graphics Support Functions
6. Floating-Point Unit (FPU) Graphics Support Functions This LSI supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 Geometric Operation Instructions Geometric operation instructions perform approximate-value computations. To enable high-speed computation with a minimum of hardware, this LSI ignores comparatively small values in the partial computation results of four multiplications.
Page 171: Pair Single-Precision Data Transfer
FTRV XMTRX, FVn (n: 0, 4, 8, 12) This instruction is basically used for the following purposes: • Matrix (4 × 4) ⋅ vector (4): This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). Since affine transformation processing for angle + parallel movement basically requires a 4 ×...
Page 172 6. Floating-Point Unit (FPU) This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use and non-use of pair single-precision data transfer. Rev.1.00 Jan. 10, 2008 Page 142 of 1658 REJ09B0261-0100...
Page 173: Section 7 Memory Management Unit (Mmu)
7. Memory Management Unit (MMU) Section 7 Memory Management Unit (MMU) This LSI supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit or 32-bit physical address space. Address translation from virtual addresses to physical addresses is enabled by the memory management unit (MMU) in this LSI.
Page 174: Overview Of Mmu
7. Memory Management Unit (MMU) Overview of MMU The MMU was conceived as a means of making efficient use of physical memory. As shown in (0) in figure 7.1, when a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory, but if the process increases in size to the point where it does not fit into physical memory, it becomes necessary to divide the process into smaller parts, and map the parts requiring execution onto physical memory as occasion arises ((1) in figure 7.1).
Page 175 There are two methods by which the MMU can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space called a page.
Page 176: Address Spaces
7. Memory Management Unit (MMU) 7.1.1 Address Spaces Virtual Address Space This LSI supports a 32-bit virtual address space, and can access a 4-Gbyte address space. The virtual address space is divided into a number of areas, as shown in figures 7.2 and 7.3. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed.
Page 177 H'0000 0000 P0 area Cacheable Address translation possible H'8000 0000 P1 area Cacheable Address translation not possible H'A000 0000 P2 area Non-cacheable Address translation not possible H'C000 0000 P3 area Cacheable Address translation possible H'E000 0000 P4 area Non-cacheable Address translation not possible H'FFFF FFFF Privileged mode Figure 7.3 Virtual Address Space (AT in MMUCR = 1)
Page 178 7. Memory Management Unit (MMU) (b) P1 Area The P1 area does not allow address translation using the TLB but can be accessed using the cache. Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits of an address to 0 gives the corresponding physical address.
Page 179 7. Memory Management Unit (MMU) The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). In user mode, the access right is specified by the SQMD bit in MMUCR. For details, see section 8.7, Store Queues. The area from H'E500 0000 to H'E5FF FFFF comprises addresses for accessing the on-chip memory.
Page 180 7. Memory Management Unit (MMU) Physical Address Space This LSI supports a 29-bit physical address space. The physical address space is divided into eight areas as shown in figure 7.5. Area 7 is a reserved area. For details, see section 11, Local Bus State Controller (LBSC) section of the hardware manual of the product.
Page 181 the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the SV bit in MMUCR.
Page 182: Register Descriptions
7. Memory Management Unit (MMU) Register Descriptions The following registers are related to MMU processing. Table 7.1 Register Configuration Register Name Page table entry high register Page table entry low register Translation table base register TLB exception address register MMU control register Page table entry assistance register Physical address space control...
Page 183: Page Table Entry High Register (Pteh)
Register Name Instruction re-fetch inhibit control register 7.2.1 Page Table Entry High Register (PTEH) PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN bit by hardware.
Page 184: Page Table Entry Low Register (Ptel)
7. Memory Management Unit (MMU) Initial Bit Name Value 31 to 10 VPN Undefined R/W ⎯ 9, 8 All 0 7 to 0 ASID Undefined R/W 7.2.2 Page Table Entry Low Register (PTEL) PTEL is used to hold the physical page number and page management information to be recorded in the UTLB by means of the LDTLB instruction.
Page 185: Translation Table Base Register (Ttb)
Initial Bit Name Value Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W 7.2.3 Translation Table Base Register (TTB) TTB is used to store the base address of the currently used page table, and so on. The contents of TTB are not changed unless a software directive is issued.
Page 186: Tlb Exception Address Register (Tea)
7. Memory Management Unit (MMU) 7.2.4 TLB Exception Address Register (TEA) After an MMU exception or address error exception occurs, the virtual address at which the exception occurred is stored. The contents of this register can be changed by software. Bit: Virtual address at which MMU exception or address error occurred Initial value:...
Page 187 Bit: LRUI Initial value: R/W: R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W Initial Bit Name Value 31 to 26 LRUI 000000 R/W R/W R/W R/W R/W R/W SQMD SV Description Least Recently Used ITLB These bits indicate the ITLB entry to be replaced.
Page 188 7. Memory Management Unit (MMU) Initial Bit Name Value ⎯ 25, 24 All 0 23 to 18 000000 ⎯ 17, 16 All 0 15 to 10 000000 SQMD Rev.1.00 Jan. 10, 2008 Page 158 of 1658 REJ09B0261-0100 Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product.
Page 189: Page Table Entry Assistance Register (Ptea)
Initial Bit Name Value ⎯ 6 to 3 All 0 ⎯ 7.2.6 Page Table Entry Assistance Register (PTEA) Bit: − − − − Initial value: R/W: Bit: − − − − Initial value: R/W: Description TLB Extended Mode Switching 0: TLB compatible mode 1: TLB extended mode For modifying the ME bit value, always set the TI bit to 1 to invalidate the contents of ITLB and UTLB.
Page 190: Physical Address Space Control Register (Pascr)
7. Memory Management Unit (MMU) Initial Bit Name Value ⎯ 31 to 14 All 0 13 to 8 Undefined 7 to 4 Undefined ⎯ 3 to 0 All 0 7.2.7 Physical Address Space Control Register (PASCR) PASCR controls the operation in the physical address space. Bit: Initial value: R/W:...
Page 191 Initial Bit Name Value ⎯ 31 to 8 All 0 7 to 0 H'00 Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. Buffered Write Control for Each Area (64 Mbytes) When writing is performed without using the cache or in the cache write-through mode, these bits specify whether the next bus access from the CPU waits for the...
Page 192: Instruction Re-Fetch Inhibit Control Register (Irmcr)
7. Memory Management Unit (MMU) 7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR) When the specific resource is changed, IRMCR controls whether the instruction fetch is performed again for the next instruction. The specific resource means the part of control registers, TLB, and cache.
Page 193 Initial Bit Name Value Description Re-Fetch Inhibit 1 after Register Change When a register allocated in addresses H'FF200000 to H'FF2FFFFF is changed, this bit controls whether re- fetch is performed for the next instruction. 0: Re-fetch is performed 1: Re-fetch is not performed Re-Fetch Inhibit after LDTLB Execution This bit controls whether re-fetch is performed for the next instruction after the LDTLB instruction has been...
Page 194: Unified Tlb (Utlb) Configuration
7. Memory Management Unit (MMU) TLB Functions (TLB Compatible Mode; MMUCR.ME = 0) 7.3.1 Unified TLB (UTLB) Configuration The UTLB is used for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2.
Page 195 • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ[1:0]: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page 10: 64-Kbyte page 11: 1-Mbyte page •...
Page 196 7. Memory Management Unit (MMU) 1: Cacheable When the control register area is mapped, this bit must be cleared to 0. • D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed •...
Page 197: Instruction Tlb (Itlb) Configuration
7.3.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 7.8 shows the ITLB configuration. The ITLB consists of four fully-associative type entries. Entry 0 ASID[7:0] Entry 1...
Page 198 7. Memory Management Unit (MMU) VA is VA is in P4 area in P2 area Data TLB miss exception Data TLB multiple hit exception 00 or R/W? Data TLB protection violation exception Internal resource access Figure 7.9 Flowchart of Memory Access Using UTLB (TLB Compatible Mode) Rev.1.00 Jan.
Page 199 Figure 7.10 shows a flowchart of a memory access using the ITLB. Instruction access to virtual address (VA) VA is VA is in P4 area in P2 area Hardware ITLB miss handling Search UTLB Record in ITLB Instruction TLB miss exception Instruction TLB protection violation exception Internal resource access...
Page 200: Tlb Functions (Tlb Extended Mode; Mmucr.me = 1)
7. Memory Management Unit (MMU) TLB Functions (TLB Extended Mode; MMUCR.ME = 1) 7.4.1 Unified TLB (UTLB) Configuration Figure 7.11 shows the configuration of the UTLB in TLB extended mode. Figure 7.12 shows the relationship between the page size and address format. Entry 0 ASID[7:0] Entry 1...
Page 201 0001: 4-Kbyte page 0010: 8-Kbyte page 0100: 64-Kbyte page 0101: 256-Kbyte page 0111: 1-Mbyte page 1000: 4-Mbyte page 1100: 64-Mbyte page Note: When a value other than those listed above is recorded, operation is not guaranteed. • V: Validity bit Indicates whether the entry is valid.
Page 202 7. Memory Management Unit (MMU) EPR[1]: Writing in user mode EPR[0]: Execution in user mode (instruction fetch) • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When the control register area is mapped, this bit must be cleared to 0. •...
Page 203: Instruction Tlb (Itlb) Configuration
1-Kbyte page 4-Kbyte page 8-Kbyte page 64-Kbyte page 256-Kbyte page 20 19 1-Mbyte page 22 21 4-Mbyte page 26 25 64-Mbyte page Figure 7.12 Relationship between Page Size and Address Format (TLB Extended Mode) 7.4.2 Instruction TLB (ITLB) Configuration Figure 7.13 shows the configuration of the ITLB in TLB extended mode. Entry 0 ASID[7:0] VPN[31:10]...
Page 204: Address Translation Method
7. Memory Management Unit (MMU) 7.4.3 Address Translation Method Figure 7.14 is a flowchart of memory access using the UTLB in TLB extended mode. Rev.1.00 Jan. 10, 2008 Page 174 of 1658 REJ09B0261-0100...
Page 205 Data access to virtual address (VA) VA is VA is in P4 area in P2 area CCR.OCE? CCR.CB? Data TLB miss exception Data TLB multiple hit exception 0 (User) R/W? EPR[2]? Data TLB protection violation exception Memory access Internal resource access (Non-cacheable) Figure 7.14 Flowchart of Memory Access Using UTLB (TLB Extended Mode) VA is...
Page 206 7. Memory Management Unit (MMU) Figure 7.15 is a flowchart of memory access using the ITLB in TLB extended mode. Instruction access to virtual address (VA) VA is VA is in P4 area in P2 area CCR.ICE? Hardware ITLB Search UTLB miss handling Match? Record in ITLB...
Page 207: Mmu Hardware Management
MMU Functions 7.5.1 MMU Hardware Management This LSI supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2. The MMU determines the cache access status on the basis of the page management information read during address translation (C and WT bits).
Page 208: Mmu Instruction (Ldtlb)
7. Memory Management Unit (MMU) 7.5.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, this LSI copies the contents of PTEH and PTEL (also the contents of PTEA in TLB extended mode) to the UTLB entry indicated by the URC bit in MMUCR.
Page 209 The operation of the LDTLB instruction is shown in figures 7.16 and 7.17. MMUCR 26252423 LRUI Entry specification PTEH 10 9 8 7 Entry 0 ASID [7:0] VPN [31:10] Entry 1 ASID [7:0] VPN [31:10] Entry 2 ASID [7:0] VPN [31:10] Entry 63 ASID [7:0] VPN [31:10]...
Page 210: Hardware Itlb Miss Handling
7. Memory Management Unit (MMU) MMUCR LRUI Entry specification PTEH − ASID Entry 0 ASID[7:0] Entry 1 ASID[7:0] Entry 2 ASID[7:0] Entry 63 ASID[7:0] Figure 7.17 Operation of LDTLB Instruction (TLB Extended Mode) 7.5.4 Hardware ITLB Miss Handling In an instruction access, this LSI searches the ITLB. If it cannot find the necessary address translation information (ITLB miss occurred), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB.
Page 211: Avoiding Synonym Problems
7.5.5 Avoiding Synonym Problems When information on 1- or 4-Kbyte pages is written as TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is written to a number of cache entries, and it becomes impossible to guarantee data integrity.
Page 212: Instruction Tlb Multiple Hit Exception
7. Memory Management Unit (MMU) MMU Exceptions There are seven MMU exceptions: instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 7.9, 7.10, 7.14, 7.15, and section 5, Exception Handling for the conditions under which each of these exceptions occurs.
Page 213: Instruction Tlb Miss Exception
7.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling routine. The instruction TLB miss exception processing carried out by hardware and software is shown below.
Page 214: Instruction Tlb Protection Violation Exception
7. Memory Management Unit (MMU) 3. In TLB compatible mode, execute the LDTLB instruction and write the contents of PTEH and PTEL to the TLB. In TLB extended mode, execute the LDTLB instruction and write the contents of PTEH, PTEL, PTEA to the UTLB. 4.
Page 215: Data Tlb Multiple Hit Exception
Software Processing (Instruction TLB Protection Violation Exception Handling Routine) Resolve the instruction TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 7.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual...
Page 216 7. Memory Management Unit (MMU) 3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC.
Page 217: Data Tlb Protection Violation Exception
7.6.6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR or EPR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below.
Page 218: Initial Page Write Exception
7. Memory Management Unit (MMU) 7.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted.
Page 219 5. In TLB compatible mode, execute the LDTLB instruction and write the contents of PTEH and PTEL to the TLB. In TLB extended mode, execute the LDTLB instruction and write the contents of PTEH, PTEL, PTEA to the UTLB. 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow.
Page 220: Memory-Mapped Tlb Configuration
7. Memory Management Unit (MMU) Memory-Mapped TLB Configuration To enable the ITLB and UTLB to be managed by software, their contents are allowed to be read from and written to by a program in the P1/P2 area with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area.
Page 221: Itlb Address Array
7.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field.
Page 222: Itlb Data Array (Tlb Compatible Mode)
7. Memory Management Unit (MMU) 7.7.2 ITLB Data Array (TLB Compatible Mode) The ITLB data array is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 223: Itlb Data Array (Tlb Extended Mode)
7.7.3 ITLB Data Array (TLB Extended Mode) In TLB extended mode the names of the data arrays have been changed from ITLB data array to ITLB data array 1, ITLB data array 2 is added, and the EPR and ESZ bits are accessible. In TLB extended mode, the PR and SZ bits of ITLB data array 1 are reserved and 0 should be specified as the write value for these bits.
Page 224 7. Memory Management Unit (MMU) ITLB Data Array 2 The ITLB data array is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. Access to data array 2 requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 225: Utlb Address Array
7.7.4 UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F60F FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, D, V, and ASID to be written to the address array are specified in the data field.
Page 226: Utlb Data Array (Tlb Compatible Mode)
7. Memory Management Unit (MMU) Address field 1 1 1 1 0 1 1 0 0 0 0 0 Data field VPN: Virtual page number Validity bit Entry Dirty bit Don't care Figure 7.22 Memory-Mapped UTLB Address Array 7.7.5 UTLB Data Array (TLB Compatible Mode) The UTLB data array is allocated to addresses H'F700 0000 to H'F70F FFFF in the P4 area.
Page 227: Utlb Data Array (Tlb Extended Mode)
Address field 1 1 1 1 0 1 1 1 0 0 0 0 29 28 Data field PPN: Physical page number Validity bit Entry Page size bits Dirty bit Don't care Figure 7.23 Memory-Mapped UTLB Data Array (TLB Compatible Mode) 7.7.6 UTLB Data Array (TLB Extended Mode) In TLB extended mode, the names of the data arrays have been changed from UTLB data array to...
Page 228 7. Memory Management Unit (MMU) UTLB Data Array 2 The UTLB data array is allocated to addresses H'F780 0000 to H'F78F FFFF in the P4 area. Access to data array 2 requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 229: Bit Address Extended Mode
32-Bit Address Extended Mode Setting the SE bit in PASCR to 1 changes mode from 29-bit address mode which handles the 29- bit physical address space to 32-bit address extended mode which handles the 32-bit physical address space. Virtual address space U0/P0 (2 Gbytes) P1 (0.5 Gbyte)
Page 230: Transition To 32-Bit Address Extended Mode
7. Memory Management Unit (MMU) 7.8.2 Transition to 32-Bit Address Extended Mode This LSI enters 29-bit address mode after a power-on reset. Transition is made to 32-bit address extended mode by setting the SE bit in PASCR to 1. In 32-bit address extended mode, the MMU operates as follows.
Page 231 Legend: • VPN: Virtual page number For 16-Mbyte page: Upper 8 bits of virtual address For 64-Mbyte page: Upper 6 bits of virtual address For 128-Mbyte page: Upper 5 bits of virtual address For 512-Mbyte page: Upper 3 bits of virtual address Note: B'10 should be set to the upper 2 bits of VPN in order to indicate P1 or P2 area.
Page 232: Pmb Function
7. Memory Management Unit (MMU) • WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode • UB: Buffered write bit Specifies whether a buffered write is performed. 0: Buffered write (Data access of subsequent processing proceeds without waiting for the write to complete.) 1: Unbuffered write (Data access of subsequent processing is stalled until the write has completed.)
Page 233: Memory-Mapped Pmb Configuration
7.8.5 Memory-Mapped PMB Configuration To enable the PMB to be managed by software, its contents are allowed to be read from and written to by a P1 or P2 area program with a MOV instruction in privileged mode. The PMB address array is allocated to addresses H'F610 0000 to H'F61F FFFF in the P4 area and the PMB data array to addresses H'F710 0000 to H'F71F FFFF in the P4 area.
Page 234: Notes On Using 32-Bit Address Extended Mode
7. Memory Management Unit (MMU) Address field 1 1 1 1 0 Data field VPN: Physical page number Validity bit Entry Figure 7.28 Memory-Mapped PMB Address Array Address field 1 1 1 1 0 1 1 1 0 0 0 1 Data field PPN: Physical page number...
Page 235 Initial Bit Name Value ⎯ 30 to 8 All 0 7 to 0 All 0 ITLB The PPN field in the ITLB is extended to bits 31 to 10. UTLB The PPN field in the UTLB is extended to bits 31 to 10. The same UB bit as that in the PMB is added in each entry of the UTLB.
Page 236 7. Memory Management Unit (MMU) CCR.CB The CB bit in CCR is invalid. Whether a cacheable write for the P1 area is performed in copy- back mode or write-though mode is determined by the WT bit in the PMB. IRMCR.MT The MT bit in IRMCR is valid for a memory-mapped PMB write.
Page 237: Bit Boot Function
32-Bit Boot Function The address mode of this LSI after a power-on reset or manual reset can be switched between 29- bit address mode and 32-bit address extended mode by specifying external pins. The following changes apply when this LSI is booted up in 32-bit address extended mode. 7.9.1 Initial Entries to PMB When 32-bit address extended mode is specified by external pins, the following initial entries are...
Page 238 7. Memory Management Unit (MMU) C. If the MT bit in IRMCR is set to 0 (initial value) before accessing the memory-mapped PMB, no specific sequence is required. However, correct operation with method C may no longer be guaranteed in future SuperH- family products.
Page 239: Note On Using Ldtlb Instruction
7.10 Usage Notes 7.10.1 Note on Using LDTLB Instruction When using an LDTLB instruction instead of software to a value to the MMUCR. URC, execute 1 or 2 below. 1. In 29-bit address mode, follow A. and B. below. In 32-bit address mode, follow A. through D. below.
Page 240 7. Memory Management Unit (MMU) Notes: 1. An exception handling routine is an entire set of instructions that are executed from the address (VBR + offset) upon occurrence of an exception to the RTE for returning to the original program or to the RTE delay slot. 2.
Page 241: Section 8 Caches
This LSI has an on-chip 32-Kbyte instruction cache (IC) for instructions and an on-chip 32-Kbyte operand cache (OC) for data. Features The features of the cache are given in table 8.1. This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory.
Page 242 8. Caches This LSI has an IC way prediction scheme to reduce power consumption. In addition, memory- mapped associative writing, which is detectable as an exception, can be enabled by using the non- support detection exception register (EXPMASK). For details, see section 5, Exception Handling. Virtual address Entry selection Address array...
Page 243 Virtual address Entry selection Address array (way 0 to way 3) 19 bits Comparison Figure 8.2 Configuration of Instruction Cache (Cache size = 32 Kbytes) • Tag Stores the upper 19 bits of the 29-bit physical address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
Page 244 8. Caches • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU In a 4-way set-associative method, up to 4 items of data can be registered in the cache at each entry address.
Page 245: Register Descriptions
Register Descriptions The following registers are related to cache. Table 8.3 Register Configuration Register Name Cache control register Queue address control register 0 Queue address control register 1 On-chip memory control register Note: These P4 addresses are for the P4 area in the virtual address space. These area 7 addresses are accessed from area 7 in the physical address space by means of the TLB.
Page 246: Cache Control Register (Ccr)
8. Caches 8.2.1 Cache Control Register (CCR) CCR controls the cache operating mode, the cache write mode, and invalidation of all cache entries. CCR modifications must only be made by a program in the non-cacheable P2 area or IL memory. After CCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the cacheable area is performed.
Page 247 Initial Bit Name Value ⎯ 10, 9 All 0 ⎯ 7 to 4 All 0 Description Reserved For details on reading from or writing to these bits, see description in General Precautions on Handling of Product. IC Enable Bit Selects whether the IC is used. Note however when address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1.
Page 248: Queue Address Control Register 0 (Qacr0)
8. Caches 8.2.2 Queue Address Control Register 0 (QACR0) QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is disabled. Bit: Initial value: R/W: Bit: Initial value: R/W: Initial Bit Name Value ⎯ 31 to 5 All 0 4 to 2 AREA0...
Page 249: Queue Address Control Register 1 (Qacr1)
8.2.3 Queue Address Control Register 1 (QACR1) QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is disabled. Bit: Initial value: R/W: Bit: Initial value: R/W: Initial Bit Name Value ⎯ 31 to 5 All 0 4 to 2 AREA1...
Page 250: On-Chip Memory Control Register (Ramcr)
8. Caches 8.2.4 On-Chip Memory Control Register (RAMCR) RAMCR controls the number of ways in the IC and OC and prediction of the IC way. RAMCR modifications must only be made by a program in the non-cacheable P2 area. After RAMCR has been updated, execute one of the following three methods before an access (including an instruction fetch) to the cacheable area, the IL memory area, the OL memory area, or the U memory area is performed.
Page 251 Initial Bit Name Value IC2W OC2W ICWPD ⎯ 4 to 0 All 0 Description On-Chip Memory Protection Enable Bit For details, see section 9.4, On-Chip Memory Protective Functions. IC Two-Way Mode bit 0: IC is a four-way operation 1: IC is a two-way operation For details, see section 8.4.3, IC Two-Way Mode.
Page 252: Operand Cache Operation
8. Caches Operand Cache Operation 8.3.1 Read Operation When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is read from a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5].
Page 253: Prefetch Operation
write-back buffer is then written back to external memory. 8.3.2 Prefetch Operation When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is prefetched from a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5].
Page 254: Write Operation
8. Caches 8.3.3 Write Operation When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is written to a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5].
Page 255: Write-Back Buffer
6. Cache miss (copy-back, with write-back) The tag and data field of the cache line on the way which is selected to replace are saved in the write-back buffer. Then a data write in accordance with the access size is performed for the data field on the hit way which is indexed by virtual address bits [4:0].
Page 256: Oc Two-Way Mode
8. Caches 8.3.6 OC Two-Way Mode When the OC2W bit in RAMCR is set to 1, OC two-way mode which only uses way 0 and way 1 in the OC is entered. Thus, power consumption can be reduced. In this mode, only way 0 and way 1 are used even if a memory-mapped OC access is made.
Page 257: Instruction Cache Operation
Instruction Cache Operation 8.4.1 Read Operation When the IC is enabled (ICE = 1 in CCR) and instruction fetches are performed from a cacheable area, the instruction cache operates as follows: 1. The tag, V bit, U bit and LRU bits on each way are read from the cache line indexed by virtual address bits [12:5].
Page 258: Ic Two-Way Mode
8. Caches 3. Cache hit The LRU bits is updated to indicate the way is the latest one. 4. Cache miss Data is read into the cache line on a way which selected using the LRU bits to replace from the physical address space corresponding to the virtual address.
Page 259: Cache Operation Instruction
Cache Operation Instruction 8.5.1 Coherency between Cache and External Memory Cache Operation Instruction Coherency between cache and external memory should be assured by software. In this LSI, the following six instructions are supported for cache operations. Details of these instructions are given in section 11, Instruction Descriptions of the SH-4A Extended Functions Software Manual.
Page 260 8. Caches • FLUSH transaction When the operand cache is enabled, the FLUSH transaction checks the operand cache and if the hit line is dirty, then the data is written back to the external memory. If the transaction is not hit to the cache or the hit entry is not dirty, it is no-operation. Changes in Instruction Specifications Regarding Coherency Control Of the operand cache operating instructions, the coherency control-related specifications of OCBI, OCBP, and OCBWB have been changed from those of the SH-4A with H'20-valued VER bits in...
Page 261: Prefetch Operation
the dirty bit to 0. This operation is only executable in privileged mode, and an address error exception occurs in user mode. TLB-related exceptions do not occur. Do not execute this instruction to invalidate the memory-mapped array areas and control register areas for which Rn[31:24] is not H'F4, and their reserved areas (H'F0 to H'F3, H'F5 to H'FF).
Page 262: Memory-Mapped Cache Configuration
8. Caches Memory-Mapped Cache Configuration The IC and OC can be managed by software. The contents of IC data array can be read from or written to by a program in the P2 area by means of a MOV instruction in privileged mode. The contents of IC address array can also be read from or written to in privileged mode by a program in the P2 area or the IL memory area by means of a MOV instruction.
Page 263 In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed.
Page 264: Ic Data Array
8. Caches 8.6.2 IC Data Array The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 265 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the way is specified by bits [14:13] and the entry by bits [12:5].
Page 266: Oc Data Array
8. Caches Address field 1 1 1 1 0 1 0 0 Data field : Validity bit : Dirty bit : Association bit : Reserved bits (write value should be 0 and read value is undefined ) : Don't care Figure 8.7 Memory-Mapped OC Address Array (Cache size = 32 Kbytes) 8.6.4 OC Data Array...
Page 267: Memory-Mapped Cache Associative Write Operation
Address field 1 1 1 1 0 1 0 1 Data field : Longword specification bits : Don't care Figure 8.8 Memory-Mapped OC Data Array (Cache size = 32 Kbytes) 8.6.5 Memory-Mapped Cache Associative Write Operation Associative writing to the IC and OC address arrays may not be supported in future SuperH- family products.
Page 268: Store Queues
8. Caches Store Queues This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. 8.7.1 SQ Configuration There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 8.9. These two store queues can be set independently.
Page 269: Transfer To External Memory
8.7.3 Transfer to External Memory Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area starts a transfer from the SQs to external memory. The transfer length is fixed at 32 bytes, and the start address is always at a 32-byte boundary.
Page 270: Determination Of Sq Access Exception
8. Caches Physical address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. 8.7.4 Determination of SQ Access Exception Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is enabled or disabled.
Page 271: Notes On Using 32-Bit Address Extended Mode
Notes on Using 32-Bit Address Extended Mode In 32-bit address extended mode, the items described in this section are extended as follows. 1. The tag bits [28:10] (19 bits) in the IC and OC are extended to bits [31:10] (22 bits). 2.
Page 272 8. Caches Rev.1.00 Jan. 10, 2008 Page 242 of 1658 REJ09B0261-0100...
Page 273: Section 9 On-Chip Memory
Section 9 On-Chip Memory This LSI includes three types of memory modules for storage of instructions and data: OL memory, IL memory, and U memory. The OL memory is suitable for data storage while the IL memory is suitable for instruction storage. The U memory can store instructions and/or data. Features OL Memory •...
Page 274 9. On-Chip Memory IL Memory • Capacity The IL memory in this LSI is 8 Kbytes. • Page The IL memory is divided into two pages (pages 0 and 1). • Memory map The IL memory is allocated to the addresses shown in table 9.2 in both the virtual address space and the physical address space.
Page 275 The CPU can access the P4 area in the virtual address space (when SR.MD = 1) or on-chip memory area (when SR.MD = 0 and RAMCR.RMD = 1). Access operations involving these addresses are always non-cacheable. Table 9.3 U Memory Addresses Address Space Memory Address Virtual address...
Page 276: Register Descriptions
9. On-Chip Memory Register Descriptions The following registers are related to the on-chip memory. Table 9.4 Register Configuration Name On-chip memory control register OL memory transfer source address register 0 OL memory transfer source address register 1 OL memory transfer destination address register OL memory transfer destination address register...
Page 277: On-Chip Memory Control Register (Ramcr)
9.2.1 On-Chip Memory Control Register (RAMCR) RAMCR controls the protective functions in the on-chip memory. When updating RAMCR, please follow limitation described at section 8.2.4, On-Chip Memory Control Register (RAMCR). Bit : Initial value : R/W: Bit : Initial value : R/W: Initial Bit Name...
Page 278: Ol Memory Transfer Source Address Register 0 (Lsa0)
9. On-Chip Memory Initial Bit Name Value OC2W ICWPD 4 to 0 — All 0 9.2.2 OL memory Transfer Source Address Register 0 (LSA0) When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA0 specifies the transfer source physical address for block transfer to page 0A or 0B of the OL memory. Bit : Initial value : R/W:...
Page 279 Initial Bit Name Value 5 to 0 L0SSZ Undefined R/W Description OL memory Page 0 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L0SADR values are used as bits 15 to 10 of the transfer source physical address for block transfer to page 0A or 0B in the OL memory.
Page 280: Ol Memory Transfer Source Address Register 1 (Lsa1)
9. On-Chip Memory 9.2.3 OL memory Transfer Source Address Register 1 (LSA1) When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA1 specifies the transfer source physical address for block transfer to page 1A or 1B in the OL memory. Bit : Initial value : R/W:...
Page 281 Initial Bit Name Value 5 to 0 L1SSZ Undefined R/W Description OL memory Page 1 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L1SADR values are used as bits 15 to 10 of the transfer source physical address for block transfer to page 1A or 1B in the OL memory.
Page 282: Ol Memory Transfer Destination Address Register 0 (Lda0)
9. On-Chip Memory 9.2.4 OL memory Transfer Destination Address Register 0 (LDA0) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA0 specifies the transfer destination physical address for block transfer to page 0A or 0B of the OL memory. Bit : Initial value : R/W: Bit :...
Page 283 Initial Bit Name Value 5 to 0 L0DSZ Undefined R/W Description OL memory Page 0 Block Transfer Destination Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L0DADR values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 0A or 0B in the OL memory.
Page 284: Ol Memory Transfer Destination Address Register 1 (Lda1)
9. On-Chip Memory 9.2.5 OL memory Transfer Destination Address Register 1 (LDA1) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA1 specifies the transfer destination physical address for block transfer to page 1A or 1B in the OL memory. Bit : Initial value : R/W: Bit :...
Page 285 Initial Bit Name Value 5 to 0 L1DSZ Undefined R/W Description OL memory Page 1 Block Transfer Destination Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand addresses or L1DADR values are used as bits 15 to 10 of the transfer destination physical address for block transfer to page 1A or 1B in the OL memory.
Page 286: Operation
9. On-Chip Memory Operation 9.3.1 Instruction Fetch Access from the CPU OL Memory Instruction fetch access from the CPU is performed via the cache/RAM internal bus. This access takes more than one cycle. IL Memory Instruction fetch access from the CPU is performed directly via the instruction bus for a given virtual address.
Page 287: Access From The Superhyway Bus Master Module
U Memory Operand access from the CPU and read access from the FPU are performed via the read buffer. The read buffer is configured with two sets of one-line 32-byte buffers, and holds up to two lines which have been accessed through operand access by the CPU and accessed through read access by the FPU.
Page 288 9. On-Chip Memory When MMU is Enabled (MMUCR.AT = 1) and RAMCR.RP = 1 An address of the OL memory area is specified to the UTLB VPN field, and to the physical address of the transfer source (in the case of the PREF instruction) or the transfer destination (in the case of the OCBWB instruction) to the PPN field.
Page 289 9. On-Chip Memory When the PREF instruction is issued to the OL memory area, the physical address bits [28:10] are generated in accordance with the LSA0 or LSA1 specification. The physical address bits [9:5] are generated from the virtual address. The physical address bits [4:0] are fixed to 0. Block transfer is performed from the external memory specified by these physical addresses to the OL memory.
Page 290: On-Chip Memory Protective Functions
9. On-Chip Memory On-Chip Memory Protective Functions This LSI implements the following protective functions to the on-chip memory by using the on- chip memory access mode bit (RMD) and the on-chip memory protection enable bit (RP) in the on-chip memory control register (RAMCR). •...
Page 291: Page Conflict
Usage Notes 9.5.1 Page Conflict In the event of simultaneous access to the same page from different buses, page conflict occurs. Although each access is completed correctly, this kind of conflict tends to lower OL memory accessibility. Therefore it is advisable to provide all possible preventative software measures. For example, conflicts will not occur if each bus accesses different pages.
Page 292: Sleep Mode
9. On-Chip Memory IL Memory In order to allocate instructions in the IL memory, write an instruction to the IL memory, execute the following sequence, then branch to the rewritten instruction. • SYNCO • ICBI @Rn In this case, the target for the ICBI instruction can be any address (IL memory address may be possible) within the range where no address error exception occurs, and cache hit/miss is possible.
Page 293: Section 10 Interrupt Controller (Intc)
Section 10 Interrupt Controller (INTC) The interrupt controller (INTC) determines the priority of interrupt sources and controls the flow of interrupt requests to the CPU (SH-4A). The INTC has registers for setting the priority of each of the interrupts and processing of interrupt requests follows the priority order set in these registers by the user.
Page 294 10. Interrupt Controller (INTC) Figure 10.1 shows a block diagram of the INTC. IRQOUT Input control IRQ/IRL7 to IRQ/IRL0 IRQ/IRL7 to IRQ/IRL4 and GPIO port L4 to L1 are multiplexed GPIO Port E5 to E0 H4 to H1 L7, L6 GPIO interrupts Interrupt request Interrupt request...
Page 295 The details of the input control circuit of figure 10.1 are shown in figure 10.2. IRL/IRQ pin mode controller* IRQ/IRL7 to IRQ/IRL0 ICR0 ICR1 Notes: 1. The internal signal for IRQ is fixed when ICR0.IRLMn (n = 0, 1) is cleared to 0, and the internal signal for IRL is fixed when ICR0.IRLMn is set to 1 to prevent propagation of the state transition on the pin to inside the LSI.
Page 296: Interrupt Method
10. Interrupt Controller (INTC) 10.1.1 Interrupt Method The basic flow of exception handling for interrupts is as follows. In interrupt exception handling, the contents of the program counter (PC), status register (SR), and general register 15 (R15) are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the interrupt exception handling routine at the corresponding vector address.
Page 297: Interrupt Sources
10.1.2 Interrupt Sources Table 10.1 shows an example of the interrupt types. The INTC supports both external interrupts and on-chip peripheral module interrupts. External interrupts refer to the interrupts input through the external NMI, IRL, and IRQ pins. The IRQ and IRL interrupts are assigned to the same pins in the SH7785. The pin functions are selected to suit the system configuration.
Page 298 10. Interrupt Controller (INTC) Number of Sources Source (Max.) External interrupts interrupt On-chip peripheral TMU-ch0 1 module TMU-ch1 1 interrupts* TMU-ch2 2 H-UDI DMAC(0) 7 Rev.1.00 Jan. 10, 2008 Page 268 of 1658 REJ09B0261-0100 Priority INTEVT Inverse of values on H'320 the input pins H'C20...
Page 299 Number of Sources Source (Max.) On-chip DMAC(0) 7 module interrupts* SCIF-ch0 4 SCIF-ch1 4 DMAC(1) 7 HSPI SCIF-ch2 4 SCIF-ch3 4 SCIF-ch4 4 SCIF-ch5 4 PCIC(0) PCIC(1) PCIC(2) PCIC(3) PCIC(4) PCIC(5) Priority INTEVT Values set in INT2PRI0 to H'680 INT2PRI9 H'6A0 H'6C0 H'6E0...
Page 300 10. Interrupt Controller (INTC) Number of Sources Source (Max.) On-chip SIOF module MMCIF interrupts* GDTA TMU-ch3 1 TMU-ch4 1 TMU-ch5 1 SSI-ch0 SSI-ch1 HAC-ch0 HAC-ch1 FLCTL GPIO Legend: ITI: WDT Interval timer interrupt TUNI0 to TUNI5: TMU channels 0 to 5 underflow interrupt TICPI2: TMU channel 2 input capture interrupt DMINT0 to DMINT11:...
Page 301 BRI0, BRI1, BRI2, BRI3, BRI4, BRI5: SCIF channels 0 to 5 break interrupt TXI0, TXI1, TXI2, TXI3, TXI4, TXI5: SCIF channels 0 to 5 transmission data empty interrupt FLSTE: FLCTL error interrupt FLTEND: FLCTL error interrupt FLTRQ0: FLCTL data FIFO transfer request interrupt FLTRQ1: FLCTL control code FIFO transfer request interrupt Note:...
Page 302: Input/Output Pins
10. Interrupt Controller (INTC) 10.2 Input/Output Pins Table 10.2 shows the pin configuration. Table 10.2 INTC Pin Configuration Pin Name Function Nonmaskable interrupt input pin IRQ/IRL7 to External IRQ/IRL0 interrupt input pins IRQOUT Interrupt request output pin Rev.1.00 Jan. 10, 2008 Page 272 of 1658 REJ09B0261-0100 Description Input...
Page 303: Register Descriptions
10.3 Register Descriptions Table 10.3 shows the INTC register configuration. Table 10.4 shows the register states in each operating mode. Table 10.3 INTC Register Configuration Name Abbreviation Interrupt control register 0 ICR0 Interrupt control register 1 ICR1 Interrupt priority register INTPRI Interrupt source register INTREQ...
Page 304 10. Interrupt Controller (INTC) Name Abbreviation Interrupt source register INT2A1 (affected by the mask state) Interrupt mask register INT2MSKR Interrupt mask clear register INT2MSKCLR R/W On-chip module interrupt INT2B0 source registers INT2B1 INT2B2 INT2B3 INT2B4 INT2B5 INT2B6 INT2B7 GPIO interrupt set register INT2GPIC Notes: 1.
Page 305 Table 10.4 Register States in Each Operating Mode Name Abbreviation Interrupt control ICR0 register 0 Interrupt control ICR1 register 1 Interrupt priority INTPRI register Interrupt source INTREQ register Interrupt mask INTMSK0 register 0 Interrupt mask INTMSK1 register 1 Interrupt mask INTMSK2 register 2 Interrupt mask clear...
Page 306 10. Interrupt Controller (INTC) Name Abbreviation Interrupt priority INT2PRI7 registers INT2PRI8 INT2PRI9 Interrupt source INT2A0 register (not affected by the mask state) Interrupt source INT2A1 register (affected by the mask state) Interrupt mask INT2MSKR register Interrupt mask clear INT2MSKCR register Module interrupt INT2B0 source registers...
Page 307: External Interrupt Request Registers
10.3.1 External Interrupt Request Registers Interrupt Control Register 0 (ICR0) ICR0 is a 32-bit readable and partially writable register that sets the input signal detection mode for the external interrupt input pins and NMI pin, and indicates the level being input on the NMI pin.
Page 308 10. Interrupt Controller (INTC) Initial Name Value NMIB NMIE IRLM0 IRLM1 Rev.1.00 Jan. 10, 2008 Page 278 of 1658 REJ09B0261-0100 Description NMI Block Mode Selects whether an NMI interrupt is held until the BL bit in SR is cleared to 0 or detected immediately when the BL bit in SR of the CPU is set to 1.
Page 309 Initial Name Value LVLMODE 0 ⎯ 20 to 0 All 0 Notes: 1. When IRLM0 and IRLM1 are changed from 0 to 1, the IRL interrupt source that has been detected or held is cleared. When IRLM0 and IRLM1 are changed from 1 to 0, the IRL interrupt source that has been detected or held is not cleared.
Page 310 10. Interrupt Controller (INTC) Interrupt Control Register 1 (ICR1) ICR1 is a 32-bit readable/writable register that specifies the individual input signal detection modes for the respective external interrupt input pins IRQ/IRL7 to IRQ/IRL0. These settings are only valid when IRLM0 or IRLM1 of ICR0 is set to 1 so that IRQ/IRL3 to IRQ/IRL0 or IRQ/IRL7 to IRQ/IRL4 pins are used as individual interrupts (IRQ7 to IRQ0 interrupts) inputs.
Page 311 10. Interrupt Controller (INTC) IRQ and IRL Interrupt Requests). 2. When the IRQnS setting is changed from edge sense (IRQnS is 00 or 01) to level sense (IRQnS is 10 or 11), the IRQ interrupt source that has been edge sensed is cleared.
Page 312 10. Interrupt Controller (INTC) Interrupt Priority Register (INTPRI) INTPRI is a 32-bit readable/writable register used to set the priorities of IRQ[7:0] (as levels from 15 to 0). These settings are only valid for IRQ/IRL7 to IRQ/IRL4 or IRQ/IRL3 to IRQ/IRL0 when set up as individual IRQ interrupts (IRQ7 to IRQ0 interrupts) by setting the IRLM0 or IRLM1 bit in ICR0 to 1.
Page 313 Interrupt Source Register (INTREQ) INTREQ is a 32-bit readable and conditionally writable register that indicates which of the IRQ [n] (n = 0 to 7) interrupts is currently asserting a request for the INTC. Even if an interrupt is masked by the setting in INTPRI or INTMSK0, operation of the corresponding INTREQ bit is not affected.
Page 314 10. Interrupt Controller (INTC) Interrupt Mask Register 0 (INTMSK0) INTMSK0 is a 32-bit readable and conditionally writable register that sets masking for each of the interrupt requests IRQn (n = 0 to 7). To clear the mask setting for an interrupt, write 1 to the corresponding bit in INTMSKCLR0.
Page 315 Initial Name Value IM05 IM06 IM07 23 to 0 All 0 Description Sets masking of individual pin interrupt source on IRQ5. Sets masking of individual pin interrupt source on IRQ6. Sets masking of individual pin interrupt source on IRQ7. Reserved These bits are always read as 0.
Page 316 10. Interrupt Controller (INTC) Interrupt Mask Register 1 (INTMSK1) INTMSK1 is a 32-bit readable and conditionally writable register that sets masking for IRL interrupt requests. To clear the mask setting for the interrupt, write 1 to the corresponding bit in INTMSKCLR1.
Page 317 Interrupt Mask Register 2 (INTMSK2) INTMSK2 is a 32-bit readable and conditionally writable register that sets masking for IRL interrupt requests for input level pattern on the IRL pins. To clear the mask setting for the interrupt, write 1 to the corresponding bit in INTMSKCLR2. Writing 0 to the bits in INTMSK2 has no effect.
Page 318 10. Interrupt Controller (INTC) Initial Name Value IM010 IM009 IM008 IM007 IM006 IM005 IM004 IM003 IM002 IM001 — Rev.1.00 Jan. 10, 2008 Page 288 of 1658 REJ09B0261-0100 Description Masks the interrupt source of IRL3 to IRL0 = LHLH (H'5). Masks the interrupt source of IRL3 to IRL0 = LHHL (H'6).
Page 319 Initial Name Value IM115 IM114 IM113 IM112 IM111 IM110 IM109 IM108 IM107 IM106 IM105 IM104 IM103 Description Masks the interrupt source of IRL7 to IRL4 = LLLL (H'0). Masks the interrupt source of IRL7 to IRL4 = LLLH (H'1). Masks the interrupt source of IRL7 to IRL4 = LLHL (H'2).
Page 320 10. Interrupt Controller (INTC) Initial Name Value IM102 IM101 — Rev.1.00 Jan. 10, 2008 Page 290 of 1658 REJ09B0261-0100 Description Masks the interrupt source of IRL7 to IRL4 = HHLH (H'D). Masks the interrupt source of IRL7 to IRL4 = HHHL (H'E).
Page 321 Interrupt Mask Clear Register 0 (INTMSKCLR0) INTMSKCLR0 is a 32-bit write-only register that clears the mask settings for each of the interrupt requests IRQn (n = 0 to 7). Undefined values are read from this register. Bit: IC00 IC01 IC02 IC03 Initial value: R/W:...
Page 322 10. Interrupt Controller (INTC) Interrupt Mask Clear Register 1 (INTMSKCLR1) INTMSKCLR1 is a 32-bit write-only register that clears the mask settings for the IRL interrupt requests. Undefined values are read from this register. Bit: ⎯ ⎯ IC10 IC11 Initial value: R/W: Bit: ⎯...
Page 323 (10) Interrupt Mask Clear Register 2 (INTMSKCLR2) INTMSKCLR2 is a 32-bit write-only register that clears the mask settings for the IRL interrupt requests for each input level pattern on the IRL pins. Undefined values are read from this register. Bit: IC015 IC014 IC013 IC012...
Page 324 10. Interrupt Controller (INTC) Initial Name Value IC007 IC006 IC005 IC004 IC003 IC002 IC001 — IC115 IC114 IC113 IC112 Rev.1.00 Jan. 10, 2008 Page 294 of 1658 REJ09B0261-0100 Description Clears masking of the interrupt source of IRL3 to IRL0 = HLLL (H'8). Clears masking of the interrupt source of IRL3 to IRL0 = HLLH (H'9).
Page 325 Initial Name Value IC111 IC110 IC109 IC108 IC107 IC106 IC105 IC104 IC103 IC102 IC101 — Description Clears masking of the interrupt source of IRL7 to IRL4 = LHLL (H'4). Clears masking of the interrupt source of IRL7 to IRL4 = LHLH (H'5). Clears masking of the interrupt source of IRL7 to IRL4 = LHHL (H'6).
Page 326 10. Interrupt Controller (INTC) (11) NMI Flag Control Register (NMIFCR) NMIFCR is a 32-bit readable and conditionally writable register that has an NMI flag (NMIFL bit). The NMIFL bit is automatically set to 1 when an NMI interrupt is detected by the INTC. Writing 0 to the NMIFL bit clears it.
Page 327 Initial Name Value NMIFL 15 to 0 — All 0 Description R/(W) NMI Flag (NMI Interrupt Request Detection) Indicates whether an NMI interrupt request signal has been detected. This bit is automatically set to 1 when the INTC detects an NMI interrupt request. Write 0 to clear the bit.
Page 328: User Mode Interrupt Disable Function
10. Interrupt Controller (INTC) 10.3.2 User Mode Interrupt Disable Function User Interrupt Mask Level Setting Register (USERIMASK) USERIMASK is a 32-bit readable and conditionally writable register that sets the acceptable interrupt level. This register is allocated to the 64-Kbyte page that the other registers in the INTC are not allocated.
Page 329 Initial Name Value 31 to 24 (Code for H'00 writing) 23 to 8 — All 0 7 to 4 UIMASK 3 to 0 — All 0 Procedure for Using the User Interrupt Mask Level Register By setting the interrupt mask level in USERIMASK, the interrupts whose level is equal to or lower than the value set in USERIMASK are disabled.
Page 330: On-Chip Module Interrupt Priority Registers
10. Interrupt Controller (INTC) 3. Branch to the device driver. 4. In the device driver operating in user mode, set the UIMASK bits to mask the B-type interrupts. 5. Process more urgent interrupts in the device driver. 6. Clear the UIMASK bit to 0 and return from the processing by the device driver. 10.3.3 On-chip Module Interrupt Priority Registers Interrupt Priority Registers (INT2PRI0 to INT2PRI9)
Page 331 Table 10.5 Interrupt Request Sources and INT2PRI0 to INT2PRI9 Register 28 to 24 INT2PRI0 TMU channel 0 INT2PRI1 TMU channel 3 INT2PRI2 SCIF channel 0 INT2PRI3 SCIF channel 4 INT2PRI4 H-UDI INT2PRI5 HAC channel 0 INT2PRI6 PCIC (2) INT2PRI7 SIOF INT2PRI8 FLCTL INT2PRI9...
Page 332 10. Interrupt Controller (INTC) Interrupt Source Register (Not affected by Mask Setting) (INT2A0) INT2A0 is a 32-bit read-only register that indicates the interrupt sources of on-chip peripheral modules. Even if an interrupt is masked by the interrupt mask register, the corresponding bit in INT2A0 is set (further interrupt operation is not performed for the corresponding bit).
Page 333 Initial Value R/W Source Undefined HSPI Undefined SIOF Undefined PCIC (5) Undefined PCIC (4) Undefined PCIC (3) Undefined PCIC (2) Undefined PCIC (1) Undefined PCIC (0) Undefined channel 1 Undefined channel 0 Undefined DMAC (1) Undefined DMAC (0) Undefined H-UDI Undefined Undefined SCIF...
Page 334 10. Interrupt Controller (INTC) Initial Value R/W Source Undefined R SCIF channel 3 Undefined R SCIF channel 2 Undefined R SCIF channel 1 Undefined R SCIF channel 0 Undefined R channels 3 to 5 Undefined R channels 0 to 2 If the interrupt source in an individual module is set or cleared, the time required until the state is reflected in INT2A0 is as shown in table 10.7.
Page 335 Table 10.7 Reflection time for INT2A0 and INT2A1 when Interrupt Source Bit in Peripheral Module Is Set/Cleared Module WDT, TMU, SCIF, HSPI, SIOF, MMCIF, DU, SSI, HAC, FLCTL H-UDI, GDTA PCIC (excluding the pin input- related interrupt sources PCIINTA, PCIINTB, PCIINTC, and PCIINTD) Relation between Setting/Clearing Interrupt Source of Module and Indication by INT2A0 and INT2A1...
Page 336 10. Interrupt Controller (INTC) Module DMAC Interrupt sources DMAE0, DMAE1 Interrupt sources DMINT0 to DMINT11 Note: The registers in the modules that indicate generation of interrupt requests are as follows. WDT: WDTCSR TMU: TCR0 to TCR5 SCIF: SCFSR0 to SCFSR6, SCLSR0 to SCLSR6 HSPI: SPSR SIOF:...
Page 337 Interrupt Source Register (Affected by Mask States) (INT2A1) INT2A1 is a 32-bit read-only register that indicates the interrupt sources of on-chip peripheral modules. If an interrupt is masked by the interrupt mask register, the corresponding bit in INT2A1 is not set to 1. Use INT2A0 to check whether interrupts have been generated, regardless of the state of the interrupt mask register.
Page 338 10. Interrupt Controller (INTC) Initial Value R/W Source SIOF PCIC (5) PCIC (4) PCIC (3) PCIC (2) PCIC (1) PCIC (0) HAC channel HAC channel DMAC (1) DMAC (0) H-UDI SCIF channel 5 SCIF channel 4 SCIF channel 3 SCIF channel 2 Rev.1.00 Jan.
Page 339 Initial Value R/W Source SCIF channel 1 SCIF channel 0 channels 3 to 5 channels 0 to 2 If the interrupt source in an individual module is set or cleared, the time required until the state is reflected in INT2A1 is as shown in table 10.7. If the interrupt masking is set by INT2MSKR or the interrupt masking by INT2MSKR is cleared by INT2MSKCLR, the reflection time required for INT2A1 is guaranteed by hardware.
Page 340 10. Interrupt Controller (INTC) Interrupt Mask Register (INT2MSKR) INT2MSKR is a 32-bit readable/writable register that can mask interrupts for sources indicated in the interrupt source register. When a bit in this register is set to 1, the interrupt in the corresponding bit is not notified.
Page 341 Initial Value R/W Source R/W PCIC (4) R/W PCIC (3) R/W PCIC (2) R/W PCIC (1) R/W PCIC (0) R/W HAC channel 1 Masks the HAC channel 1 interrupt R/W HAC channel 0 Masks the HAC channel 0 interrupt R/W DMAC (1) R/W DMAC (0) R/W H-UDI R/W WDT...
Page 342 10. Interrupt Controller (INTC) Interrupt Mask Clear Register (INT2MSKCR) INT2MSKCR is a 32-bit write-only register that clears the masking set in the interrupt mask register. When the corresponding bit in this register is set to 1, the interrupt source masking is cleared.
Page 343 Initial Value R/W Source R/W PCIC (4) R/W PCIC (3) R/W PCIC (2) R/W PCIC (1) R/W PCIC (0) R/W HAC channel 1 Clears the HAC channel 1 interrupt R/W HAC channel 0 Clears the HAC channel 0 interrupt R/W DMAC (1) R/W DMAC (0) R/W H-UDI R/W WDT...
Page 344: Individual On-Chip Module Interrupt Source Registers (Int2B0 To Int2B7)
10. Interrupt Controller (INTC) 10.3.4 Individual On-Chip Module Interrupt Source Registers (INT2B0 to INT2B7) INT2B0 to INT2B7 are registers that indicate more details on each interrupt source, in addition to the interrupt source that is corresponding to each module and is indicated in the interrupt source register.
Page 345 INT2B1: Detailed Interrupt Sources for the SCIF Module Name ⎯ SCIF 31 to 24 TXI5 BRI5 RXI5 ERI5 TXI4 BRI4 RXI4 ERI4 TXI3 BRI3 RXI3 ERI3 Description Detailed Source Reserved SCIF interrupt sources are indicated. This register indicates These bits are read as 0 the SCIF interrupt sources even if and cannot be modified.
Page 346 10. Interrupt Controller (INTC) Module Name SCIF TXI2 BRI2 RXI2 ERI2 TXI1 BRI1 RXI1 ERI1 TXI0 BRI0 RXI0 ERI0 Rev.1.00 Jan. 10, 2008 Page 316 of 1658 REJ09B0261-0100 Description Detailed Source SCIF channel 2 transmit SCIF interrupt sources are FIFO data empty interrupt indicated.
Page 347 INT2B2: Detailed Interrupt Sources for the DMAC Module Name ⎯ DMAC 31 to 14 DMAE1 DMINT11 DMINT10 DMINT9 DMINT8 DMINT7 DMINT6 DMAE0 DMINT5 DMINT4 DMINT3 DMINT2 DMINT1 DMINT0 Detailed Source Description Reserved DMAC interrupt sources are indicated. This register indicates These bits are read as 0 the DMAC interrupt sources and cannot be modified.
Page 348 10. Interrupt Controller (INTC) INT2B3: Detailed Interrupt Sources for the PCIC Module Name ⎯ PCIC 31 to 10 PCIPWD0 PCIPWD1 PCIPWD2 PCIPWD3 PCIERR PCIINTD PCIINTC PCIINTB PCIINTA PCISERR Rev.1.00 Jan. 10, 2008 Page 318 of 1658 REJ09B0261-0100 Detailed Source Description Reserved PCIC interrupt sources are indicated.
Page 349 INT2B4: Detailed Interrupt Sources for the MMCIF Module Name ⎯ MMCIF 31 to 4 FRDY TRAN FSTAT INT2B5: Detailed Interrupt Sources for the FLCTL Module Name ⎯ FLCTL 31 to 4 FLTRQ1 FLTRQ0 FLTEND FLSTE Detailed Source Description Reserved MMCIF interrupt sources are indicated.
Page 350 10. Interrupt Controller (INTC) INT2B6: Detailed Interrupt Sources for the GPIO Module Name 31 to 26 ⎯ GPIO PORTL7I PORTL6I 23 to 20 ⎯ PORTH4I PORTH3I PORTH2I PORTH1I 15 to 11 ⎯ PORTE5I PORTE4I PORTE3I ⎯ 7 to 3 PORTE2I PORTE1I PORTE0I Rev.1.00 Jan.
Page 351 INT2B7: Detailed Interrupt Sources for the GDTA Module Name ⎯ GDTA 31 to 3 GAERI GAMCI GACLI Detailed Source Description Reserved GDTA interrupt sources are indicated. This register indicates These bits are read as 0 the GDTA interrupt sources even and cannot be modified.
Page 352: Gpio Interrupt Set Register (Int2Gpic)
10. Interrupt Controller (INTC) 10.3.5 GPIO Interrupt Set Register (INT2GPIC) INT2GPIC enables interrupt requests input from the pins 0 to 5 of port E, pins 1 to 4 of port H, pins 6 and 7 of port L, as GPIO interrupts. A GPIO interrupt is a low-active interrupt.
Page 353 Initial Name Value R/W PORTH3E 0 PORTH2E 0 PORTH1E 0 ⎯ 15 to All 0 PORTE5E 0 PORTE4E 0 PORTE3E 0 ⎯ 7 to All 0 PORTE2E 0 PORTE1E 0 PORTE0E 0 When a GPIO port pin is used as an interrupt pin, the GPIO notifies the INTC of the interrupt when the GPIO detects an interrupt.
Page 354: Nmi Interrupts
10. Interrupt Controller (INTC) 10.4 Interrupt Sources There are four types of interrupt sources, NMI, IRQ, IRL, and on-chip module interrupts. Each interrupt has a priority level (16 to 0). Level 16 is the highest and level 1 is the lowest. When the level is set to 0, the interrupt is masked and interrupt requests are ignored.
Page 355: Irl Interrupts
Dependence on ICR0.LVLMODE Setting For the IRQ interrupt at level detection, there are the following features according to the setting of ICR0.LVLMODE. The initial value of the ICR0 bit in LVLMODE is 0. It is recommended to set the bit to 1 before using the INTC. ICR0.LVLMODE = 0 After an IRQ interrupt request is detected at the level detection, the source is retained in INTREQ even if the pin state of IRQ interrupts is changed and the request is turned down before the request...
Page 356 10. Interrupt Controller (INTC) Interrupt requests Interrupt requests Figure 10.3 Example of IRL Interrupt Connection Table 10.12 IRL Interrupt Pins (IRL[3:0], IRL[7:4]) and Interrupt Levels IRL3 or IRL2 or IRL1 or IRL7 IRL6 IRL5 High High High High High High High High High...
Page 357: On-Chip Peripheral Module Interrupts
The priority of IRL interrupts should be retained from when an interrupt is accepted to when interrupt handling starts. The level can be changed to a higher level. When the INTMU bit in CPUOPM is set to 1, the interrupt mask level (IMASK) bit in SR is automatically set to the level of the accepted interrupt.
Page 358: Priority Of On-Chip Peripheral Module Interrupts
10. Interrupt Controller (INTC) An on-chip peripheral module interrupt source flag or an interrupt enable flag should be updated when the BL bit in SR is set to 1 or when the corresponding interrupt is not generated by the setting of interrupt masking occurs. To prevent the acceptance of incorrect interrupts by the updated interrupt source, read from the on-chip peripheral module register that has the corresponding flag.
Page 359: Interrupt Exception Handling And Priority
An interrupt request is masked if priority level H'01 is set. INTC Priority level: H'01 Priority level: H'0 (interrupt is masked) Priority level H'01 becomes H'00 after the least significant bit is truncated, so the CPU is not notified of the corresponding interrupt.
Page 360 10. Interrupt Controller (INTC) Table 10.13 Interrupt Exception Handling and Priority Interrupt Source ⎯ IRL[3:0] = LLLL (H'0) L: Low IRL[7:4] = LLLL (H'0) level input H: High IRL[3:0] = LLLH (H'1) level input IRL[7:4] = LLLH (H'1) (See table IRL[3:0] = LLHL (H'2) 10.11) IRL[7:4] = LLHL (H'2)
Page 361 Interrupt Source IRL[3:0] = HLLL (H'8) L: Low IRL[7:4] = HLLL (H'8) level input H: High IRL[3:0] = HLLH (H'9) level input IRL[7:4] = HLLH (H'9) (See table 10.11) IRL [3:0] = HLHL (H'A) H'340 IRL[7:4] = HLHL (H'A) IRL[3:0] = HLHH (H'B) H'360 IRL[7:4] = HLHH (H'B) H'C60 IRL[3:0] = HHLL (H'C) IRL[7:4] = HHLL (H'C)
Page 362 10. Interrupt Controller (INTC) Interrupt Source IRQ[0] IRQ[1] IRQ[2] IRQ[3] IRQ[4] IRQ[5] IRQ[6] IRQ[7] ITI* TMU-ch0 TUNI0* TMU-ch1 TUNI1* TMU-ch2 TUNI2* TICPI2* H-UDI H-UDII Rev.1.00 Jan. 10, 2008 Page 332 of 1658 REJ09B0261-0100 INTEVT Interrupt Mask/Clear Code Priority Register & Bit H'240 INTPRI INTMSK0[31]...
Page 363 INTEVT Interrupt Source Code DMAC(0) DMINT0* H'620 DMINT1* H'640 DMINT2* H'660 DMINT3* H'680 DMINT4* H'6A0 DMINT5* H'6C0 DMAE (ch0 to ch5)* H'6E0 SCIF-ch0 ERI0* H'700 RXI0* H'720 BRI0* H'740 TXI0* H'760 SCIF-ch1 ERI1* H'780 RXI1* H'7A0 BRI1* H'7C0 TXI1* H'7E0 DMAC(1) DMINT6* H'880 DMINT7*...
Page 364 10. Interrupt Controller (INTC) INTEVT Interrupt Source Code SCIF-ch2 ERI2* H'980 RXI2* BRI2* TXI2* SCIF-ch3 ERI3* H'9A0 RXI3* BRI3* TXI3* SCIF-ch4 ERI4* H'9C0 RXI4* BRI4* TXI4* SCIF-ch5 ERI5* H'9E0 RXI5* BRI5* TXI5* PCIC(0) PCISERR H'A00 PCIC(1) PCIINTA H'A20 PCIC(2) PCIINTB H'A40 PCIC(3) PCIINTC...
Page 365 INTEVT Interrupt Source Code PCIC(5) PCIERR H'AA0 PCIPWD3 H'AC0 PCIPWD2 H'AC0 PCIPWD1 H'AC0 PCIPWD0 H'AE0 SIOF SIOFI H'CE0 MMCIF FSTAT H'D00 TRAN H'D20 H'D40 FRDY H'D60 H'D80 GDTA GACLI H'DA0 GAMCI H'DC0 GAERI H'DE0 TMU-ch3 TUNI3* H'E00 TMU-ch4 TUNI4* H'E20 TMU-ch5 TUNI5* H'E40...
Page 366 10. Interrupt Controller (INTC) Interrupt Source HAC-ch1 HACI1 FLCTL FLSTE* FLTEND* FLTRQ0* FLTRQ1* GPIO GPIOI0 (Port E0) GPIOI0 (Port E1) GPIOI0 (Port E2) GPIOI1 (Port E3) GPIOI1 (Port E4) GPIOI1 (Port E5) GPIOI2 (Port H1) GPIOI2 (Port H2) GPIOI2 (Port H3) GPIOI2 (Port H4) GPIOI3 (Port L6) GPIOI3 (Port L7)
Page 367: Interrupt Sequence
10.5 Operation 10.5.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 10.4 shows a flowchart of the operations. 1. Interrupt request sources send interrupt request signals to the INTC. 2. The INTC selects the interrupt with the highest priority among the interrupts that have been sent, according to the priority set in INTPRI and INT2PRI0 to INT2PRI9.
Page 368 10. Interrupt Controller (INTC) Program execution state ICR0.MAI = 1? Interrupt generated? SR.BL = 0 or sleep mode? ICR0.NMIB = 1? NMI? CPUOPM.INTMU = 1? Set SR.IMASK to accepted interrupt level Set interrupt source code in INTEVT Save SR in SSR; save PC in SPC;...
Page 369: Multiple Interrupts
10.5.2 Multiple Interrupts To handle multiple interrupts, the procedure for the interrupt handling routine should be as follows. 1. To identify the interrupt source, set the value of INTEVT to an offset and branch it to the interrupt handling routine for each interrupt source. 2.
Page 370: Interrupt Response Time
10. Interrupt Controller (INTC) 10.6 Interrupt Response Time Table 10.14 shows response time. The response time is the interval from generation of an interrupt request until the start of interrupt exception handling and until fetching of the first instruction of the exception handling routine.
Page 371 Table 10.15 shows response time. The response time is from the interrupt exception handling to the start of fetching the first instruction in exception handling routine. In this case, suppose that the setting values of the following registers that enable or disable interrupt, INTMSK0, INTMSK1, INTMSK2, INT2MSKR, and INT2GPIC, are changed from the interrupt disable state to the interrupt enable state.
Page 372 10. Interrupt Controller (INTC) Table 10.16 shows response time. The response time is the time until when the interrupt request signal from the INTC to the CPU is negated. In this case, suppose that the setting values of the following registers, INTMSK0, INTMSK1, INTMSK2, INT2MSKR, and INT2GPIC, are changed from the interrupt enable state to the interrupt disable state.
Page 373: Example Of Handing Routine Of Irl Interrupts And Level Detection Irq Interrupts When Icr0.Lvlmode = 0
10.7 Usage Notes 10.7.1 Example of Handing Routine of IRL Interrupts and Level Detection IRQ Interrupts when ICR0.LVLMODE = 0 When ICR0.LVLMODE is 0, IRL interrupt requests and level detection IRQ interrupt requests that the INTC retains should be cleared in the interrupt handling routine because the CPU detects after accepting interrupts.
Page 374: Notes On Setting Irq/Irl[7:0] Pin Function
10. Interrupt Controller (INTC) 10.7.2 Notes on Setting IRQ/IRL[7:0] Pin Function When the IRQ/IRL[7:0] pin functions are switched, the INTC may retain an incorrectly detected interrupt request. Therefore, mask the IRL and IRQ interrupt requests before switching the IRQ/IRL[7:0] pin functions. Table 10.17 Switching Sequence of IRQ/IRL[7:0] Pin Function Sequence Item IRL interrupt request and IRQ interrupt...
Page 375: Clearing Irq And Irl Interrupt Requests
10.7.3 Clearing IRQ and IRL Interrupt Requests To clear the interrupt request retained in the INTC, follow the procedure below. Clearing Interrupt Request Independent from ICR0.LVLMODE Setting ⎯ Clearing IRQ interrupt requests at edge detection To clear the interrupt requests IRQ7 to IRQ0 setting edge detection, read the IR7 to IR0 bits corresponding to INTREQ as 1 and write 0 to the bits.
Page 376 10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 346 of 1658 REJ09B0261-0100...
Page 377: Section 11 Local Bus State Controller (Lbsc)
Section 11 Local Bus State Controller (LBSC) The local bus state controller (LBSC) divides the external memory space and outputs control signals according to the specification of each memory and bus interface. The LBSC function enables connection of the SRAM or ROM, etc. to this LSI. The LBSC also supports the PCMCIA interface protocol, which implements simple system design and high-speed data transfers in a compact system.
Page 378 11. Local Bus State Controller (LBSC) • MPX interface ⎯ Address/data multiplexing Connectable area: 0 to 6 Settable bus width: 64 and 32 bits • Byte control SRAM interface ⎯ SRAM interface with byte control Connectable area: 1 and 4 Settable bus width: 64, 32 and 16 bits •...
Page 379 Figure 11.1 shows a block diagram of the LBSC. CS0 to CS6 CE2A to CE2B WE7 to WE0 IORD, IOWR IOIS16 Legend: CSnWCR: CSn wait control register (n = 0 to 6) CSnBCR: CSn bus control register (n = 0 to 6) BCR: CSnPCR: CSn PCMCIA control register (n = 5 and 6) CSnWCR...
Page 380: Input/Output Pins
11. Local Bus State Controller (LBSC) 11.2 Input/Output Pins Table 11.1 shows the LBSC pin configuration. Table 11.1 Pin Configuration Pin Name Function A25 to A0 Address Bus D63 to D0 Data Bus Bus Cycle Start O CS6 to CS0 Chip Select 6 to Read/Write RD/FRAME...
Page 381 Pin Name Function WE0/REG Data Enable 0 Data Enable 1 WE2/IORD Data Enable 2 WE3/IOWR Data Enable 3 Data Enable 4 Data Enable 5 Data Enable 6 Data Enable 7 Ready IOIS16 16-Bit I/O BREQ Bus Release Request 11. Local Bus State Controller (LBSC) Description Write strobe signal for D7 to D0 in SRAM interface setting...
Page 382 11. Local Bus State Controller (LBSC) Pin Name Function BACK Bus Request Acknowledge CE2A* PCMCIA Card CE2B* Select MODE5, Bus Width and MODE6, Memory Type MODE7 for Area 0 MODE8 Endian Switching MODE9 Master/Slave Switching Rev.1.00 Jan. 10, 2008 Page 352 of 1658 REJ09B0261-0100 Description Bus request acknowledge signal...
Page 383 Pin Name Function MODE11, Bus Mode MODE12 Switching DACK0* DMAC0 Acknowledge Signal DACK1* DMAC1 Acknowledge Signal DACK2* DMAC2 Acknowledge Signal DACK3* DMAC3 Acknowledge Signal Notes: 1. CE2A is an output pin when the TYPE bits in CS5BCR are set to B'100. 2.
Page 384: Overview Of Areas
11. Local Bus State Controller (LBSC) 11.3 Overview of Areas 11.3.1 Space Divisions The LSI has a 32-bit virtual address space as the architecture. The virtual address space is divided into five areas according to the upper address value. Also, the memory space of the local bus has a 29-bit address space, and it is divided into eight areas.
Page 385 Table 11.2 LBSC External Memory Space Map External Area addresses Size H'0000 0000 to 64 Mbytes H'03FF FFFF H'0400 0000 to 64 Mbytes H'07FF FFFF H'0800 0000 to 64 Mbytes H'0BFF FFFF H'0C00 0000 to 64 Mbytes H'0FFF FFFF H'1000 0000 to 64 Mbytes H'13FF FFFF H'1400 0000 to...
Page 386 11. Local Bus State Controller (LBSC) External Area addresses Size H'1800 0000 to 64 Mbytes H'1BFF FFFF 64 Mbytes ⎯ H'1C00 0000 to H'1FFF FFFF Notes: 1. The memory bus width is specified by the external pins. 2. The memory bus width is specified by the register. 3.
Page 387: Memory Bus Width
11.3.2 Memory Bus Width The memory bus width of the LBSC can be set independently for each area. In area 0, a bus width of 8, 16, 32, or 64 bits is selected according to the external pin settings at a power-on reset by the PRESET pin.
Page 388: Pcmcia Support
11. Local Bus State Controller (LBSC) 11.3.3 PCMCIA Support This LSI supports the PCMCIA interface specifications for areas 5 and 6 in the external memory space. The IC memory card interface and I/O card interface specified in JEIDA specifications version 4.2 (PCMCIA2.1) are supported.
Page 389 Table 11.4 PCMCIA Support Interface IC Memory Card Interface Signal Name Function Ground Data Data Data Data Data Card enable Address Output enable Address Address Address Address Address Write enable READY Ready Operating power supply VPP1 Programming (VPP) power supply Address Address Address...
Page 390 11. Local Bus State Controller (LBSC) IC Memory Card Interface Signal Function Name Data Data Data Write protect Ground Ground Card detection Data Data Data Data Data Card enable RFSH Refresh request RFSH (VS1) RSRVD Reserved RSRVD Reserved Address Address Address Address Address...
Page 391 IC Memory Card Interface Signal Function Name RSRVD Reserved Attribute memory space select BVD2 Battery voltage detection BVD1 Battery voltage detection Data Data Data Card detection Ground Notes: 1. WP is not supported. 2. Be careful of the polarity. I/O means input/output in PCMCIA card. The polarity of the PCMCIA card interface indicates that on the card side, and the polarity of the corresponding pin of the SH7785 indicates that on this LSI side.
Page 392: Register Descriptions
11. Local Bus State Controller (LBSC) 11.4 Register Descriptions Table 11.5 shows registers for the LBSC. These registers control the interface with each memory, wait state, etc. Table 11.5 Register Configuration (1) Register Name Memory Address Map Select Register Bus Control Register CS0 Bus Control Register CS1 Bus Control Register CS2 Bus Control Register...
Page 393 Table 11.5 Register Configuration (2) Register Name Abbrev. Memory Address Map MMSELR Select Register Bus Control Register CS0 Bus Control Register CS0BCR CS1 Bus Control Register CS1BCR CS2 Bus Control Register CS2BCR CS3 Bus Control Register CS3BCR CS4 Bus Control Register CS4BCR CS5 Bus Control Register CS5BCR CS6 Bus Control Register CS6BCR CS0 Wait Control...
Page 394: Memory Address Map Select Register (Mmselr)
11. Local Bus State Controller (LBSC) 11.4.1 Memory Address Map Select Register (MMSELR) MMSELR is a 32-bit register that selects memory address maps for areas 2 to 5. This register should be accessed at the address H'FC40 0020 in longword. To prevent incorrect writing, writing is accepted only when the upper 16-bit data is H'A5A5.
Page 395 Initial Bit Name Value 2 to 0 AREASEL This register should be written by the CPU. Before writing to this register, set that no access will be generated from the DMAC, GDTA, DU or PCIC and execute the SYNCO instruction immediately before the MOV instruction to write this register, etc.
Page 396 11. Local Bus State Controller (LBSC) Example: ----------------------------------------------------------------------- MOV.L #H'FC400020, R0 MOV.L #MMSELR_DATA, R1 SYNCO MOV.L R1, @R0 MOV.L @R0, R2 MOV.L @R0, R2 SYNCO ----------------------------------------------------------------------- The instruction to write to this register should be allocated to the uncacheable area P2 and to the area that is not affected by writing to this register.
Page 397: Bus Control Register (Bcr)
11.4.2 Bus Control Register (BCR) BCR is a 32-bit readable/writable register that specifies the function, bus cycle state, etc for each area. BCR is initialized to H'0000 0000 in big endian mode and to H'8000 0000 in little endian mode by a power-on reset, however, not initialized by a manual reset. BIt: —...
Page 398 11. Local Bus State Controller (LBSC) Initial Bit Name Value DPUP ⎯ OPUP 23 to 20 DACKBST All 0 [3:0] Rev.1.00 Jan. 10, 2008 Page 368 of 1658 REJ09B0261-0100 Description Data Pin Pull-Up Resistor Control Specifies the pull-up resistor state of the data pins (D63 to D0).
Page 399 Initial Bit Name Value ⎯ 19, 18 All 0 BREQEN DMABST ⎯ HIZCNT ⎯ 13 to 7 All 0 Description Reserved These bits are always read as 0. The write value should always be 0. BREQ Enable Specifies whether an external request can be accepted or not.
Page 400 11. Local Bus State Controller (LBSC) Initial Bit Name Value 6 to 0 ASYNC[6:0] All 0 When asynchronous input is set (ASYNCn = 1), the sampling timing is one cycle before the synchronous input setting (see figure 11.4). The timing shown in this section, other sections and section 32 Electrical Characteristics is that with synchronous input setting (ASYNCn = 0).
Page 401: Csn Bus Control Register (Csnbcr)
11.4.3 CSn Bus Control Register (CSnBCR) CSnBCR are 32-bit readable/writable registers that specify the bus width for area n (n = 0 to 6), idle mode between cycles, burst ROM setting and memory types. Some types of memory continue to drive the data bus immediately after the read signal is turned off.
Page 402 11. Local Bus State Controller (LBSC) Initial Bit Name Value 30 to 28 IWW ⎯ 26 to 24 IWRWD Rev.1.00 Jan. 10, 2008 Page 372 of 1658 REJ09B0261-0100 Description Idle Cycles between Write-Read/Write-Write These bits specify the number of idle cycles to be inserted after the access of the memory connected to the space.
Page 403 Initial Bit Name Value ⎯ 22 to 20 IWRWS ⎯ 18 to 16 IWRRD Description Reserved This bit is always read as 0. The write value should always be 0. Idle Cycles between Read-Write in Same Space These bits specify the number of idle cycles to be inserted after the access to the memory connected to the space.
Page 404 11. Local Bus State Controller (LBSC) Initial Bit Name Value ⎯ 14 to 12 IWRRS 11, 10 Rev.1.00 Jan. 10, 2008 Page 374 of 1658 REJ09B0261-0100 Description Reserved This bit is always read as 0. The write value should always be 0. Idle Cycles between Read-Read in Same Space These bits specify the number of idle cycles to be inserted after the memory connected to the space is...
Page 405 Initial Bit Name Value 9, 8 RDSPL Description R/W* Bus Width In CS0BCR, the external pins (MODE5 and MODE6) to specify the bus size are sampled at a power-on reset. When using the MPX interface, set these bits to 00 or 11.
Page 406 11. Local Bus State Controller (LBSC) Initial Bit Name Value 6 to 4 2 to 0 TYPE Rev.1.00 Jan. 10, 2008 Page 376 of 1658 REJ09B0261-0100 Description Burst Pitch When the burst ROM interface is used, these bits specify the number of wait cycles to be inserted after the second data access in a burst transfer.
Page 407: Csn Wait Control Register (Csnwcr)
11.4.4 CSn Wait Control Register (CSnWCR) CSnWCR (n = 0 to 6) are 32-bit readable/writable registers that specify the number of wait cycles to be inserted for areas 0 to 6, the number of wait cycles to be inserted preceding the first data in burst memory access, the address setup time, which is the time from the point at which the output of address for access is started until assertion of the read/write strobe signal, and the number of cycles to be inserted as the data hold time from negation of the write strobe signal.
Page 408 11. Local Bus State Controller (LBSC) Initial Bit Name Value ⎯ 26 to 24 ADH ⎯ 22 to 20 RDS Rev.1.00 Jan. 10, 2008 Page 378 of 1658 REJ09B0261-0100 Description Reserved This bit is always read as 0. The write value should always be 0.
Page 409 Initial Bit Name Value ⎯ 18 to 16 RDH ⎯ 14 to 12 WTS Description Reserved This bit is always read as 0. The write value should always be 0. RD Hold Cycle (RD Negation–CSn Negation Delay Cycle) These bits specify the number of cycles to be inserted as the time from RD negation to CSn negation.
Page 410 11. Local Bus State Controller (LBSC) Initial Bit Name Value ⎯ 10 to 8 ⎯ 6 to 4 Rev.1.00 Jan. 10, 2008 Page 380 of 1658 REJ09B0261-0100 Description Reserved This bit is always read as 0. The write value should always be 0.
Page 411 Initial Bit Name Value 3 to 0 IW[3:0] 1111 Description Insert Wait Cycle These bits specify the number of wait cycles to be inserted. The wait cycles are as follows when the SRAM interface, byte control SRAM interface, burst ROM interface (first data cycle only), or PCMCIA interface is selected.
Page 412: Csn Pcmcia Control Register (Csnpcr)
11. Local Bus State Controller (LBSC) 11.4.5 CSn PCMCIA Control Register (CSnPCR) CSnPCR is a 32-bit readable/writable register that specifies the timing for the PCMCIA interface connected to area n (CSnPCR, n = 5 or 6), the space property, and the assert/negate timing for the OE and WE signals.
Page 413 Initial Bit Name Value ⎯ 26 to 24 SAB 23, 22 PCWA 21, 20 PCWB Description Reserved This bit is always read as 0. The write value should always be 0. Space Property B These bits specify the space property of PCMCIA connected to the second half of the area.
Page 414 11. Local Bus State Controller (LBSC) Initial Bit Name Value 19 to 16 PCIW 0000 ⎯ Rev.1.00 Jan. 10, 2008 Page 384 of 1658 REJ09B0261-0100 Description PCMCIA Insert Wait Cycle B These bits specify the number of wait cycles to be inserted.
Page 415 Initial Bit Name Value 14 to 12 TEDA ⎯ 10 to 8 TEDB ⎯ Description OE/WE Assert Delay A These bits set the delay time from address output to OE/WE assertion when the first half area is accessed with the connected PCMCIA interface. 000: No wait cycle inserted 001: 1 wait cycle inserted 010: 2 wait cycles inserted...
Page 416 11. Local Bus State Controller (LBSC) Initial Bit Name Value 6 to 4 TEHA ⎯ 2 to 0 TEHB Rev.1.00 Jan. 10, 2008 Page 386 of 1658 REJ09B0261-0100 Description OE/WE Negation-Address Delay A These bits set the delay time from OE/WE negation to address hold when the first half area is accessed with the connected PCMCIA interface.
Page 417: Endian/Access Size And Data Alignment
11.5 Operation 11.5.1 Endian/Access Size and Data Alignment This LSI supports both big and little endian modes. In big endian mode, the most significant byte (MSByte) in a string of byte data is stored at address 0, and in little endian mode, the least significant byte (LSByte) in a string of byte data is stored at address 0.
Page 418 11. Local Bus State Controller (LBSC) Table 11.6 64-Bit External Device/Big Endian Access and Data Alignment (1) Operation Access D63 to Size Address No. Data 7 to 0 ⎯ Byte 8n + 1 ⎯ 8n + 2 ⎯ 8n + 3 ⎯...
Page 419 Table 11.7 64-Bit External Device/Big Endian Access and Data Alignment (2) Operation Access No. WE7 Size Address Asserted ⎯ Byte 8n + 1 ⎯ 8n + 2 ⎯ 8n + 3 ⎯ 8n + 4 ⎯ 8n + 5 ⎯ 8n + 6 ⎯...
Page 420 11. Local Bus State Controller (LBSC) Table 11.8 32-Bit External Device/Big-Endian Access and Data Alignment Operation Access D31 to Size Address Byte Data 7 to 0 ⎯ 4n + 1 ⎯ 4n + 2 ⎯ 4n + 3 Word Data 15 to 8 ⎯...
Page 421 Table 11.9 16-Bit External Device/Big-Endian Access and Data Alignment Operation Access D31 to Size Address ⎯ Byte ⎯ 2n + 1 ⎯ Word ⎯ Longword ⎯ 4n + 2 ⎯ 32 Bytes ⎯ 8n + 2 ⎯ 8n + 4 …...
Page 422 11. Local Bus State Controller (LBSC) Table 11.10 8-Bit External Device/Big-Endian Access and Data Alignment Operation Access D31 to Size Address ⎯ Byte ⎯ Word ⎯ 2n + 1 ⎯ Longword ⎯ 4n + 1 ⎯ 4n + 2 ⎯ 4n + 3 ⎯...
Page 423 Table 11.11 64-Bit External Device/Little Endian Access and Data Alignment (1) Operation Access D63 to Size Address No. ⎯ Byte 8n + 1 ⎯ 8n + 2 ⎯ 8n + 3 ⎯ 8n + 4 ⎯ 8n + 5 ⎯ 8n + 6 ⎯...
Page 424 11. Local Bus State Controller (LBSC) Table 11.12 64-Bit External Device/Little Endian Access and Data Alignment (2) Operation Access Address No. WE7 Size ⎯ Byte 8n + 1 ⎯ 8n + 2 ⎯ 8n + 3 ⎯ 8n + 4 ⎯...
Page 425 Table 11.13 32-Bit External Device/Little-Endian Access and Data Alignment Operation Access D31 to Size Address ⎯ Byte ⎯ 4n + 1 ⎯ 4n + 2 4n + 3 Data 7 to 0 ⎯ Word 4n + 2 Data 15 to 8 Longword Data 31 to 24...
Page 426 11. Local Bus State Controller (LBSC) Table 11.14 16-Bit External Device/Little-Endian Access and Data Alignment Operation Access D31 to Size Address ⎯ Byte ⎯ 2n + 1 ⎯ Word ⎯ Longword ⎯ 4n + 2 ⎯ 32 Bytes* ⎯ 8n + 2 ⎯...
Page 427 Table 11.15 8-Bit External Device/Little-Endian Access and Data Alignment Operation Access D31 to Size Address ⎯ Byte ⎯ Word ⎯ 2n + 1 ⎯ Longword ⎯ 4n + 1 ⎯ 4n + 2 ⎯ 4n + 3 ⎯ 32 Bytes* 8n + 1 ⎯...
Page 428: Areas
11. Local Bus State Controller (LBSC) 11.5.2 Areas Area 0 Area 0 is an area where bits 28 to 26 in the local bus address are 000. The interface that can be set for this area is the SRAM, burst ROM or MPX interface. A bus width of 8, 16, 32, or 64 bits is selectable by external pins MODE6 and MODE5 at a power- on reset.
Page 429 11. Local Bus State Controller (LBSC) For the number of bus cycles, 0 to 25 wait cycles to be inserted can be selected by CS1WCR. When the burst ROM interface is used, the number of a burst pitch is selectable in the range from 0 to 7 with the BW bits in CS1BCR.
Page 430 11. Local Bus State Controller (LBSC) Area 3 Area 3 is an area where bits 28 to 26 in the local bus address are 011. The interface that can be set for this area is the SRAM, MPX, or burst ROM interface. A bus width of 8, 16, 32, or 64 bits is selectable by bits SZ in CS3BCR.
Page 431 11. Local Bus State Controller (LBSC) For the number of bus cycles, 0 to 25 wait cycles inserted can be selected by CS4WCR. When the burst ROM interface is used, the number of a burst pitch is selectable in the range from 0 to 7 with the BW bits in CS4BCR.
Page 432 11. Local Bus State Controller (LBSC) CS5PCR. In addition, the number of wait cycles can be specified in the range from 0 to 50 cycles by the PCWA/B bit. The number of wait cycles specified by CS5PCR is added to the value specified by bits IW3 to IW0 in CS5WCR or bits PCIW3 to PCIW0 in CS5PCR.
Page 433: Sram Interface
11. Local Bus State Controller (LBSC) 11.5.3 SRAM interface Basic Timing The strobe signals for the SRAM interface in this LSI are output primarily based on the SRAM connection. Figure 11.5 shows the basic timing of the SRAM interface. Normal access without wait cycles is completed in two cycles.
Page 434 11. Local Bus State Controller (LBSC) CLKOUT A25 to A0 D31 to D0 (In reading) D31 to D0 (In writing) DACKn In this example, DACKn is high-active. Figure 11.5 Basic Timing of SRAM Interface Rev.1.00 Jan. 10, 2008 Page 404 of 1658 REJ09B0261-0100...
Page 435 Figures 11.6 to 11.8 show examples of connections to SRAM with 32-, 16- and 8-bit data width, respectively. SH7785 Figure 11.6 Example of 32-Bit Data Width SRAM Connection 11. Local Bus State Controller (LBSC) 128K × 8 bits SRAM I/O7 I/O0 I/O7 I/O0...
Page 436 11. Local Bus State Controller (LBSC) SH7785 Figure 11.7 Example of 16-Bit Data Width SRAM Connection Rev.1.00 Jan. 10, 2008 Page 406 of 1658 REJ09B0261-0100 128K × 8 bits SRAM I/O7 I/O0 I/O7 I/O0...
Page 437 SH7785 Figure 11.8 Example of 8-Bit Data Width SRAM Connection Wait Cycle Control Wait cycle insertion for the SRAM interface can be controlled by CSnWCR. If the IW bits in CSnWCR are set to a value other than 0, a software wait is inserted in accordance with the wait control bits.
Page 438 11. Local Bus State Controller (LBSC) CLKOUT A25 to A0 D31 to D0 (In reading) D31 to D0 (In writing) DACKn : Sampling Timing In this example, DACKn is active-high. (The circle indicates the sampling timing.) Figure 11.9 SRAM Interface Wait Timing (Software Wait Only) Rev.1.00 Jan.
Page 439 When software wait insertion is specified by CSnWCR, the external wait input signal, RDY, is also sampled. The RDY signal sampling timing is shown in figure 11.10, where a single wait cycle is specified as a software wait. The RDY signal is sampled at the transition from the Tw state to the T2 state.
Page 440 11. Local Bus State Controller (LBSC) Read-Strobe/Write-Strobe Timing When the SRAM interface is used, the strobe signal negation timing in reading can be specified with the RDSPL bit in CSnBCR. For details of settings, see section 11.4.3, CSn Bus Control Register (CSnBCR).
Page 441 TAS1 CLKOUT A25-A0 D31-D0 TS1: CSn assertion - RD assertion delay cycle CSnWCR RDS = 001 TAS1: Address setup wait CSnWCR ADS=001 CLKOUT D31-D0 (ADS=000) D31-D0 (ADS=001 to 111) TS1: CSn assertion - WEn assertion delay cycle CSnWCR WTS = 001 TAS1: Address setup wait CSnWCR BSH=001 Notes: 1.
Page 442: Burst Rom Interface
11. Local Bus State Controller (LBSC) 11.5.4 Burst ROM Interface When the TYPE bit in CSnBCR is set to 010, a burst ROM can be connected to areas 0 to 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The burst access timing of burst ROM is shown in figure 11.12.
Page 443 11. Local Bus State Controller (LBSC) CLKOUT A25 to A5 A4 to A0 D31 to D0 (In reading) Figure 11.12 Burst ROM Basic Timing Rev.1.00 Jan. 10, 2008 Page 413 of 1658 REJ09B0261-0100...
Page 444 11. Local Bus State Controller (LBSC) CLKOUT A25 to A5 A4 to A0 D31 to D0 (In reading) Figure 11.13 Burst ROM Wait Timing Rev.1.00 Jan. 10, 2008 Page 414 of 1658 REJ09B0261-0100...
Page 445 TAS1 CLKOUT A25 to A5 A4 to A0 D31 to D0 (In reading) DACKn * Notes: 1. In this example, DACKn is active-high. When RDSPL in CSnBCR is set to 1. Figure 11.14 Burst ROM Wait Timing Rev.1.00 Jan. 10, 2008 Page 415 of 1658 11.
Page 446: Pcmcia Interface
11. Local Bus State Controller (LBSC) 11.5.5 PCMCIA Interface By setting the TYPE bits in CS5BCR and CS6BCR, the bus interface for the external space areas 5 and 6 can be set to the IC memory card interface or I/O card interface, which is stipulated in JEIDA specification version 4.2 (PCMCIA 2.1).
Page 447 complement mode. To access the Device Control Register and Alternate Status Register, use a CPU byte access (do not use a DMA transfer), and to access the Data Register, use the CPU word access (do not use a DMA transfer). To access the Data Port use a DMA transfer. When a CPU byte access is executed, CE1x is negated and CE2x is asserted (x = A, B).
Page 448 11. Local Bus State Controller (LBSC) Table 11.16 Relationship between Address and CE when Using PCMCIA Interface Read/ Access Odd/ Bus (Bits) Write (bits)* Even Read Even Even Even Write Even Even Even Read Even Even Write Even Even Dynamic Read Even Bus Sizing*...
Page 449 Read/ Access Odd/ Bus (Bits) Write (bits)* Even Dynamic Write Even Sizing* Even Even Read Even comple- (does ment mode Even output DACK) Write Even (does Even output DACK) Read Even (outputs DACK) Even Write Even (outputs DACK) Even Legend: ×...
Page 450 11. Local Bus State Controller (LBSC) A25 to A0 D15 to D0 CE1B/(CS6) CE1A/(CS5) CE2B CE2A SH7785 ICIORD ICIOWR IOIS16 Figure 11.16 Example of PCMCIA Interface Rev.1.00 Jan. 10, 2008 Page 420 of 1658 REJ09B0261-0100 A25 to A0 D7 to D0 D15 to D0 D15 to D8 PC card...
Page 451 Memory Card Interface Basic Timing Figure 11.17 shows the basic timing for the PCMCIA memory card interface, and figure 11.18 shows the wait timing for the PCMCIA memory card interface. CLKOUT A25 to A0 CExx (In reading) D15 to D0 (In reading) (In writing) D15 to D0...
Page 452 11. Local Bus State Controller (LBSC) Tpcm0 CLKOUT A25 to A0 CExx (In reading) D15 to D0 (In reading) (In writing) D15 to D0 (In writing) DACKn In this example, DACKn is active-high. Figure 11.18 Wait Timing for PCMCIA Memory Card Interface Rev.1.00 Jan.
Page 453 11. Local Bus State Controller (LBSC) I/O Card Interface Timing Figures 11.19 and 11.20 show the timing for the PCMCIA I/O card interface. When a PCMCIA card is accessed as the I/O card interface, dynamic sizing with the I/O bus width can be performed using the IOIS16 pin.
Page 454 11. Local Bus State Controller (LBSC) CLKOUT A25 to A0 CExx ICIORD (In reading) D15 to D0 (In reading) ICIOWR (In writing) D15 to D0 (In writing) DACKn In this example, DACKn is active-high. Figure 11.19 Basic Timing for PCMCIA I/O Card Interface Rev.1.00 Jan.
Page 455 11. Local Bus State Controller (LBSC) Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CLKOUT A25 to A0 CExx ICIORD (In reading) D15 to D0 (In reading) ICIOWR (In writing) D15 to D0 (In writing) IOIS16 DACKn In this example, DACKn is active-high. Figure 11.20 Wait Timing for PCMCIA I/O Card Interface Rev.1.00 Jan.
Page 456 11. Local Bus State Controller (LBSC) Tpci0 Tpci Tpci1w CLKOUT A25 to A1 CExx IORD (WE2) (In reading) D15 to D0 (In reading) IOWR (WE3) (In writing) D15 to D0 (In writing) IOIS16 DACKn In this example, DACKn is active-high. Figure 11.21 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.1.00 Jan.
Page 457: Mpx Interface
11.5.6 MPX Interface When both the MODE 7 pin is set to 0 at a power-on reset by the PRESET pin, the MPX interface is selected for area 0. The MPX interface is selected for areas 1 to 6 by the MPX bit in CS1BCR, CS2BCR, and CS4BCR to CS6BCR.
Page 458 11. Local Bus State Controller (LBSC) SH7785 CLKOUT D31 to D0 Figure 11.22 Example of 32-Bit Data Width MPX Connection SH7785 CLKOUT RD/WR D63 to D0 Figure 11.23 Example of 64-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for area 0, the bus size should be set to 64 or 32 bits by MODE5 and MODE6.
Page 459 11. Local Bus State Controller (LBSC) Tmd1w Tmd1 CLKOUT RD/FRAME D63 to D0 DACK Figure 11.24 MPX Interface Timing 1 (Single Read Cycle, IW = 0000, No External Wait, 64-Bit Bus Width) Rev.1.00 Jan. 10, 2008 Page 429 of 1658 REJ09B0261-0100...
Page 460 11. Local Bus State Controller (LBSC) CLKOUT RD/FRAME D63 to D0 DACKn In this example, DACKn is active-high. The circles indicate the sampling timing. Figure 11.25 MPX Interface Timing 2 (Single Read, IW = 0000, One External Wait Inserted, 64-Bit Bus Width) Rev.1.00 Jan.
Page 461 CLKOUT RD/FRAME D63 to D0 DACKn In this example, DACKn is active-high. The circle indicates the sampling timing. Figure 11.26 MPX Interface Timing 3 (Single Write Cycle, IW = 0000, No External Wait, 64-Bit Bus Width) 11. Local Bus State Controller (LBSC) Tmd1 Rev.1.00 Jan.
Page 462 11. Local Bus State Controller (LBSC) CLKOUT RD/FRAME D63 to D0 DACKn In this example, DACKn is active-high. Figure 11.27 MPX Interface Timing 4 (Single Write Cycle, IW = 0001, One External Wait Inserted, 64-Bit Bus Width) Rev.1.00 Jan. 10, 2008 Page 432 of 1658 REJ09B0261-0100 Tmd1w Tmd1w...
Page 463 11. Local Bus State Controller (LBSC) Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 CLKOUT RD/FRAME D63 to D0 DACKn In this example, DACKn is active-high. Figure 11.28 MPX Interface Timing 5 (Burst Read Cycle, IW = 0000, No External Wait, 64-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
Page 464 11. Local Bus State Controller (LBSC) Tmd1w CLKOUT RD/FRAME D63 to D0 DACKn In this example, DACKn is active-high. Figure 11.29 MPX Interface Timing 6 (Burst Read Cycle, IW = 0000, External Wait Control, 64-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
Page 465 11. Local Bus State Controller (LBSC) Tmd1 Tmd2 Tmd3 Tmd4 CLKOUT RD/FRAME D63 to D0 DACKn In this example, DACKn is active-high. Figure 11.30 MPX Interface Timing 7 (Burst Write Cycle, IW = 0000, No External Wait, 64-Bit Width, 32-Byte Data Transfer) Rev.1.00 Jan.
Page 466 11. Local Bus State Controller (LBSC) CLKOUT RD/FRAME D63 to D0 DACKn In this example, DACKn is active-high. Figure 11.31 MPX Interface Timing 8 (Burst Write Cycle, IW = 0001, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan. 10, 2008 Page 436 of 1658 REJ09B0261-0100 Tmd1w Tmd1...
Page 467 11. Local Bus State Controller (LBSC) Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 CLKOUT RD/FRAME D31 to D0 DACKn In this example, DACKn is active-high. Figure 11.32 MPX Interface Timing 9 (Burst Read Cycle, IW = 0000, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
Page 468 11. Local Bus State Controller (LBSC) Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 CLKOUT RD/FRAME D31 to D0 DACKn In this example, DACKn is active-high. Figure 11.33 MPX Interface Timing 10 (Burst Read Cycle, IW = 0000, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
Page 469 11. Local Bus State Controller (LBSC) Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 CLKOUT RD/FRAME D31 to D0 DACKn In this example, DACKn is active-high. Figure 11.34 MPX Interface Timing 11 (Burst Write Cycle, IW = 0000, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
Page 470 11. Local Bus State Controller (LBSC) Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 CLKOUT RD/FRAME D31 to D0 DACKn In this example, DACKn is active-high. Figure 11.35 MPX Interface Timing 12 (Burst Write Cycle, IW = 0001, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer) Rev.1.00 Jan.
Page 471: Byte Control Sram Interface
11.5.7 Byte Control SRAM Interface The byte control SRAM interface is a memory interface that outputs a byte-select strobe (WEn) in both read and write bus cycles. This interface has 16-bit data pins and can be connected to SRAM having an upper byte select strobe and lower select strobe functions such as UB and LB. Areas 1 and 4 can be specified as a byte control SRAM interface.
Page 472 11. Local Bus State Controller (LBSC) SH7785 A18 to A3 D63 to D48 D47 to D32 D31 to D16 D15 to D0 Figure 11.37 Example of Byte Control SRAM with 64-Bit Data Width Rev.1.00 Jan. 10, 2008 Page 442 of 1658 REJ09B0261-0100 64K ×...
Page 473 11. Local Bus State Controller (LBSC) CLKOUT A25 to A0 D31 to D0 (In reading) DACKn In this example, DACKn is active-high. Figure 11.38 Basic Read Cycle of Byte Control SRAM (No Wait) Rev.1.00 Jan. 10, 2008 Page 443 of 1658 REJ09B0261-0100...
Page 474 11. Local Bus State Controller (LBSC) TAS1 CLKOUT A25-A0 (In reading) D63-D0 TS1: CSn assertion - RD assertion delay cycle CSnWCR RDS = 001 TAS1: Address setup wait CSnWCR ADS=001 CLKOUT (In writing) D63 to D0 (ADS=000) D63 to D0 (ADS=001 to 111) TS1: CSn assertion - WEn assertion delay cycle CSnWCR WTS = 001...
Page 475 11. Local Bus State Controller (LBSC) CLKOUT A25 to A0 D31 to D0 (In reading) DACKn In this example, DACKn is active-high. Figure 11.40 Wait State Timing of Byte Control SRAM (One Internal Wait + One External Wait) Rev.1.00 Jan. 10, 2008 Page 445 of 1658 REJ09B0261-0100...
Page 476: Wait Cycles Between Access Cycles
11. Local Bus State Controller (LBSC) 11.5.8 Wait Cycles between Access Cycles When the external memory bus operating frequency is high, the turn-off of the data buffer performed on completion of reading from a low-speed device may not be made in time. This cause a collision with the next access data or a malfunction, which results in lower reliability.
Page 477 11. Local Bus State Controller (LBSC) Twait Twait CLKOUT A25 to A0 D31 to D0 Reading area m space Reading area n space Writing area n space CSnBCR.IWRRD=001 CSnBCR.IWRWS=001 Figure 11.41 Wait Cycles between Access Cycles (Access Size Is 4 Bytes) Rev.1.00 Jan.
Page 478: Bus Arbitration
11. Local Bus State Controller (LBSC) 11.5.9 Bus Arbitration This LSI is provided with a bus arbitration function that gives the bus to an external device when a request is issued from the device. This bus arbitration supports master mode and slave mode. In master mode the bus is held on a steady state, and is released to another device in response to a bus request.
Page 479 CLKOUT BREQ BACK A25 to A0 D31 to D0 (write) Master-mode device access BREQ BACK A25 to A0 D31 to D0 (write) Slave-mode device access Master access Figure 11.42 Arbitration Sequence 11. Local Bus State Controller (LBSC) Asserted for 2 cycles or more Negated within 2 cycles Hi-Z Hi-Z...
Page 480: Master Mode
11. Local Bus State Controller (LBSC) 11.5.10 Master Mode The processor in master mode holds the bus itself until it receives a bus request. On receiving an assertion (low level) of the bus request signal (BREQ) from the outside, the master mode processor releases the bus and asserts (drives low) the bus use permission signal (BACK) as soon as the currently executing bus cycle ends.
Page 481: Slave Mode
11. Local Bus State Controller (LBSC) 11.5.11 Slave Mode In slave mode, usually, the bus is released. Unless the bus control is hold by performing bus arbitration, the external device cannot be accessed. The bus is released at a reset, and the bus arbitration sequence starts from the fetch of the reset vector.
Page 482: Mode Pin Settings And General Input Output Port Settings About Data Bus Width
11. Local Bus State Controller (LBSC) 11.5.14 Mode Pin Settings and General Input Output Port Settings about Data Bus Width Table 11.18 shows the examples of MODE pin settings and port settings (GPIO port control register) related to the selection of the data bus width used in the local bus. Table 11.18 MODE Pin Settings and Port Settings Related to Data Bus Width Selection Data Bus Width...
Page 483 Table 11.19 Register Settings for Divided-Up DACKn Output in DMA1 Transfer Using the SRAM/Burst ROM/Byte Control SRAM Interfaces Bus Width Access Size in [Bit] DMA Transfer Byte Word Longword 16 bytes 32 bytes Byte Word Longword 16 bytes 32 bytes Byte Word Longword...
Page 484 11. Local Bus State Controller (LBSC) Table 11.20 Register Settings for Divided-Up DACKn Output in DMA1 Transfer Using the PCMCIA Interface Bus Width [Bit] Access Size Byte Word Longword 16 bytes 32 bytes Byte Word Longword 16 bytes 32 bytes Notes: "⎯"...
Page 485 Table 11.21 Register Settings for Divided-Up DACKn Output in DMA1 Transfer in Read Access Using the MPX Interface Bus Width [Bit] Access Size Byte Word Longword 16 bytes 32 bytes Byte Word Longword 16 bytes 32 bytes Note: "⎯" means an arbitrary setting value. When transfer is done in a single bus cycle, DACKn is not divided up because DACKn is output once in DMA1 transfer.
Page 486 11. Local Bus State Controller (LBSC) Table 11.22 Register Settings for Divided-Up DACKn Output in DMA1 Transfer in Write Access Using the MPX Interface Bus Width Bus Cycle [Bit] Access Size Number Byte Word Longword 16 bytes 32 bytes Byte Word Longword 16 bytes...
Page 487: Section 12 Ddr2-Sdram Interface (Dbsc2)
Section 12 DDR2-SDRAM Interface (DBSC2) The DDR2-SDRAM interface (DBSC2) controls the DDR2-SDRAM. 12.1 Features • Supports 32-bit and 16-bit external data bus widths • Supports from DDR2-600 (controller operation at 300 MHz) to DDR2-400 (controller operation at 200 MHz) • Connects to 64-bit SuperHyway internal bus •...
Page 488 12. DDR2-SDRAM Interface (DBSC2) ⎯ DDR2-SDRAM data bus width: 16 bits • One 256 Mbits (16M × 16 bits) connected in parallel (total capacity = 256 Mbits) • Two 256 Mbits (32M × 8 bits) connected in parallel (total capacity = 512 Mbits) •...
Page 489 Figure 12.1 shows a block diagram of the DBSC2. DBSC2 Request queue Control unit MCK0/ MCK0, MCK1/ MCK1 Notes: Request queue: Stores the access request of the SuperHyway bus. Write data queue: Stores the write data sent from the SuperHyway bus. Response queue: Stores the read data to be sent back to the SuperHyway bus.
Page 490: Input/Output Pins
12. DDR2-SDRAM Interface (DBSC2) 12.2 Input/Output Pins Table 12.1 shows the pin configuration of the DBSC2. Table 12.1 Pin Configuration of the DBSC2 Pin Name Function MCK0 DDR2-SDRAM clock 0 MCK0 DDR2-SDRAM clock 0 MCK1 DDR2-SDRAM clock 1 MCK1 DDR2-SDRAM clock 1 MCKE Clock enable Chip select...
Page 491 12. DDR2-SDRAM Interface (DBSC2) The frequency of the SDRAM operation clocks MCK0, MCK0, MCK1, and MCK1 is the same as the frequency of the DDR clock. MDQ7 to MDQ0 correspond to MDQS0 and MDM0, MDQ15 to MDQ8 correspond to MDQS1 and MDM1, MDQ23 to MDQ16 correspond to MDQS2 and MDM2, and MDQ31 to MDQ24 correspond to MDQS3 and MDM3.
Page 492 12. DDR2-SDRAM Interface (DBSC2) Table 12.2 An Example of DDR2-SDRAM Connection (When Four 2-Gb DDR2-SDRAM Units (256 M × 8 Bits) Are Used) MCK1, MCK0, MCK1 MCK0 Memory Memory #1 Connected* Memory #2 Connected* Memory #3 Connected* Memory #4 Connected* Notes: 1.
Page 493 3. SDRAM pins should be connected as shown below. Memory #1 Pins SH7785 Pins MDQS3 MDQS3 MDM3 MDQ31 MDQ30 MDQ29 MDQ28 MDQ27 MDQ26 MDQ25 MDQ24 4. SDRAM pins should be connected as shown below. Memory #2 Pins SH7785 Pins MDQS2 MDQS2 MDM2 MDQ23...
Page 494 12. DDR2-SDRAM Interface (DBSC2) 5. SDRAM pins should be connected as shown below. Memory #3 Pins 6. SDRAM pins should be connected as shown below. Memory #4 Pins Rev.1.00 Jan. 10, 2008 Page 464 of 1658 REJ09B0261-0100 SH7785 Pins MDQS1 MDQS1 MDM1 MDQ15...
Page 495: Data Alignment
12. DDR2-SDRAM Interface (DBSC2) 12.3 Data Alignment The DBSC2 accesses DDR2-SDRAM with a fixed burst length of 4 (figure 12.2). As shown in table 12.3 and table 12.4, invalid read data is discarded during reading, and data mask signals are used to mask invalid data during writing, according to the access size.
Page 496 12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 MCKE MRAS MCAS MA[14:11] Invalid Valid MA[9:0] MA[10] Invalid Valid MBA[2:0] Invalid Valid Example of CL = 3 32-bit width: MDQS[3:0] 16-bit width: MDQS[1:0] Invalid 32-bit width: MDM[3:0] 16-bit width: MDM[1:0] 32-bit width: MDQ[31:0] Invalid 16-bit width: MDQ[15:0] SDRAM...
Page 497 Table 12.3 Positions of Valid Data for Access with Burst Length of 4, when the External Data Bus Width Is Set to 32 Bits (1) Little Endian First Access Byte access Invalid (address 8n + 0,1,2,3) Byte access Valid (address 8n + 4,5,6,7) Word access Invalid...
Page 498 12. DDR2-SDRAM Interface (DBSC2) Table 12.4 Positions of Valid Data for Access with Burst Length of 4, when the External Data Bus Width Is Set to 16 Bits (1) Little Endian First Access Byte access Invalid (address 8n + 0,1) Byte access Invalid (address 8n + 2,3)
Page 499 (2) Big Endian First Access Byte access Valid (address 8n + 0,1) Byte access Invalid (address 8n + 2,3) Byte access Invalid (address 8n + 4,5) Byte access Invalid (address 8n + 6,7) Word access Valid (address 8n + 0) Word access Invalid (address 8n + 2)
Page 500 12. DDR2-SDRAM Interface (DBSC2) Table 12.5 Data Alignment for Access in Little Endian when External Data Bus Width Is Set to 32 Bits Access Size Address Byte Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Word Address 0...
Page 501 Access Size Address Quadword Address 0 (First access: address 4) Address 0 (Second access: Address 0) Table 12.6 Data Alignment for Access in Big Endian when External Data Bus Width Is Set to 32 Bits Access Size Address Byte Address 0 Address 1 Address 2 Address 3...
Page 502 12. DDR2-SDRAM Interface (DBSC2) Access Size Address Word Address 0 Address 2 Address 4 Address 6 Longword Address 0 Address 4 Quadword Address 0 (First access: Address 0) Address 0 (Second access: Address 4) Rev.1.00 Jan. 10, 2008 Page 472 of 1658 REJ09B0261-0100 MDQ31 to MDQ23 to...
Page 503 Table 12.7 Data Alignment for Access in Little Endian when External Data Bus Width Is Set to 16 Bits Access Size Address Byte Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Word Address 0 Address 2 Address 4...
Page 504 12. DDR2-SDRAM Interface (DBSC2) Access Size Address Longword Address 0 (First access: Address 2) Address 0 (Second access: Address 0) Address 4 (First access: Address 6) Address 4 (Second access: Address 4) Quadword Address 0 (First access: Address 6) Address 0 (Second access: Address 4) Address 0...
Page 505 Table 12.8 Data Alignment for Access in Big Endian when External Data Bus Width Is Set to 16 Bits Access Size Address Byte Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Word Address 0 Address 2 Address 4...
Page 506 12. DDR2-SDRAM Interface (DBSC2) Access Size Address Longword Address 0 (First access: Address 0) Address 0 (Second access: Address 2) Address 4 (First access: Address 4) Address 4 (Second access: Address 6) Quadword Address 0 (First access: Address 0) Address 0 (Second access: Address 2) Address 0...
Page 507 When the external bus width is set to 16 bits 16-byte read/write access (a total of two commands are issued) Address 16n + 0 Address 16n + 8 32-byte read access (a total of four commands are issued) Address 32n + 0 Address 32n + 8 Address 32n + 16 Address 32n + 24...
Page 508 12. DDR2-SDRAM Interface (DBSC2) When the external bus width is set to 32 bits 16-byte read/write access (a total of one command is issued) Address 16n + 0 Address 16n + 8 32-byte read access (a total of two commands are issued) Address 32n + 0 Address 32n + 8 Address 32n + 16...
Page 509: Register Descriptions
12. DDR2-SDRAM Interface (DBSC2) 12.4 Register Descriptions Table 12.9 shows the DBSC2 register configuration; Table 12.10 shows register states in the different processing modes. The register bit width is 32 bits, and the longword size (32 bits) should be used for register access. If registers are accessed with sizes other than the longword size, correct operation cannot be guaranteed.
Page 510 12. DDR2-SDRAM Interface (DBSC2) Table 12.9 DBSC2 Register Configuration Register Name Abbreviation R/W DBSC2 status DBSTATE register SDRAM DBEN operation enable register SDRAM DBCMDCNT command control register SDRAM DBCONF configuration setting register SDRAM timing DBTR0 register 0 SDRAM timing DBTR1 register 1 SDRAM timing DBTR2...
Page 511 Table 12.10 Register Status in each Processing Mode Register Name Abbreviation DBSC2 status DBSTATE register SDRAM operation DBEN enable register SDRAM command DBCMDCNT control register SDRAM DBCONF configuration setting register SDRAM timing DBTR0 register 0 SDRAM timing DBTR1 register 1 SDRAM timing DBTR2 register 2...
Page 512: Dbsc2 Status Register (Dbstate)
12. DDR2-SDRAM Interface (DBSC2) 12.4.1 DBSC2 Status Register (DBSTATE) The DBSC2 status register (DBSTATE) is a read-only register. Writing is invalid. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ ⎯ ⎯ ⎯...
Page 513: Sdram Operation Enable Register (Dben)
12.4.2 SDRAM Operation Enable Register (DBEN) The SDRAM operation enable register (DBEN) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: Initial Bit Name Value ⎯...
Page 514: Sdram Command Control Register (Dbcmdcnt)
12. DDR2-SDRAM Interface (DBSC2) 12.4.3 SDRAM Command Control Register (DBCMDCNT) The SDRAM command control register (DBCMDCNT) is a readable/writable register. It is initialized only upon power-on reset. The CMD2 to CMD0 bits in DBCMDCNT are always read as 000. BIt: ⎯...
Page 515 Initial Bit Name Value 2 to 0 CMD2 to CMD0 Note: This register can be written only when automatic issue of auto-refresh is disabled (the ARFEN bit in the DBRFCNT0 register is cleared to 0). 12. DDR2-SDRAM Interface (DBSC2) Description SDRAM Command Issue Bit These bits are used to issue commands necessary to execute the DDR2-SDRAM initialization sequence and...
Page 516: Sdram Configuration Setting Register (Dbconf)
12. DDR2-SDRAM Interface (DBSC2) 12.4.4 SDRAM Configuration Setting Register (DBCONF) The SDRAM configuration setting register (DBCONF) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: Initial...
Page 517 Initial Bit Name Value 15 to 10 ⎯ All 0 9, 8 BASFT1 BASFT0 ⎯ 7 to 3 All 0 1, 0 BWIDTH1 BWIDTH0 Note: Writing to this register should be performed only when the following conditions are met. • When SDRAM access is disabled (when the ACEN bit in the DBEN register is 0.).
Page 518: Sdram Timing Register 0 (Dbtr0)
12. DDR2-SDRAM Interface (DBSC2) 12.4.5 SDRAM Timing Register 0 (DBTR0) The SDRAM timing register 0 (DBTR0) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ TRFC6 TRFC5 TRFC4 Initial value: R/W: Initial...
Page 519 Initial Bit Name Value 23 to 20 ⎯ All 0 19 to 16 TRAS3 to 0011 TRAS0 ⎯ 12. DDR2-SDRAM Interface (DBSC2) Description Reserved These bits are always read as 0. The write value should always be 0. Operation when a value other than 0 is written is not guaranteed.
Page 520 12. DDR2-SDRAM Interface (DBSC2) Initial Bit Name Value 14 to 8 TRFC6 to 000 0101 TRFC0 ⎯ 7 to 3 All 0 Rev.1.00 Jan. 10, 2008 Page 490 of 1658 REJ09B0261-0100 Description tRFC (REF-ACT/REF period) Setting Bits These bits set the REF-ACT/REF minimum period constraint These bits should be set according to the DDR2-SDRAM specifications.
Page 521 Initial Bit Name Value 2 to 0 TRCD2 to TRCD0 Notes: 1. AL (Additive Latency) supported by the DBSC2 is only 0. 2. Writing to this register should be performed only when the following conditions are met. • When SDRAM access is disabled (when the ACEN bit in the DBEN register is 0.). •...
Page 522: Sdram Timing Register 1 (Dbtr1)
12. DDR2-SDRAM Interface (DBSC2) 12.4.6 SDRAM Timing Register 1 (DBTR1) The SDRAM timing register 1 (DBTR1) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: Initial...
Page 523 Initial Bit Name Value 15 to 11 ⎯ All 0 10 to 8 TRRD2 to TRRD0 ⎯ 7 to 3 All 0 12. DDR2-SDRAM Interface (DBSC2) Description Reserved These bits are always read as 0. The write value should always be 0. Operation when a value other than 0 is written is not guaranteed.
Page 524 12. DDR2-SDRAM Interface (DBSC2) Initial Bit Name Value 2 to 0 TWR2 to TWR0 Note: Writing to this register should be performed only when the following conditions are met. • When SDRAM access is disabled (when the ACEN bit in the DBEN register is 0.). •...
Page 525: Sdram Timing Register 2 (Dbtr2)
12.4.7 SDRAM Timing Register 2 (DBTR2) The SDRAM timing register 2 (DBTR2) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: Initial Bit Name Value 31 to 26 ⎯...
Page 526 12. DDR2-SDRAM Interface (DBSC2) Initial Bit Name Value 20 to 16 TRC4 to 0 0100 TRC0 15 to 12 ⎯ All 0 Rev.1.00 Jan. 10, 2008 Page 496 of 1658 REJ09B0261-0100 Description tRC (ACT-ACT/REF period) Setting Bits These bits set the constraint for the minimum time from ACT command to ACT command (in the same bank)/ REF command.
Page 527 Initial Bit Name Value 11 to 8 RDWR3 to 0011 RDWR0 ⎯ 7 to 4 All 0 12. DDR2-SDRAM Interface (DBSC2) Description READ-WRITE Command Minimum Interval Setting Bits These bits set the READ-WRITE command minimum interval constraint. These bits should be set according to the SDRAM specifications.
Page 528 12. DDR2-SDRAM Interface (DBSC2) Initial Bit Name Value 3 to 0 WRRD3 to 0011 WRRD0 Note: Writing to this register should be performed only when the following conditions are met. • When SDRAM access is disabled (when the ACEN bit in the DBEN register is 0.). •...
Page 529: Sdram Refresh Control Register 0 (Dbrfcnt0)
12.4.8 SDRAM Refresh Control Register 0 (DBRFCNT0) The SDRAM refresh control register 0 (DBRFCNT0) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: Initial Bit Name...
Page 530: Sdram Refresh Control Register 1 (Dbrfcnt1)
12. DDR2-SDRAM Interface (DBSC2) Initial Bit Name Value SRFEN 12.4.9 SDRAM Refresh Control Register 1 (DBRFCNT1) The SDRAM refresh control register 1 (DBRFCNT1) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯...
Page 531 Initial Bit Name Value 12 to 0 TREFI12 to 0 0010 TREFI0 0000 0000 Note: Writing to this register should be performed only when the following condition is met. • When automatic issue of auto-refresh is disabled (when the ARFEN bit in the DBRFCNT0 register is cleared to 0.).
Page 532: Sdram Refresh Control Register 2 (Dbrfcnt2)
12. DDR2-SDRAM Interface (DBSC2) 12.4.10 SDRAM Refresh Control Register 2 (DBRFCNT2) The SDRAM refresh control register 2 (DBRFCNT2) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ TH14 TH13 TH12 Initial value: R/W: BIt: ⎯ ⎯ ⎯...
Page 533 Initial Bit Name Value ⎯ 15 to 8 All 0 7 to 0 LV0TH7 to 1000 0000 R/W LV0TH0 Notes: 1. The TREFI bit value of the DBRFCNT1 register and the LV1TH bit of this register are added and the result used as the maximum value of the auto-refresh counter, that is, the maximum interval for refresh commands when periodically issuing auto-refresh signals.
Page 534: Sdram Refresh Status Register (Dbrfsts)
12. DDR2-SDRAM Interface (DBSC2) 12.4.11 SDRAM Refresh Status Register (DBRFSTS) The SDRAM refresh status register (DBRFSTS) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: Initial...
Page 535: Ddrpad Frequency Setting Register (Dbfreq)
12.4.12 DDRPAD Frequency Setting Register (DBFREQ) The DDRPAD frequency setting register (DBFREQ) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: Initial Bit Name Value ⎯...
Page 536 12. DDR2-SDRAM Interface (DBSC2) Initial Bit Name Value 2 to 0 FREQ2 to FREQ0 Note: This register is used for initialization, when canceling self-refresh, and when canceling power supply backup. For details, refer to section 12.5.3, Initialization Sequence, section 12.5.4, Self-Refresh Operation, and (2) Recovery from SDRAM Power Supply Backup Mode in section 12.5.10, DDR2-SDRAM Power Supply Backup Function.
Page 537: Ddrpad Dic, Odt, Ocd Setting Register (Dbdicodtocd)
12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD) The SDRAM refresh status register (DBRFSTS) is a readable/writable register. It is initialized only upon power-on reset. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ ⎯ ⎯ ODTEN1 Initial value: R/W: Initial Bit Name...
Page 538 12. DDR2-SDRAM Interface (DBSC2) Initial Bit Name Value DIC_DQ DIC_CK 15 to 13 ⎯ All 0 12, 11 ODTEN1 ODTEN0 Rev.1.00 Jan. 10, 2008 Page 508 of 1658 REJ09B0261-0100 Description Data Pin Impedance value This bit should be set to the same value as the value set for DIC of EMRS(1) in the DDR2-SDRAM.
Page 539 Initial Bit Name Value ODT_ EARLY 9, 8 T_ODT1 T_ODT0 ⎯ 7 to 3 All 0 ⎯ 2 to 0 12. DDR2-SDRAM Interface (DBSC2) Description ODT Assertion Period Setting Sets the ODT assertion period. The number of cycles is the number of DDR clock cycles. This setting is valid only when ODTEN is set to 01.
Page 540: Sdram Mode Setting Register (Dbmrcnt)
12. DDR2-SDRAM Interface (DBSC2) 12.4.14 SDRAM Mode Setting Register (DBMRCNT) The SDRAM mode setting register (DBMRCNT) is a write-only register. If it is read, correct operation cannot be guaranteed. BIt: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯...
Page 541 12. DDR2-SDRAM Interface (DBSC2) By writing to this register, the DDR2-SDRAM address and bank address pins can be directly manipulated to set the mode and extended mode registers. When this register is written, the mode register setting (MRS)/extended mode register setting (EMRS) command is issued for the DDR2- SDRAM.
Page 542: Dbsc2 Operation
12. DDR2-SDRAM Interface (DBSC2) 12.5 DBSC2 Operation 12.5.1 Supported SDRAM Commands Table 12.11 lists the SDRAM commands issued by the DBSC2. These commands are issued to the DDR2-SDRAM in synchronously with MCK0, MCK0, MCK1, and MCK1. In the table, n-1 indicates the state of the signal applied to DDR2-SDRAM one cycle before SDRAM command issue;...
Page 543: Sdram Command Issue
12. DDR2-SDRAM Interface (DBSC2) 12.5.2 SDRAM Command Issue Basic Access The DBSC2 stores in a queue the requests received via the SuperHyway bus. Request processing is begun around the time of preceding precharge/activate processing, but processing completion is in the order received in the queue. When SDRAM initialization is completed, upon receiving a read/write request, a page miss occurs with all banks in the closed state.
Page 544 12. DDR2-SDRAM Interface (DBSC2) 16-bit external bus 1 command Read (1, 2, 4, or 8 bytes) 2 commands Read (16 bytes) 4 commands Read (32 bytes) 1 command Write (1, 2, 4, or 8 bytes) 2 commands Write (16 bytes) 4 commands Write (32 bytes) 32-bit external bus...
Page 545 command to be issued at time 2 from the following request queue. From the search results it is seen that advance precharge processing can be executed for the third read (8-byte) request and the fourth read (16-byte) request. Because the DBSC2 gives priority to preceding requests, it decides to perform advance precharge processing for the third read (8-byte) request, and issues a PRE command to the SDRAM.
Page 546: Initialization Sequence
12. DDR2-SDRAM Interface (DBSC2) 12.5.3 Initialization Sequence The following shows an example of the initialization sequence. For detailed information such as the power supply and timing parameters, please refer to the datasheet for the DDR2-SDRAM being used. 1. Following the instructions in the datasheet guide for the SDRAM being used, supply the power and the reference voltage.
Page 547: Self-Refresh Operation
10. Writing to DBMRCNT issues the MRS command to the SDRAM and sets the various parameters. At this point, the operating mode is set to normal mode, the DLL reset is set to reset, the burst length is set to 4, and the burst type is set to sequential. The additive latency should be set to 0, and CAS latency and write recovery times should be set to match the settings of DBTR0 and DBTR1.
Page 548 12. DDR2-SDRAM Interface (DBSC2) Because access is disabled in self-refresh mode, any attempt to access data in the DDR2-SDRAM will be ignored. The following procedure is used to make a transition to self-refresh mode. 1. Check to make sure the DBSC2 is not being accessed. The time required for transition to self- refresh must not exceed the auto-refresh interval requested by the SDRAM by interrupts or some other causes.
Page 549 1. Check to make sure the DBSC2 is not being accessed. The time required for transition to self- refresh must not exceed the auto-refresh interval requested by the SDRAM by interrupts or some other causes. 2. Set the ACEN bit in the SDRAM operation enable register (DBEN) to 0 (access disabled). 3.
Page 550: Auto-Refresh Operation
12. DDR2-SDRAM Interface (DBSC2) 12.5.5 Auto-Refresh Operation When the auto-refresh enable bit (ARFEN) in the SDRAM refresh control register 0 (DBRFCNT0) is 1, the auto-refresh command is issued periodically. If accessing data in the SDRAM, always make sure this is set. The average refresh interval is set in the TREFI bits in the SDRAM refresh control register 1 (DBRFCNT1).
Page 551: Regarding Address Multiplexing
Refresh counter value Max. value (Average refresh interval + LV1TH) Level 2 (Refreshing not done) LV1TH Level 1 (Refreshing during request empty cycles) LV0TH Level 0 (Refreshing in vacant periods between SHwy commands) Figure 12.7 Relation between Auto-Refresh Operation and Threshold Values 12.5.6 Regarding Address Multiplexing Memory of various sizes can be connected through the settings of the SDRAM configuration...
Page 552 12. DDR2-SDRAM Interface (DBSC2) Table 12.12 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Width Is Set to 16 Bits (BASFT = 00) (When Using a 16-Bit Product, One Is Connected; for 8-Bit Products, Two Are Connected) Memory Type...
Page 553 Table 12.13 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Width Is Set to 32 Bits (BASFT = 00) (When Using 16-Bit Products, Two Are Connected; for 8-Bit Products, Four Are Connected) Memory Type MA14 MA13 MA12 MA11 MA10 MA9 ROW ⎯...
Page 554 12. DDR2-SDRAM Interface (DBSC2) Table 12.14 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Width Is Set to 16 Bits (BASFT = 01) (When Using a 16-Bit Product, One Is Connected; for 8-Bit Products, Two Are Connected) Memory Type...
Page 555 Table 12.15 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Width Is Set to 32 Bits (BASFT = 01) (When Using 16-Bit Products, Two Are Connected; for 8-Bit Products, Four Are Connected) Memory Type MA14 MA13 MA12 MA11 MA10 MA9 ROW ⎯...
Page 556 12. DDR2-SDRAM Interface (DBSC2) Table 12.16 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Width Is Set to 16 Bits (BASFT = 10) (When Using a 16-Bit Product, One Is Connected; for 8-Bit Products, Two Are Connected) Memory Type...
Page 557 Table 12.17 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Width Is Set to 32 Bits (BASFT = 10) (When Using 16-Bit Products, Two Are Connected; for 8-Bit Products, Four Are Connected) Memory Type MA14 MA13 MA12 MA11 MA10 MA9 ROW ⎯...
Page 558 12. DDR2-SDRAM Interface (DBSC2) Table 12.18 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Width Is Set to 16 Bits (BASFT = 11) (When Using a 16-Bit Product, One Is Connected; for 8-Bit Products, Two Are Connected) Memory Type...
Page 559 Table 12.19 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Width Is Set to 32 Bits (BASFT = 11) (When Using 16-bit Products, Two Are Connected; for 8-Bit Products, Four Are Connected) Memory Type MA14 MA13 MA12 MA11 MA10 MA9 ROW ⎯...
Page 560: Regarding Sdram Access And Timing Constraints
12. DDR2-SDRAM Interface (DBSC2) 12.5.7 Regarding SDRAM Access and Timing Constraints In this section, waveforms at the various pins during basic DDR2-SDRAM access are explained first and then the relation between DDR2-SDRAM access and the CAS latency (CL), tRAS, tRFC, tRCD, tRP, tRRD, tWR, tRTP, tRC, READ-WRITE minimum interval, WRITE-READ minimum interval set using the SDRAM timing registers 0 to 2 (DBTR0 to DBTR2) is explained.
Page 561 MCK0, MCK1 MCKE MRAS MCAS MA[14:11] Valid Invalid MA[9:0] MA[10] Valid Invalid MBA[2:0] Valid Invalid Example of CL = 3 MDQS[3:0] MDM[3:0] MDQ[31:0] SDRAM command bank A Figure 12.8 Waveforms for 1/2/4/8/16-Byte Reading (When the Bus Width Is Set to 32 Bits) Figure 12.9 shows waveforms for 32-byte reading when the bus width is set to 32 bits.
Page 562 12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 MCKE MRAS MCAS MA[14:11 ] Valid Invalid MA[9:0] MA[10] Valid Invalid Valid Invalid MBA[2:0] Example of CL = 3 MDQS[3:0] MDM[3:0] MDQ[31:0] SDRAM command bank A Figure 12.9 Waveforms for 32-Byte Reading (When the Bus Width Is Set to 32 Bits) Figure 12.10 shows waveforms for 1/2/4/8/16-byte writing when the bus width is set to 32 bits.
Page 563 MCK0, MCK1 MCKE MRAS MCAS MA[14:11] Valid Invalid MA[9:0] MA[10] Valid Invalid MBA[2:0] Valid Invalid Example of CL = 3 MDQS[3:0] MDM[3:0] MDQ[31:0] SDRAM command bank A Figure 12.10 Waveforms for 1/2/4/8/16-Byte Writing (When the Bus Width Is Set to 32 Bits) Figure 12.11 shows waveforms for 32-byte writing when the bus width is set to 32 bits.
Page 564 12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 MCKE MRAS MCAS MA[14:11] Valid Invalid MA[9:0] MA[10] Valid Invalid Valid Invalid MBA[2:0] Example of CL = 3 MDQS[3:0] MDM[3:0] MDQ[31:0] SDRAM command bank A Figure 12.11 Waveforms for 32-Byte Writing (When the Bus Width Is Set to 32 Bits) Figure 12.12 shows waveforms during auto-refresh operation resulting from settings of the SDRAM refresh control registers 0, 1, and 2.
Page 565 MCK0, MCK1 MCKE MRAS MCAS MA[14:11] MA[9:0] MA[10] MBA[2:0] MDQS[3:0] MDM[3:0] MDQ[31:0] SDRAM command Figure 12.12 Auto-Refresh Operation Figure 12.13 shows the self-refresh operation. In order to perform self-refresh operation, the sequence must be observed. For details, refer to section 12.5.4, Self-Refresh Operation. When performing processing according to the sequence in section 12.5.4, Self-Refresh Operation, commands to be issued to the SDRAM are those shown in figure 12.13.
Page 566 12. DDR2-SDRAM Interface (DBSC2) example is shown in section 12.5.11, Method for Securing Time Required for Initialization, Self- Refresh Cancellation, etc. MCK0, MCK1 MCKE MRAS MCAS MA[14:11] MA[9:0] MA[10] Invalid MBA[2:0] MDQS[3:0] MDM[3:0] MDQ[31:0] SDRAM PALL command Regarding Timing Constraints Figure 12.14 shows the relation between the settings of CL, tRAS, tRCD, and tRP, and the issuing of commands.
Page 567 command, the constraint tRCD between the ACT command and READ command, and the constraint tRAS between the ACT command and the PRE command are involved. The DBSC2 waits to issue commands until each of the constraints is satisfied. MCK0, MCK1 MCKE MRAS MCAS...
Page 568 12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 MCKE MRAS MCAS MA[14:11] Valid Valid Invalid MA[9:0] MA[10] Valid Invalid Valid MBA[2:0] Valid Invalid Valid tRRD = 2 cycles Example of CL = 3 MDQS[3:0] MDM[3:0] MDQ[31:0] SDRAM command bank A bank B Figure 12.15 shows a case in which the pages for both of banks A and B are closed, the page for bank C is open, and a page hit has occurred.
Page 569 MCK0, MCK1 MCKE MRAS MCAS MA[14:11] Valid MA[9:0] MA[10] Valid MBA[2:0] Valid Example of CL = 3 MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid SDRAM WRITE bank A command Figure 12.16 shows a case in which, after a write request, access occurs requiring that bank B be closed.
Page 570 12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 MCKE MRAS MCAS MA[14:11] Valid Invalid MA[9:0] MA[10] Valid Invalid MBA[2:0] Valid Invalid Example of CL = 3 MDQS[3:0] MDM[3:0] MDQ[31:0] SDRAM command bank A Figure 12.17 shows an example of performing auto-refresh after read access of bank A, the page for which had been closed.
Page 571 MCK0, MCK1 MCKE MRAS MCAS MA[14:11] Valid Invalid MA[9:0] MA[10] Valid Invalid MBA[2:0] Valid Invalid RDWR = 4 cycles Example of CL = 3 MDQS[3:0] MDM[3:0] Invalid MDQ[31:0] Invalid SDRAM READ command bank Figure 12.18 READ-WRITE Minimum Time Figure 12.18 is an example of a case in which, after issuing a READ command, a WRITE command is issued.
Page 572 12. DDR2-SDRAM Interface (DBSC2) MCK0, MCK1 MCKE MRAS MCAS MA[14:11] Valid MA[9:0] MA[10] Valid MBA[2:0] Valid WRRD = 7 cycles Example of CL= 3 MDQS[3:0] Invalid MDM[3:0] MDQ[31:0] Invalid SDRAM WRITE command bank Figure 12.19 WRITE-READ Minimum Time Figure 12.19 is an example of a case in which, after issuing a WRITE command, a READ command is issued.
Page 573 MCK0, MCK1 MCKE MRAS MCAS MA[14:11] MA[9:0] MA[10] MBA[2:0] tRFC = 6 cycles MDQS[3:0] MDM[3:0] MDQ[31:0] SDRAM command Figure 12.20 is an example of a case in which, after issuing a REF command, a READ request is issued. In order to issue the ACT commend after issuing the REF command, the DBSC2 waits for a time stipulated by tRFC.
Page 574: Important Information Regarding Use Of 8-Bank Ddr2-Sdram Products
12. DDR2-SDRAM Interface (DBSC2) 12.5.8 Important Information Regarding Use of 8-Bank DDR2-SDRAM Products The DDR2-SDRAM specifications limit the number of banks in an 8-bank product which can be activated simultaneously. Control must be executed so that the number of activated banks never exceeds four banks.
Page 575 High level MCKE write Command 3 cycles Data for product with CL = 4 MODT tAOND = 2 cycles Terminating resistor in SDRAM As shown in the above figure, when CL is 4, the effective ODT control signal (MODT) to the SDRAM can be asserted at the same timing as the issue of the WRITE command.
Page 576: Ddr2-Sdram Power Supply Backup Function
12. DDR2-SDRAM Interface (DBSC2) 4 -> 5 cycles MCKE 5 cycles for read Command product with CL = 5 Data If the interval from the READ command to the WRITE command is 4 cycles, read data exists on the data bus when Rtt is turned on. Therefore, the interval should be 5 cycles. MODT Terminating Extended for 1 cycle...
Page 577 Normal operation This LSI DBSC2 IO cell Internal MCKE MBKPRST High level 1.0-V 1.8-V input power on power on Status signal Figure 12.23 SDRAM Power Supply Backup Function In order to implement the power supply backup function, a control signal MBKPRST is necessary to hold MCKE at low level even when power other than for the 1.8 V I/O is turned off.
Page 578 12. DDR2-SDRAM Interface (DBSC2) MCKE to high level, upon power-on reset the data within the SDRAM is destroyed. Hence if the state signal is not set in advance to a state other than power supply backup state, there is the danger that the destroyed data may be treated as the correct data.) In this way, procedures are used to make a transition to and cancel SDRAM power supply backup mode;...
Page 579: Cancellation, Etc
5. The SDRAM configuration setting register (DBCONF), SDRAM timing register 0 (DBTR0), SDRAM timing register 1 (DBTR1), and SDRAM timing register 2 (DBTR2) should be set. 6. By writing to the DDRPAD frequency setting register DBFREQ, DLL settings are made. A.
Page 580: Regarding Mcke Signal Operation
12. DDR2-SDRAM Interface (DBSC2) 12.5.13 Regarding MCKE Signal Operation The MCKE signal operation is explained using figure 12.24. Here, the explanation assumes that MBKPRST is high-level input. Prior to power-on reset the MCKE signal is indefinite, but upon power-on reset is output at low level. After release of power-on reset, by writing 011 to the CMD bits in the SDRAM command control register (DBCMDCNT), the MCKE signal output is at high level, corresponding to the enable state.
Page 581: Section 13 Pci Controller (Pcic)
Section 13 PCI Controller (PCIC) The PCI controller (PCIC) controls the PCI bus and enables data transfers between memory connected to an external bus and a PCI device connected to the PCI bus. The PCIC facilitates the system design using the PCI bus and enables short and fast data transfer. The PCIC operates as a bus bridge which links the PCI bus to the internal bus (SuperHyway bus).
Page 582 13. PCI Controller (PCIC) • Cache snoop functions are supported when the PCIC is a target (cache coherency can be supported by sacrificing performance). • Supports four external interrupt inputs (INTA, INTB, INTC, and INTD) in host mode • Supports one external interrupt output (INTA) in normal mode •...
Page 583 Figure 13.1 shows a block diagram of the PCIC. SHwy bus interface Data FIFO read 32 bytes x 2 PCIECR Data FIFO write 32 bytes x 2 SHwy clock input Interrupt control Interrupt The PCIC comprises two blocks, the PCI bus interface block and SuperHyway bus interface block.
Page 584: Input/Output Pins
13. PCI Controller (PCIC) 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the PCIC. Table 13.1 Signal Descriptions PCI Standard Signal Name Signal D32/AD0/DR0 to AD[31:0] D37/AD5/DR5, D38/AD6/DG0 to D43/AD11/DG5, D44/AD12/DB0 to D49/AD17/DB5, D50/AD18 to D63/AD31 WE7/CBE3 to C/BE[3:0] WE4/CBE0 PCICLK/...
Page 585 PCI Standard Signal Name Signal LOCK/ODDF LOCK IDSEL IDSEL DEVSEL/ DEVSEL DCLKOUT SCIF0_CTS/ INTD INTD DREQ3/INTC INTC DREQ2/INTB INTB INTA INTA REQ3 REQ3 REQ2 to REQ1 REQ[2:1] GNT3 GNT3 GNT2 to GNT1 GNT[2:1] REQ0/REQOUT REQ0 GNT0/GNTIN GNT0 SERR SERR PERR PERR PCIRESET —...
Page 586 13. PCI Controller (PCIC) PCI Standard Signal Name Signal MODE12 — MODE11 Legend: TRI: Tri-state STRI: Sustained tri-state Open Drain Only input OUT: Only output Rev.1.00 Jan. 10, 2008 Page 556 of 1658 REJ09B0261-0100 Description PCI Operating Mode Select 00: PCI host mode, or PCI host bridge operation by PCICLK 01: PCI normal mode, or non-PCI host bridge operation by PCICLK...
Page 587: Register Descriptions
13.3 Register Descriptions Table 13.2 shows a list of PCIC registers. The addresses and offsets of PCI configuration registers are the values used when the PCIC is in little endian mode. The access size is the maximum access size in each register. The registers in the PCI configuration register space can be accessed with 32-, 16-, or 8-bit access sizes.
Page 588 13. PCI Controller (PCIC) Name Abbreviation PCI interrupt line register PCIINTLINE PCI interrupt pin register PCIINTPIN PCI minimum grant register PCIMINGNT PCI maximum latency register PCIMAXLAT PCI capability ID register PCICID PCI next item pointer register PCINIP PCI power management PCIPMC capability register PCI power management...
Page 589 Name Abbreviation PCI power management PCIPINT interrupt register PCI power management PCIPINTM interrupt mask register PCI memory bank register 0 PCIMBR0 PCI memory bank mask PCIMBMR0 register 0 PCI memory bank register 1 PCIMBR1 PCI memory bank mask PCIMBMR1 register 1 PCI memory bank register 2 PCIMBR2 PCI memory bank mask...
Page 590 13. PCI Controller (PCIC) Table 13.3 Register States in Each Processing Mode Name Control register space (physical address: H'FE00 0000 to H'FE03 FFFF) PCIC enable control register PCI configuration register space (physical address: H'FE04 0000 to H'FE04 00FF) PCI vendor ID register PCI device ID register PCI command register PCI status register...
Page 591 Name PCI power consumption/dissipation data register PCI local register space (physical address: H'FE04 0100 to H'FE04 03FF) PCI control register PCI local space register 0 PCI local space register 1 PCI local address register 0 PCI local address register 1 PCI interrupt register PCI interrupt mask register PCI error address information register...
Page 592: Pcic Enable Control Register (Pciecr)
13. PCI Controller (PCIC) 13.3.1 PCIC Enable Control Register (PCIECR) PCIECR is a register that specifies whether the PCIC is valid or invalid. Bit: — — — — Initial value: SH R/W: PCI R/W: — — — — Bit: — —...
Page 593: Configuration Registers
Description SH: R PCI Vender ID PCI: R These bits indicate the vender ID that is allocated by PCI-SIG. Renesas Technology's vendor ID is H'1912. Description SH: R PCI Device ID PCI: R These bits indicate the device ID of this LSI that is allocated by the vendor of a PCI device.
Page 594 13. PCI Controller (PCIC) PCI Command Register (PCICMD) PCICMD controls the basic functions of the PCIC to generate and respond to PCI cycles. When 0 is written to this register, this register ignores access commands from the external PCI device, other than configuration access.
Page 595 Initial Bit Name Value VGAPS MWIE Description SH: R/W Parity Error Response PCI: R/W Controls the response of the device when the PCIC detects a parity error or receives a parity error. When this bit is set to 1, the PERR signal is asserted. 0: Ignores parity error 1: Responds to parity error SH: R...
Page 596 13. PCI Controller (PCIC) PCI Status Register (PCISTATUS) PCISTATUS is used to record status information for events related to the PCI bus. The reserved bits are read-only bits that are read as 0. Reading from this register is normally performed. During writing, the write clear bit can be reset, but it cannot be set (R/WC in the figure below).
Page 597 Initial Bit Name Value 10, 9 DEVSEL MDPE FBBC Description SH: R/WC Target Abort Receive Status PCI: R/WC This bit indicates that a transaction was completed by target abort when the PCIC is a master. 0: Transaction is not completed with target abort 1: The bus master detected completion of transaction with target abort.
Page 598 13. PCI Controller (PCIC) Initial Bit Name Value ⎯ ⎯ 3 to 0 All 0 PCI Revision ID Register (PCIRID) PCIRID specifies a revision identifier specific to a PCI device. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value 7 to 0 H'xx...
Page 599 PCI Program Interface Register (PCIPIF) This field is the programming interface for the class code of the IDE controller. For details of the code value, see appendix D in PCI Local Bus Specification Revision 2.2. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name...
Page 600 13. PCI Controller (PCIC) Initial Bit Name Value PCI Sub Class Code Register (PCISUB) This field defines the sub class code. For details of the code value, see appendix D in PCI Local Bus Specification Revision 2.2. Bit: Initial value: SH R/W: PCI R/W: Initial...
Page 601 PCI Base Class Code Register (PCIBCC) This field defines the base class code. For details of the class code, see appendix D in PCI Local Bus Specification Revision 2.2. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value 7 to 0 H'xx PCI Cache Line Size Register (PCICLS)
Page 602 13. PCI Controller (PCIC) (10) PCI Latency Timer Register (PCILTM) Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value 7 to 0 H'00 (11) PCI Header Type Register (PCIHDR) Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value 6 to 0 H'00...
Page 603 (12) PCI BIST Register (PCIBIST) Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value BISTC ⎯ 6 to 0 All 0 — — — — BISTC Description SH: R This bit is used for the BIST function control and status.
Page 604 13. PCI Controller (PCIC) (13) PCI I/O Base Address Register (PCIIBAR) This register is the I/O space base address register of the PCI configuration register space header that is defined in PCI local bus specification. This register specifies the base address in the I/O space of the PCIC.
Page 605 (14) PCI Memory Base Address Register 0 (PCIMBAR0) This register is the memory base address register of the PCI configuration register space header that is defined in PCI local bus specification. PCIMBAR0 specifies the memory space 0 (local address space 0) in this LSI internal bus (SuperHyway bus). See section 13.4.4 (1), Accessing Memory Space in This LSI.
Page 606 13. PCI Controller (PCIC) Initial Bit Name Value 19 to 4 MBA2 H'0000 SH: R 2, 1 Rev.1.00 Jan. 10, 2008 Page 576 of 1658 REJ09B0261-0100 Description Memory Space 0 Base Address (lower 16 bits) PCI: R These bits are fixed to H'0000 by hardware. SH: R Prefetch Control PCI: R...
Page 607 (15) PCI Memory Base Address Register 1 (PCIMBAR1) This register is the memory base address register of the PCI configuration register space header that is defined in PCI local bus specification. PCIMBAR1 specifies the memory space 1 (local address space 1) in this LSI internal bus (SuperHyway bus). See section 13.4.4 (1), Accessing Memory Space in This LSI.
Page 608 13. PCI Controller (PCIC) Initial Bit Name Value 19 to 4 MBA2 H'0000 SH: R 2, 1 Rev.1.00 Jan. 10, 2008 Page 578 of 1658 REJ09B0261-0100 Description Memory Space 1 Base Address (lower 16 bits) PCI: R These bits are fixed to H'0000 by hardware. SH: R Prefetch Control PCI: R...
Page 609 (16) PCI Subsystem Vender ID Register (PCISVID) See the description of each register in PCI Local Bus Specification Revision 2.2. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value 15 to 0 SVID H'0000 SH: R/W (17) PCI Subsystem ID Register (PCISID) See description of each register in PCI Local Bus Specification Revision 2.2.
Page 610 13. PCI Controller (PCIC) (18) PCI Capability Pointer Register (PCICP) This register is the extension function pointer register of the PCI configuration register that is defined in the PCI Power Management Specification. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value 7 to 0...
Page 611 (20) PCI Interrupt Pin Register (PCIINTPIN) Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value 7 to 0 INTPIN H'01 (21) Minimum Grant Register (PCIMINGNT) This register is not programmable. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value 7 to 0...
Page 612 13. PCI Controller (PCIC) (22) Maximum Latency Register (PCIMAXLAT) This register is not programmable. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value 7 to 0 MAXLAT H'00 (23) PCI Capability Identifier Register (PCICID) Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name...
Page 613 (24) PCI Next Item Pointer Register (PCINIP) PCINIP indicates the location of the next item in the list of extension function. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value 7 to 0 H'00 Description SH: R Next Item Pointer PCI: R H'00: Indicates that power management function is listed as the last item.
Page 614 13. PCI Controller (PCIC) (25) PCI Power Management Register (PCIPMC) PCIPMC is a 16-bit register that provides information on the functions related to power management. For details, see section 3, PCI Power Management Interface in PCI Bus Power Management Interface Specification Revision 1.1. This register is not cleared by a power-on reset. This register must be set during initialization of register initialization in the PCIC (CFINIT = 0 in PCICR).
Page 615 Initial Bit Name Value ⎯ 8 to 6 All 0 ⎯ PMEC 2 to 0 Description SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. SH: R PCI: R The write value should always be 0. 0: Indicates that the proper initialization is not required SH: R Reserved...
Page 616 13. PCI Controller (PCIC) (26) PCI Power Management Control/Status Register (PCIPMCSR) This register manages power management events (PME) of the PCI function. For details, see section 3, PCI Power Management Interface in PCI Bus Power Management Interface Specification Revision 1.1. Bit: PMES Initial value:...
Page 617 Initial Bit Name Value 1, 0 Description SH: R/W Power State PCI: R/W These bits specify the power state. If an unsupported state is specified, a state transition is not made. However, the register is written normally and no error is indicated. 00: D0 state 01: D1 state 10: D2 state...
Page 618 13. PCI Controller (PCIC) (27) PCIPMCSR Bridge Support Extension Register (PCIPMCSRBSE) This register supports the functions specific to the PCI bridge and is required for all PCI-to-PCI bridges. Bit: Initial value: SH R/W: PCI R/W: Initial Bit Name Value BPCCEN B2B3N ⎯...
Page 619 (28) PCI Power Consumption/Radiation Register (PCIPCDD) The data register is an 8-bit optional register (read-only from the PCI bus) that notifies operation data such as power consumption depending on the state and heat dissipation. For details, see section 3, PCI Power Management Interface in PCI Bus Power Management Interface Specification Revision 1.1.
Page 620: Pci Local Registers
13. PCI Controller (PCIC) 13.3.3 PCI Local Registers PCI Control Register (PCICR) PCICR is a 32-bit register which controls the operation of the PCIC in this LSI. Writing to this register is valid only when the value of bits 31 to 24 are H'A5. Bit: —...
Page 621 Initial Bit Name Value ⎯ BMAM ⎯ 5 to 3 Description PCI TRDY/Control Enable SH: R/W Specifies the function that negates TRDY within 5 PCI: R cycles before disconnection in a target access. 0: Disabled 1: Enabled SH: R/W PCI Pre-Fetch Enable PCI: R Specifies whether pre-fetch is performed when a target memory access is performed by an external...
Page 622 13. PCI Controller (PCIC) Initial Bit Name Value IOCS RSTCTL CFINIT Rev.1.00 Jan. 10, 2008 Page 592 of 1658 REJ09B0261-0100 Description INTA Output SH: R/W Controls the INTA output by software. This bit is valid PCI: R only when the PCIC operates in normal mode. 0: The INTA pin is in the high-impedance state (driven high by an on-chip pull-up resistor) 1: Asserts INTA (output at low level)
Page 623 PCI Local Space Register 0 (PCILSR0) See section 13.4.4 (1), Accessing Memory Space in This LSI. Bit: — — — Initial value: SH R/W: PCI R/W: Bit: — — — — Initial value: SH R/W: PCI R/W: Initial Bit Name Value 31 to 29 ⎯...
Page 624 13. PCI Controller (PCIC) Initial Bit Name Value ⎯ 19 to 1 All 0 MBARE PCI Local Space Register 1 (PCILSR1) See section 13.4.4 (1), Accessing Memory Space in This LSI. Bit: — — — Initial value: SH R/W: PCI R/W: Bit: —...
Page 625 Initial Bit Name Value 28 to 20 LSR 0 0000 0000 ⎯ 19 to 1 All 0 MBARE Description SH: R/W Capacity of Local Address Spaces 1 (9 bits) PCI: R These bits specify the size of the local address space 1 (address space for this LSI internal bus) in byte units.
Page 626 13. PCI Controller (PCIC) PCI Local Address Register 0 (PCILAR0) See section 13.4.3 (2), Accessing PCI Memory Space. Bit: Initial value: SH R/W: PCI R/W: Bit: — — — — Initial value: SH R/W: PCI R/W: Initial Bit Name Value R/W 31 to 20 LAR H'000 SH: R/W PCI: R...
Page 627 PCI Local Address Register 1 (PCILAR1) See section 13.4.3 (2), Accessing PCI Memory Space. Bit: Initial value: SH R/W: PCI R/W: Bit: — — — — Initial value: SH R/W: PCI R/W: Initial Bit Name Value 31 to 20 LAR H'000 ⎯...
Page 628 13. PCI Controller (PCIC) PCI Interrupt Register (PCIIR) PCIIR records interrupt sources. When an interrupt occurs, the corresponding bit is set to 1. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, 1 is written to the corresponding bit by the interrupt source, and no interrupt occurs.
Page 629 Initial Bit Name Value TMTOI MDEI APEDI Description SH: R/WC Target Memory Read Retry Timeout Interrupt PCI: R Indicates that the master did not perform retry processing within 2 PCIC is a target. This bit is detected only for memory read transfers.
Page 630 13. PCI Controller (PCIC) Initial Bit Name Value DPEITW PEDITR Rev.1.00 Jan. 10, 2008 Page 600 of 1658 REJ09B0261-0100 Description SERR Detection Interrupt SH: R/WC Indicates that the assertion of SERR was detected PCI: R when the PCIC is a host. 0: A SERR detection interrupt was not generated 1: A SERR detection interrupt was generated When TTADI bit is write to 0, target target-abort...
Page 631 Initial Bit Name Value TADIM MADIM MWPDI Description SH: R/WC Target Abort Detection Interrupt for Master PCI: R Indicates that transaction was terminated by a target abort when the PCIC is a master. 0: A target abort interrupt was not generated when the PCIC is a master 1: A target abort interrupt was generated when the PCIC is a master...
Page 632 13. PCI Controller (PCIC) Initial Bit Name Value MRDPEI Rev.1.00 Jan. 10, 2008 Page 602 of 1658 REJ09B0261-0100 Description SH: R/WC Master Read Data Parity Error Interrupt PCI: R Indicates that the PCIC detected a parity error during data read from the target when the PCIC is a master. Note: A master read data parity error is detected only when bit 6 (PER) in PCICMD is set to 1.
Page 633 PCI Interrupt Mask Register (PCIIMR) This register is the mask register for PCIIR. Bit: — — — — Initial value: SH R/W: PCI R/W: Bit: — — — Initial value: SH R/W: PCI R/W: Initial Bit Name Value 31 to 15 ⎯ All 0 TTADIM 13 to 10 ⎯...
Page 634 13. PCI Controller (PCIC) Initial Bit Name Value SDIM DPEITWM 0 PEDITRM TADIMM MADIMM MWPDIM MRDPEIM 0 Rev.1.00 Jan. 10, 2008 Page 604 of 1658 REJ09B0261-0100 Description SERR Detection Interrupt Mask SH: R/W PCI: R 0: SEDI disabled (masked) 1: SEDI enabled (not masked) SH: R/W Data Parity Error Interrupt Mask for Target Write PCI: R...
Page 635 PCI Error Address Information Register (PCIAIR) This register records PCI address information when an error is detected. The value of this register is undefined until an interrupt is detected. Regardless of the information on mask registers, etc, the value is retained when an interrupt is detected. Bit: Initial value: SH R/W:...
Page 636 13. PCI Controller (PCIC) PCI Error Command Information Register (PCICIR) This register records the PCI command information when an error is detected. The value of this register is undefined until an interrupt is detected. Regardless of the information on mask registers, etc, the value is retained when an interrupt is detected. Bit: MTEM —...
Page 637 (10) PCI Arbiter Interrupt Register (PCIAINT) In host mode, this register records interrupt sources. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, the source is written to the corresponding bit in this register, and, no interrupt occurs. Bit: —...
Page 638 13. PCI Controller (PCIC) Initial Bit Name Value MBTOI ⎯ 10 to 4 All 0 RDPEI WDPEI Rev.1.00 Jan. 10, 2008 Page 608 of 1658 REJ09B0261-0100 Description SH: R/WC Master Bus Time-Out Interrupt An interrupt is detected when IRDY is not asserted PCI: R within 8 clock cycles during data transfer.
Page 639 (11) PCI Arbiter Interrupt Mask Register (PCIAINTM) This register is the mask register for PCIAINT. Bit: — — — — Initial value: SH R/W: PCI R/W: Bit: — — MBIM Initial value: SH R/W: R/WC R/WC PCI R/W: Initial Bit Name Value 31 to 14 ⎯...
Page 640 13. PCI Controller (PCIC) Initial Bit Name Value MAIM RDPEIM WDPEIM (12) PCI Arbiter Bus Master Information Register (PCIBMIR) In host mode, this register records when the interrupt is generated by PCIAINT. When multiple interrupts occur, only the first source is registered. When an interrupt is disabled, the source is registered in the corresponding bit, and no interrupt occurs.
Page 641 Initial Bit Name Value ⎯ 31 to 5 All 0 REQ3BME x REQ2BME x REQ1BME x REQ0BME x PCICBME x Description SH: R Reserved PCI: R These bits are always read as 0. The write value should always be 0. SH: R REQ3 Error PCI: R...
Page 642 13. PCI Controller (PCIC) (13) PCI PIO Address Register (PCIPAR) Setting this register generates configuration cycles on the PCI bus. For details, see section 13.4.5 (2), Configuration Space Access. Bit: CCIE — — — Initial value: SH R/W: PCI R/W: —...
Page 643 Initial Bit Name Value 15 to 11 DN xxxxx 10 to 8 7 to 2 xxxxxx ⎯ 1, 0 All 0 Description SH: R/W Device Number PCI: ⎯ These bits specify a device number for the configuration access target. A device number is represented by a 5-bit value in the range from 0 to 31.
Page 644 13. PCI Controller (PCIC) (14) PCI Power Management Interrupt Register (PCIPINT) This register registers power management interrupt sources. Bit: — — — — Initial value: SH R/W: PCI R/W: — — — — Bit: — — — — Initial value: SH R/W: PCI R/W: —...
Page 645 Initial Bit Name Value PMD0 (15) PCI Power Management Interrupt Mask Register (PCIPINTM) This register is the mask register for PCIPINT. Bit: — — — — Initial value: SH R/W: PCI R/W: — — — — Bit: — — — —...
Page 646 13. PCI Controller (PCIC) Initial Bit Name Value PMD1M PMD0M (16) PCI Memory Bank Register 0 (PCIMBR0) This register specifies the upper 14 bits of the memory space address on the PCI bus for a memory read or write to the PCI memory space 0 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
Page 647 (17) PCI Memory Bank Mask Register 0 (PCIMBMR0) This register is the mask register for PCIMBR0. This register specifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 0 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
Page 648 13. PCI Controller (PCIC) (18) PCI Memory Bank Register 1 (PCIMBR1) This register specifies the upper 14 bits of the memory space address on the PCI bus for a memory read or write to the PCI memory space 1 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
Page 649 (19) PCI Memory Bank Mask Register 1 (PCIMBMR1) This register is the mask register for PCIMBR1. This register specifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 1 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
Page 650 13. PCI Controller (PCIC) (20) PCI Memory Bank Register 2 (PCIMBR2) This register specifies the upper 14 bits of the memory space address on the PCI bus for a memory read or write to the PCI memory space 2 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
Page 651 (21) PCI Memory Bank Mask Register 2 (PCIMBMR2) This register is the mask register for PCIMBR2. This register specifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 2 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
Page 652 13. PCI Controller (PCIC) (22) PCI I/O Bank Register (PCIIOBR) This register specifies the upper 14 bits of the I/O space address on the PCI bus for an I/O-read or I/O-write to the PCI I/O space by the CPU or DMAC. See section 13.4.3 (3), Accessing PCI I/O Space.
Page 653 (23) PCI I/O Bank Mask Register (PCIIOBMR) This register is the mask register for PCIIOBR. This register specifies the I/O space size on the PCI bus for an I/O-read or I/O-write to the PCI I/O space by the CPU or DMAC. See section 13.4.3 (3), Accessing PCI I/O Space.
Page 654 13. PCI Controller (PCIC) (24) PCI Cache Snoop Control Register 0 (PCICSCR0) An external PCI device can access memory of this LSI via the PCIC. When an PCI device accesses a cacheable area, the PCIC can issue cache snoop commands to the on-chip caches. This register can specify the function that uses PCICSAR0.
Page 655 Initial Bit Name Value 1, 0 SNPMD All 0 (25) PCI Cache Snoop Control Register 1 (PCICSCR1) An external device can access memory of this LSI via the PCIC. When an PCI device accesses a cacheable area, the PCIC can issue cache snoop commands to the on-chip caches. This register can specify the function that uses PCICSAR1.
Page 656 13. PCI Controller (PCIC) Initial Bit Name Value ⎯ 31 to 5 All 0 4 to 2 RANGE All 0 1, 0 SNPMD All 0 Rev.1.00 Jan. 10, 2008 Page 626 of 1658 REJ09B0261-0100 Description SH: R Reserved PCI: — These bits are always read as 0.
Page 657 (26) PCI Cache Snoop Address Register 0 (PCICSAR0) This register specifies the address to be compared with the PCI address requested by an external PCI device to the PCIC. For details, see section 13.4.4 (7), Cache Coherency. Bit: Initial value: SH R/W: PCI R/W: Bit:...
Page 658 13. PCI Controller (PCIC) (27) PCI Cache Snoop Address Register 1 (PCICSAR1) This register specifies the address to be compared with the PCI address requested by an external PCI device to the PCIC. For details, see section 13.4.4 (7), Cache Coherency. Bit: Initial value: SH R/W:...
Page 659 (28) PCI PIO Data Register (PCIPDR) By reading or writing to this register, a configuration cycle is generated on the PCI bus. For details, see section 13.4.5 (2), Configuration Space Access. Bit: Initial value: SH R/W: PCI R/W: — — —...
Page 660: Supported Pci Commands
13. PCI Controller (PCIC) 13.4 Operation 13.4.1 Supported PCI Commands Table 13.4 Supported PCI Commands C/BE[3:0] Commands 0000 Interrupt acknowledge cycle 0001 Special cycle 0010 I/O read 0011 I/O write 0100 Reserved 0101 Reserved 0110 Memory read 0111 Memory write 1000 Reserved 1001...
Page 661: Pcic Initialization
13. PCI Controller (PCIC) 13.4.2 PCIC Initialization After a power-on reset, the ENBL bit in PCIECR and the CFINIT bit in PCICR are cleared. At this time, if the PCIC operates as the PCI bus host (host mode), device arbitration is not performed on the PCI bus, and the bus mastership is always granted to the PCIC.
Page 662: Master Access
13. PCI Controller (PCIC) 13.4.3 Master Access This section describes how software controls the PCI when the PCIC is a bus master. This section describes the cases where the PCIC is used in both host mode and normal mode. Address Map Table 13.5 shows the PCIC address map.
Page 663 Accessing PCI Memory Space Figure 13.2 shows the memory map from the SuperHyway bus to the PCI bus. SHwy bus address space (4 GB) H'0000 0000 H'1000 0000 H'C000 0000 H'FD00 0000 H'FE00 0000 H'FE20 0000 Figure 13.2 Memory Map from SuperHyway Bus to PCI Bus To access the PCI memory space, use PCIMBR and PCIMBMR.
Page 664 13. PCI Controller (PCIC) For PCI memory space 0, the middle six bits ([23:18]) are controlled by PCIMBMR0. • PCIMBMR0 [23:18] B'1111 11: PCI address [23:18] = SuperHyway bus address [23:18] • PCIMBMR0 [23:18] B'0000 00: PCI address [23:18] = PCIMBR0 [23:18] The upper eight bits ([31:24]) of a SuperHyway bus address are replaced with bits 31 to 24 in PCIMBR0.
Page 665 For PCI memory space 2 accesses, the middle eleven bits ([28:18]) are controlled by PCIMBMR2. • PCIMBMR2 [28:18] B'1 1111 1111 11: PCI address [28:18] = SuperHyway bus address [28:18] • PCIMBMR2 [28:18] B'0 0000 0000 00: PCI address [28:18] = PCIMBR2 [28:18] The upper three bits ([31:29]) of a SuperHyway bus address are replaced with bits 31 to 29 in PCIMBR2.
Page 666 13. PCI Controller (PCIC) Accessing PCI I/O Space Burst transfers are not supported in I/O transfers. Access within the size of 4-byte. The PCI I/O address space is allocated from H'FD20 0000 to H'FE3F FFFF (2 Mbytes). Address translation from SuperHyway bus to PCI local bus is shown below. The lower 15 bits ([17:3]) of a SuperHyway bus address are sent without translation.
Page 667 1. Little endian SHwy data Buffer data PCI_Addr[2] = 1 PCI bus data 2. Big endian SHwy data Buffer data PCI_Addr[2] = 0 PCI bus data Note: PCIAddr[2]: PCI Figure 13.7 Endian Conversion from SuperHyway Bus to PCI Bus (Non-Byte Swapping: TBS = 0) A' B' C' D' A B A' B' C' D' A B PCI_Addr[2] = 0...
Page 668 13. PCI Controller (PCIC) Note: PCIAddr[2]: PCI Figure 13.8 Endian Conversion from SuperHyway Bus to PCI Local Bus Rev.1.00 Jan. 10, 2008 Page 638 of 1658 REJ09B0261-0100 1. Little endian SHwy data A' B' C' D' A B C A' B' C' D' A B C Buffer data PCI_Addr[2] = 1 PCI bus data...
Page 669 SHwy bus Size Address Data 4n + 0 4n + 1 Byte 4n + 2 4n + 3 4n + 0 Word 4n + 2 long- 4n + 0 word Figure 13.9 Data Alignments for SuperHyway Bus and PCI Bus PCI bus Big-endian CPU Data (without swapping) Data (with swapping)
Page 670: Target Access
13. PCI Controller (PCIC) 13.4.4 Target Access This section describes how the PCIC in this LSI is accessed by an external PCI local bus master when the PCIC is used in both the host mode and normal mode. Accessing Memory Space in This LSI Accesses to the PCIC in this LSI by an external PCI bus master are described below.
Page 671 13. PCI Controller (PCIC) To access the address space in this LSI, use PCIMBAR0/1, PCILSR0/1, and PCILAR0/1. PCI addresses can be allocated to by software. The PCIC has two types of registers for memory mapping, Local Address Space 0 (base 0) and Local Address Space 1 (base 1). By setting these two registers, two types of spaces (bases) can be allocated.
Page 672 13. PCI Controller (PCIC) PCI address Compare PCIMBAR0/1 PCILSR0/1 Figure 13.11 PCI Bus to SuperHyway Bus Address Translation Accessing PCIC I/O Space The PCI I/O address space should be allocated as 256 bytes. The lower eight bits ([7:0]) are sent to the internal bus without translation. When bits 31 to 8 of a PCI address match bits 31 to 8 of PCIIBAR, the upper 24 bits are replaced with H'FE04 01 and a PCI local register is accessed.
Page 673 Accessing PCIC Registers Configuration Registers: Configuration registers should be read or written with (offset from configuration register space base address) by configuration accesses. A burst transfer is cut off and terminated. Local Registers: Local registers should be accessed with (PCI address + offset) using I/O read or write commands.
Page 674 13. PCI Controller (PCIC) Endian This LSI supports both the big and little endian formats. Since the PCI local bus is inherently little endian, the PCIC supports both byte swapping and non-byte swapping. The endian format is specified by the TBS bit in PCICR. Note: PCIAddr[2]: PCI bus AD[2] Figure 13.13 Endian Conversion from PCI Bus to SuperHyway Bus Rev.1.00 Jan.
Page 675 1. Little endian PCI bus data PCI_Addr[2] = 1 Buffer data SHwy data 2. Big endian PCI bus data PCI_Addr[2] = 0 Buffer data SHwy data Note: PCIAddr[2]: PCI bus AD[2] Figure 13.14 Endian Conversion from PCI Bus to SuperHyway Bus (Byte Swapping: TBS = 1) A B C D PCI_Addr[2] = 0...
Page 676 13. PCI Controller (PCIC) PCI bus Size Address 4n + 0 4n + 1 Byte 4n + 2 4n + 3 4n + 0 Word 4n + 2 Long- 4n + 0 word Figure 13.15 Data Alignments for SuperHyway Bus and PCI Bus Rev.1.00 Jan.
Page 677 Cache Coherency The PCIC supports cache coherency function. When the PCIC functions as a target device, cache coherency is guaranteed on the PCI bus for accesses from a master device both in host mode and normal mode. When a cacheable area of this LSI is accessed, PCICSCR0/1 and PCICSAR0/1 should be set.
Page 678: Host Mode
13. PCI Controller (PCIC) 13.4.5 Host Mode Operation in Host Mode The PCI interface of this LSI supports a subset of the PCI version 2.2 and can be connected to a device with a PCI bus interface. According to the PCIC mode, host mode or normal mode, operation differs in two points: (1) the PCIC unconditionally performs bus parking or not, and (2) the PCI bus arbitration function is enabled or disabled.
Page 679 Configuration address register PCI bus address Figure 13.17 Address Generation for Type 0 Configuration Access In configuration accesses, no interrupt is generated by a PCI master abort (no device connected). A configuration write will end normally. A configuration read will return a value of 0. Arbitration In host mode, the PCI bus arbiter in the PCIC is activated.
Page 680 13. PCI Controller (PCIC) Subsequently, after the PCIC requires the bus and transfer data and the request is permitted, the priority changes as follows: Device 0 > device 2 > device 3 > device 1 > PCIC Then, after the device 3 requires the bus and transfer data and the request is permitted, the priority changes as follows: Device 0 >...
Page 681: Normal Mode
The PCIC can retain error information on the PCI bus. When an error occurs, the error address is stored in PCIAIR and the transfer type and command information are stored in PCICIR. When the PCIC is in host mode, the bus master information at the error occurrence is stored in PCIBMIR. The PCIC can retain only one error information.
Page 682 13. PCI Controller (PCIC) (Nomal state) (Bus idle) Figure 13.18 Power Down State Transitions on PCI Bus When the PCIC detects that the power state (PS) bit in PCIPMCSR changes (PS is written by an external PCI device), it issues a power management interrupt. PCIPINT and PCIPINTM are used to control the power management interrupts.
Page 683: Pci Local Bus Basic Interface
13.4.8 PCI Local Bus Basic Interface The PCI interface of this LSI supports subsets in the PCI bus version 2.2 and it can be connected to a device with a PCI bus interface. The following figures show the timing in each operating mode.
Page 684 13. PCI Controller (PCIC) PCICLK AD[31:0] C/BE[3:0] PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL Legend: Addr: PCI space address nth data Figure 13.20 Master Read Cycle in Host Mode (Single) Rev.1.00 Jan. 10, 2008 Page 654 of 1658 REJ09B0261-0100 Addr AP: Address parity Com: Command BEn: nth data byte enable DPn: nth data parity...
Page 685 PCICLK AD[31:0] C/BE[3:0] PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQOUT GNTIN Legend: Addr: PCI space address AP: Address parity nth data DPn: nth data parity Figure 13.21 Master Write Cycle in Normal Mode (Burst) Addr DPn-1 Com: Command BEn: nth data byte enable Rev.1.00 Jan.
Page 686 13. PCI Controller (PCIC) PCICLK AD[31:0] C/BE[3:0] PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQOUT GNTIN Legend: Addr: PCI space address nth data Figure 13.22 Master Read Cycle in Normal Mode (Burst) Rev.1.00 Jan. 10, 2008 Page 656 of 1658 REJ09B0261-0100 Addr AP: Address parity Com: Command...
Page 687 13. PCI Controller (PCIC) Target Read/Write Cycle Timing The PCIC returns retries to target memory read accesses from an external master until 8 longword (32-bit) data are prepared in the PCIC internal FIFO. That is, the first target read is always responded by a retry.
Page 688 13. PCI Controller (PCIC) PCICLK AD[31:0] C/BE[3:0] PCIFRAME IRDY DEVSEL TRDY STOP LOCK IDSEL REQOUT GNTIN Legend: Addr: PCI space address nth data Figure 13.23 Target Read Cycle in Normal Mode (Single) Rev.1.00 Jan. 10, 2008 Page 658 of 1658 REJ09B0261-0100 Addr Lock...
Page 689 PCICLK Addr AD[31:0] C/BE[3:0] PCIFRAME IRDY DEVSEL TRDY STOP LOCK IDSEL REQOUT GNTIN Legend: Addr: PCI space address AP: Address parity nth data DPn: nth data parity Figure 13.24 Target Write Cycle in Normal Mode (Single) Lock Configuration space access Com: Command BEn: nth data byte enable Rev.1.00 Jan.
Page 690 13. PCI Controller (PCIC) PCICLK AD[31:0] C/BE[3:0] PCIFRAME IRDY DEVSEL TRDY STOP LOCK IDSEL Legend: Addr: PCI space address nth data Figure 13.25 Target Memory Read Cycle in Host Mode (Burst) Rev.1.00 Jan. 10, 2008 Page 660 of 1658 REJ09B0261-0100 Addr Disconnect Lock...
Page 691 PCICLK Addr AD[31:0] C/BE[3:0] PCIFRAME IRDY DEVSEL TRDY STOP LOCK IDSEL Legend: Addr: PCI space address AP: Address parity nth data DPn: nth data parity Figure 13.26 Target Memory Write Cycle in Host Mode (Burst) DPn-1 DPn Disconnect Lock Com: Command BEn: nth data byte enable Rev.1.00 Jan.
Page 692 13. PCI Controller (PCIC) Address/Data Stepping Timing By writing 1 to the SC bit in PCICMD, a wait (stepping) of one clock can be inserted when the PCIC is driving the AD bus. As a result, the PCIC drives the AD bus with 2 clocks. This function can be used when the PCI bus load is heavy and the AD bus does not achieve the stipulated logic level in one clock.
Page 693 PCICLK AD[31:0] C/BE[3:0] PCIFRAME IRDY DEVSEL TRDY Legend: Addr: PCI space address nth data Figure 13.28 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with Stepping) Addr AP: Address parity Com: Command BEn: nth data byte enable DPn: nth data parity Rev.1.00 Jan.
Page 694 13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 664 of 1658 REJ09B0261-0100...
Page 695: Section 14 Direct Memory Access Controller (Dmac)
Section 14 Direct Memory Access Controller (DMAC) This LSI includes an on-chip direct memory access controller (DMAC). Instead of the CPU, the DMAC can be used to perform data transfers among external devices equipped with DACK (transfer request acceptance signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules.
Page 696 14. Direct Memory Access Controller (DMAC) Figure 14.1 shows a block diagram of the DMAC. On-chip memory On-chip Peripheral peripheral bus controller module DMA transfer request signal DMA transfer end signal DMINT0 to DMINT11 DMAE0 Interrupt controller DMAE1 DREQ0 to DREQ3 DRAK0 to DRAK3 DACK0 to DACK3 External ROM...
Page 697: Input/Output Pins
14.2 Input/Output Pins The DMAC-related external pins are shown below. Table 14.1 shows the configuration of the pins that are connected to external device. The DMAC has pins for four channels (channels 0 to 3) used in the external bus. Table 14.1 Pin Configuration for the External Bus Channel Function DMA transfer request...
Page 698: Register Descriptions
14. Direct Memory Access Controller (DMAC) 14.3 Register Descriptions Table 14.2 shows the register configuration. Table 14.2 Register Configuration of the DMAC (1) Channel Name DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 DMA source address register 1 DMA destination address register 1...
Page 699 Channel Name DMA source address register B0 DMA destination address register B0 DARB0 DMA transfer count register B0 DMA source address register B1 DMA destination address register B1 DARB1 DMA transfer count register B1 DMA source address register B2 DMA destination address register B2 DARB2 DMA transfer count register B2 DMA source address register B3 DMA destination address register B3 DARB3...
Page 700 14. Direct Memory Access Controller (DMAC) Channel Name 6 to 11 DMA operation register 1 DMA source address register 10 DMA destination address register 10 DAR10 DMA transfer count register 10 DMA channel control register 10 DMA source address register 11 DMA destination address register 11 DAR11 DMA transfer count register 11 DMA channel control register 11...
Page 701 Table 14.2 Register Configuration of the DMAC (2) Channel Name DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0 DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1 DMA source address register 2...
Page 702 14. Direct Memory Access Controller (DMAC) Channel Name DMA source address register B0 DMA destination address register DMA transfer count register B0 DMA source address register B1 DMA destination address register DMA transfer count register B1 DMA source address register B2 DMA destination address register DMA transfer count register B2 DMA source address register B3...
Page 703 Channel Name DMA source address register 8 DMA destination address register 8 DMA transfer count register 8 DMA channel control register 8 DMA source address register 9 DMA destination address register 9 DMA transfer count register 9 DMA channel control register 9 6 to 11 DMA operation register 1 DMA source address register 10...
Page 704 14. Direct Memory Access Controller (DMAC) Channel Name DMA source address register B9 DMA destination address register DMA transfer count register B9 6, 7 DMA extended resource selector 3 8, 9 DMA extended resource selector 4 10, 11 DMA extended resource selector 5 Rev.1.00 Jan.
Page 705: Dma Source Address Registers 0 To 11 (Sar0 To Sar11)
14.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11) SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the source address of the next transfer. A word or longword boundary address should be specified when a word or longword transfer is performed respectively.
Page 706 14. Direct Memory Access Controller (DMAC) 14.3.2 DMA Source Address Registers B0 to B3, B6 to B9 (SARB0 to SARB3, SARB6 to SARB9) SARB are 32-bit readable/writable registers that specify the source address of a DMA transfer that is set in SAR again in repeat/reload mode. The data written to SAR by the CPU is also written to SARB.
Page 707: Dma Destination Address Registers 0 To 11 (Dar0 To Dar11)
14.3.3 DMA Destination Address Registers 0 to 11 (DAR0 to DAR11) DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the destination address of the next transfer. A word or longword boundary address should be specified when a word or longword transfer is performed respectively.
Page 708 14. Direct Memory Access Controller (DMAC) 14.3.4 DMA Destination Address Registers B0 to B3, B6 to B9 (DARB0 to DARB3, DARB6 to DARB9) DARB are 32-bit readable/writable registers that specify the destination address of a DMA transfer that is set in DAR again in repeat/reload mode. The data written to DAR by the CPU is also written to DARB.
Page 709: Dma Transfer Count Registers 0 To 11 (Tcr0 To Tcr11)
14.3.5 DMA Transfer Count Registers 0 to 11 (TCR0 to TCR11) TCR are 32-bit readable/writable registers that specify the DMA transfer count. When the value is set to H'00000001, H'00FFFFFF, H'00000000, the transfer count is 1, 16,777,215, and 16,777,216 (the maximum) respectively. During a DMA transfer, these registers indicate the remaining transfer count.
Page 710 14. Direct Memory Access Controller (DMAC) 14.3.6 DMA Transfer Count Registers B0 to B3, B6 to B9 (TCRB0 to TCRB3, TCRB6 to TCRB9) TCRB are 32-bit readable/writable registers. The data written to TCR by the CPU is also written to TCRB. While the half end function is being used, TCRB are used as the initial value retain registers to detect half end.
Page 711: Dma Channel Control Registers 0 To 11 (Chcr0 To Chcr11)
14.3.7 DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11) CHCR are 32-bit readable/writable registers that control the DMA transfer mode. Bit: LCKN Initial value: R/W: Bit: DM[1:0] SM[1:0] Initial value: R/W: Note: * R/(W): To clear the flag, 0 can be written to. Initial Bit Name Value...
Page 712 14. Direct Memory Access Controller (DMAC) Initial Bit Name Value 27 to 25 RPT[2:0] ⎯ Rev.1.00 Jan. 10, 2008 Page 682 of 1658 REJ09B0261-0100 Descriptions DMA Setting Update Specification These bits are valid in only CHCR0 to CHCR3, and CHCR6 to CHCR9. 000: Normal mode 001: Repeat mode SAR/DAR/TCR are repeated...
Page 713 Initial Bit Name Value ⎯ 14. Direct Memory Access Controller (DMAC) Descriptions Reserved This bit is always read as 0. The write value should always be 0. DMA Transfer Size Specification Specifies the DMA transfer size with TS1 and TS0. When the transfer source or transfer destination is a register in an on-chip peripheral module register that the access size is specified, the transfer data size for...
Page 714 14. Direct Memory Access Controller (DMAC) Initial Bit Name Value Rev.1.00 Jan. 10, 2008 Page 684 of 1658 REJ09B0261-0100 Descriptions R/(W)* Half End Flag After HIE (bit 18) is set to 1 and the number of transfers is half of TCR (one bit shift to right) which is set before transfer, HE is 1.
Page 715 Initial Bit Name Value 14. Direct Memory Access Controller (DMAC) Descriptions Acknowledge Mode Selects whether DACK is output in a data read cycle or in a data write cycle. DACK is output only for LBSC space transfers. This bit is valid in only CHCR0 to CHCR3. 0: DACK output in a read cycle (DACK is output only when the DMA transfer source is LBSC space.)
Page 716 14. Direct Memory Access Controller (DMAC) Initial Bit Name Value 15, 14 DM[1:0] 13, 12 SM[1:0] Rev.1.00 Jan. 10, 2008 Page 686 of 1658 REJ09B0261-0100 Descriptions Destination Address Mode 1, 0 Specify whether the DMA destination address is incremented or decremented. 00: Destination address is fixed 01: Destination address is incremented byte unit transfer: +1...
Page 717 Initial Bit Name Value 11 to 8 RS[3:0] 0000 4, 3 TS[1:0] 14. Direct Memory Access Controller (DMAC) Descriptions Resource Select 3 to 0 Specify the transfer request source. To change the transfer request source, the DMA enable (DE) bit should be cleared to 0.
Page 718 14. Direct Memory Access Controller (DMAC) Initial Bit Name Value Note: To clear the flag, 0 can be written to. Rev.1.00 Jan. 10, 2008 Page 688 of 1658 REJ09B0261-0100 Descriptions Interrupt Enable Specifies whether an interrupt request is generated to the CPU at the end of the final DMA transfer.
Page 719: Dma Operation Register 0, 1 (Dmaor0 And Dmaor1)
14.3.8 DMA Operation Register 0, 1 (DMAOR0 and DMAOR1) DMAOR are 16-bit readable/writable registers that specify the priority of channels in DMA transfer. Also, these registers show the DMA transfer status. DMAOR 0 is a register common to channels 0 to 5, and DMAOR1 is a register common to channels 6 to11.
Page 720 14. Direct Memory Access Controller (DMAC) Initial Bit Name Value ⎯ 11, 10 All 0 9, 8 PR[1:0] ⎯ 7 to 3 All 0 Rev.1.00 Jan. 10, 2008 Page 690 of 1658 REJ09B0261-0100 Descriptions Reserved These bits are always read as 0. The write value should always be 0.
Page 721 Initial Bit Name Value NMIF 14. Direct Memory Access Controller (DMAC) Descriptions R/(W)* Address Error Flag Indicates that an address error occurred during DMA transfer. This bit is set under following conditions. • The value set in SAR or DAR does not match to the transfer size boundary.
Page 722 14. Direct Memory Access Controller (DMAC) Initial Bit Name Value Note: To clear the flag, 0 can be written to. Rev.1.00 Jan. 10, 2008 Page 692 of 1658 REJ09B0261-0100 Descriptions DMA Master Enable Enables or disables DMA transfers on all channels (channels 0 to 5) corresponding to DMAOR0, and all channels (channels 6 to 11) corresponding to DMAOR1.
Page 723: Dma Extended Resource Selectors 0 To 5 (Dmars0 To Dmars5)
14.3.9 DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5) DMARS are 16-bit readable/writable registers. DMARS0, DMARS1, DMARS2, DMARS3, DMARS4, and DMARS5 specify DMA transfer request source from peripheral modules for channels 0 and 1, channels 2 and 3, channels 4 and 5, channels 6 and 7, channels 8 and 9, and channels 10 and 11 respectively.
Page 724 14. Direct Memory Access Controller (DMAC) • DMARS4 Bit: Ch9MID Initial value: R/W: • DMARS5 Bit: Ch11MID Initial value: R/W: • DMARS0 Initial Bit Name Value C1MID5 C1MID4 C1MID3 C1MID2 C1MID1 C1MID0 C1RID1 C1RID0 C0MID5 C0MID4 C0MID3 C0MID2 C0MID1 C0MID0 C0RID1 C0RID0 Rev.1.00 Jan.
Page 725 • DMARS1 Initial Bit Name Value C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 C3RID1 C3RID0 C2MID5 C2MID4 C2MID3 C2MID2 C2MID1 C2MID0 C2RID1 C2RID0 14. Direct Memory Access Controller (DMAC) Descriptions Transfer request source module ID5 to ID0 for DMA channel 3 (MID) See table 14.3.
Page 726 14. Direct Memory Access Controller (DMAC) • DMARS2 Initial Bit Name Value C5MID5 C5MID4 C5MID3 C5MID2 C5MID1 C5MID0 C5RID1 C5RID0 C4MID5 C4MID4 C4MID3 C4MID2 C4MID1 C4MID0 C4RID1 C4RID0 Rev.1.00 Jan. 10, 2008 Page 696 of 1658 REJ09B0261-0100 Descriptions Transfer request source module ID5 to ID0 for DMA channel 5 (MID) See table 14.3.
Page 727 • DMARS3 Initial Bit Name Value C7MID5 C7MID4 C7MID3 C7MID2 C7MID1 C7MID0 C7RID1 C7RID0 C6MID5 C6MID4 C6MID3 C6MID2 C6MID1 C6MID0 C6RID1 C6RID0 14. Direct Memory Access Controller (DMAC) Descriptions Transfer request source module ID5 to ID0 for DMA channel 7 (MID) See table 14.3.
Page 728 14. Direct Memory Access Controller (DMAC) • DMARS4 Initial Bit Name Value C9MID5 C9MID4 C9MID3 C9MID2 C9MID1 C9MID0 C9RID1 C9RID0 C8MID5 C8MID4 C8MID3 C8MID2 C8MID1 C8MID0 C8RID1 C8RID0 Rev.1.00 Jan. 10, 2008 Page 698 of 1658 REJ09B0261-0100 Descriptions Transfer request source module ID5 to ID0 for DMA channel 9 (MID) See table 14.3.
Page 729 • DMARS5 Initial Bit Name Value C11MID5 C11MID4 C11MID3 C11MID2 C11MID1 C11MID0 C11RID1 C11RID0 C10MID5 C10MID4 C10MID3 C10MID2 C10MID1 C10MID0 C10RID1 C10RID0 14. Direct Memory Access Controller (DMAC) Descriptions Transfer request source module ID5 to ID0 for DMA channel 11 (MID) See table 14.3.
Page 730 14. Direct Memory Access Controller (DMAC) Table 14.3 List of Transfer Request Sources Peripheral Setting Value for One Module Channel (MID and RID fields) MID SSI0 H'03 SSI1 H'07 SCIF0 H'21 H'22 SCIF1 H'25 H'26 SCIF2 H'29 H'2A SCIF3 H'2D H'2E SCIF4 H'31...
Page 731: Dma Transfer Requests
14.4 Operation When DMA transfer is requested, the DMAC starts transfer according to the determined channel priority. When the transfer end conditions are satisfied, the DMAC ends transfer. Transfer requests have three modes: auto-request mode, external request mode, and on-chip peripheral module request mode.
Page 732 14. Direct Memory Access Controller (DMAC) Choose whether DREQ is detected by edge or level with the DREQ level (DL) bit and DREQ select (DS) bit in CHCR0 to CHCR3 shown in table 14.5. The source of the transfer request does not have to be the transfer source or transfer destination.
Page 733 14. Direct Memory Access Controller (DMAC) On-Chip Peripheral Module Request Mode On-chip peripheral module request mode is a mode that performs transfer by DMA transfer request signal from an on-chip peripheral module. DMA transfer request signals include a transmit data empty transfer request and receive data full transfer request that are from the SCIF0 to SCIF5, HAC0, HAC1, HSPI, SIOF, SSI0, SSI1, and MMCIF set in DMARS0 to DMARS5, and a transfer request from the FLCTL.
Page 734 14. Direct Memory Access Controller (DMAC) Table 14.8 List of On-Chip Peripheral Module Request Modes CHCR DMARS DMA Transfer RS[3:0] MID Request Source DMA Transfer Request Signal Source 1000 000000 11 SSI0 transmitter SSI0 receiver 000001 11 SSI1 transmitter SSI1 receiver 001000 01 SCIF0 transmitter TXI (transmit FIFO data empty) Any SCIF0 receiver...
Page 735 CHCR DMARS DMA Transfer Request Source DMA Transfer Request Signal Source RS[3:0] MID 1000 001101 01 SCIF5 transmitter TXI (transmit FIFO data empty) Any SCIF5 receiver 010000 01 HAC0 transmitter Transmit data empty request HAC0 receiver 010001 01 HAC1 transmitter Transmit data empty request HAC1 receiver 010100 01 SIOF transmitter...
Page 736: Channel Priority
14. Direct Memory Access Controller (DMAC) 14.4.2 Channel Priority When the DMAC receives transfer requests on two or more channels simultaneously, it transfers data according to a determined priority. Modes are chosen from among fixed mode and round- robin mode. Modes are selected by bits PR1 and PR0 in DMAOR0 (channels 0 to 5) and DMAOR1 (channels 6 to 11).
Page 737 (1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Priority order CH1 > CH2 > CH3 > CH4 > CH5 > CH0 after transfer (2) When channel 1 transfers Initial priority order CH0 >...
Page 738 14. Direct Memory Access Controller (DMAC) Figure 14.3 shows how the priority changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1.
Page 739: Dma Transfer Types
14.4.3 DMA Transfer Types Tables 14.9 and 14.10 show the transfer directions that can be supported by the DMAC. DMA transfer type supports dual address mode. A data transfer timing depends on the bus mode. Bus modes include cycle steal mode and burst mode. Table 14.9 DMA Transfer Directions for Auto-Request and External Request* LBSC Transfer Source...
Page 740 14. Direct Memory Access Controller (DMAC) Table 14.10 DMA Transfer Directions for On-Chip Peripheral Module Request* LBSC Transfer Source Space LBSC Space DBSC Space PCIC Space On-Chip Peripheral Module* L or U Memory Legend: Y: Transfer is enabled. N: Transfer is disabled. Notes: 1.
Page 741 Dual Address Mode In dual address mode, both the transfer source and transfer destination are accessed by address. The source and destination can be specified externally or internally. Data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle, and two bus cycles are required to execute DMA transfer.
Page 742 14. Direct Memory Access Controller (DMAC) CLKOUT A25 to A0 D31 to D0 DACKn (Active-low) Figure 14.5 Example of DMA Transfer Timing in Dual Address Mode (Source: SRAM, Destination: DDR-SDRAM) Rev.1.00 Jan. 10, 2008 Page 712 of 1658 REJ09B0261-0100 Transfer Transfer source address destination address...
Page 743 Bus Modes Bus modes include cycle steal mode and burst mode. The modes are chosen by the TB and LCKN bits in CHCR. Cycle Steal Mode • Normal mode 1 (CHCR.LCKN = 0, CHCR.TB = 0) In cycle steal normal mode 1, the DMAC gives the SuperHyway bus mastership to another bus master after a one-transfer unit (byte, word, longword, 16-byte, or 32-byte unit).
Page 744 14. Direct Memory Access Controller (DMAC) • Intermittent mode 16 (DMAOR. CMS = 10, CHCR.LCKN = 0 or 1, CHCR.TB = 0) • Intermittent mode 64 (DMAOR. CMS = 11, CHCR.LCKN = 0 or 1, CHCR.TB = 0) In intermittent mode of cycle steal, the DMAC gives the SuperHyway bus mastership to other bus master whenever a one-transfer unit (byte, word, longword, or 16-byte or 32-byte unit) is completed.
Page 745 14. Direct Memory Access Controller (DMAC) DREQ SuperHyway DMAC DMAC DMAC DMAC DMAC DMAC bus cycle Read Write Read Write Read Write Figure 14.9 DMA Transfer Timing Example in Burst Mode (DREQ Low Level Detection) Bus Mode and Channel Priority Figure 14.10 shows the bus modes and channel priority in priority fixed mode.
Page 746 14. Direct Memory Access Controller (DMAC) (a) CH0: Cycle steal mode CH1: Cycle steal mode Priority: CH0 > CH1 (b) CH0: Cycle steal mode CH1: Cycle steal mode Priority: CH0 > CH1 (c) CH0: Cycle steal mode CH1: Burst mode Priority: CH0 >...
Page 747: Dma Transfer Flow
14.4.4 DMA Transfer Flow After intended transfer conditions are set to SAR, DAR, TCR, CHCR, DMAOR, and DMARS, the DMAC transfers data according to the following procedure. 1. Checks if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2.
Page 748 14. Direct Memory Access Controller (DMAC) Start Initial settings SAR, DAR, TCR, CHCR, DMAOR SARB, DARB, TCRB, DMARS DE, DME = 1 and TE, AE, NMIF = 0? Transfer request occurs? Transfer (1 transfer unit); TCR – 1 → TCR, SAR, and DAR updated Reload mode: TCRBL –...
Page 749: Repeat Mode Transfer
14.4.5 Repeat Mode Transfer A repeat mode transfer of the DMAC enables a DMA transfer to repeat without specifying the transfer settings before a transfer. Using a repeat mode transfer with the half end function can execute a double buffer transfer virtually.
Page 750: Reload Mode Transfer
14. Direct Memory Access Controller (DMAC) This function enables sequential voice compression by switching a storing buffer for data received consequentially and a data buffer for processing signals alternately. 14.4.6 Reload Mode Transfer In a reload mode transfer, according to the settings of bits RPT in CHCR, the value set in SARB/DARB is reloaded to SAR/DAR at each transfer set in bits 23 to 16 and bits 7 to 0 in TCRB, and the transfer is repeated until TCR is 0 without specifying the transfer again.
Page 751: Dreq Pin Sampling Timing
14.4.7 DREQ Pin Sampling Timing Figures 14.13 to 14.22 show the timing that the DREQ input is sampled in each bus mode. Figures 14.13, 14.16, and 14.20 show the timing that the DREQ input is sampled when byte transfer is performed in 8-, 16-, 32-, or 64-bit bus width, word transfer is performed in 16-, 32-, or 64-bit bus width, or longword transfer is performed in 32- or 64-bit bus width.
Page 752 14. Direct Memory Access Controller (DMAC) CLKOUT Bus cycle DREQ (Rising edge) DRAK (High-active) DACK (High-active) Figure 14.14 Example 2 of DREQ Input Detection in Cycle Steal Mode Edge Detection (Word Transfer in 8-Bit Bus Width, Longword Transfer in 8/16-Bit Bus Width, 16/32-Byte Transfer in 8/16/32/64-Bit Bus Width: DACK of DMA1 Transfer Divided) CLKOUT Bus cycle...
Page 753 CLKOUT Bus cycle DREQ (Overrun 0, High level) DRAK (High-active) DACK (High-active) CLKOUT Bus cycle DREQ (Overrun 1, High level) DRAK (High-active) DACK (High-active) Figure 14.16 Example 1 of DREQ Input Detection in Cycle Steal Mode Level Detection (Byte Transfer in 8/16/32/64-Bit Bus Width, Word Transfer in 16/32/64-Bit Bus Width, or Longword Transfer in 32/64-Bit Bus Width) 14.
Page 754 14. Direct Memory Access Controller (DMAC) CLKOUT Bus cycle DREQ (Overrun 0, High level) DRAK (High-active) DACK (High-active) CLKOUT Bus cycle DREQ (Overrun 1, High level) DRAK (High-active) DACK (High-active) Figure 14.17 Example 2 of DREQ Input Detection in Cycle Steal Mode Level Detection (Word Transfer in 8-Bit Bus Width, Longword Transfer in 8/16-Bit Bus Width, 16/32-Byte Transfer in 8/16/32/64-Bit Bus Width: DACK of DMA1 Transfer Divided) Rev.1.00 Jan.
Page 755 CLKOUT Bus cycle Address DREQ (Overrun 0, High level) DRAK (High-active) DACK (High-active) CLKOUT Bus cycle Address DREQ (Overrun 1, High level) DRAK (High-active) DACK (High-active) Figure 14.18 Example 3 of DREQ Input Detection in Cycle Steal Mode Level Detection (Word Transfer in 8-Bit Bus Width, Longword Transfer in 8/16-Bit Bus Width, or 16/32- Byte Transfer in 8/16/32/64-Bit Bus Width: DACK of DMA1 Transfer Is Connected) CLKOUT...
Page 756 14. Direct Memory Access Controller (DMAC) CLKOUT Bus cycle DREQ (Overrun 0, High level) DRAK (High-active) DACK (High-active) CLKOUT Bus cycle DREQ (Overrun 1, High level) DRAK (High-active) DACK (High-active) Figure 14.20 Example 1 of DREQ Input Detection in Burst Mode Level Detection (Byte Transfer in 8/16/32/64-Bit Bus Width, Word Transfer in 16/32/64-Bit Bus Width, or Longword Transfer in 32/64-Bit Bus Width) Rev.1.00 Jan.
Page 757 CLKOUT Bus cycle DREQ (Overrun 0, High level) DRAK (High-active) DACK (High-active) CLKOUT Bus cycle DREQ (Overrun 1, High level) DRAK (High-active) DACK (High-active) Figure 14.21 Example 2 of DREQ Input Detection in Burst Mode Level Detection (Word Transfer in 8-Bit Bus Width, Longword Transfer in 8/16-Bit Bus Width, 16/32-Byte Transfer in 8/16/32/64-Bit Bus Width: DACK of DMA1 Transfer Divided) 14.
Page 758 14. Direct Memory Access Controller (DMAC) CLKOUT Bus cycle Address DREQ (Overrun 0, High level) DRAK (High-active) DACK (High-active) CLKOUT Bus cycle Address DREQ (Overrun 1, High level) DRAK (High-active) DACK (High-active) Figure 14.22 Example 3 of DREQ Input Detection in Burst Mode Level Detection (Word Transfer in 8-Bit Bus Width, Longword Transfer in 8/16-Bit Bus Width, or 16/32-Byte Transfer in 8/16/32/64-Bit Bus Width: DACK of DMA1 Transfer Is Connected) Rev.1.00 Jan.
Page 759: Dmac Interrupt Sources
14.5 DMAC Interrupt Sources In the DMAC, each channel has 14 interrupt sources: a DMA transfer end/half-end interrupts request (DMINT0 to DMINT11), a DMA address error interrupt request (DMAE0) common to channels 0 to 5, and a DMA address error interrupt request (DMAE1) common to channels 6 to Table 14.11 shows each interrupt source.
Page 760: Stopping Modules And Changing Frequency
14. Direct Memory Access Controller (DMAC) 14.6 Usage Notes Note the following things in using this DMAC. 14.6.1 Stopping Modules and Changing Frequency When the DMAC is operating, it is prohibited to set or clear the corresponding bit of MSTPCR1 that controls H-UDI, UBC, DMAC and GDTA modules operation, and also prohibited to change any frequencies regarding the operation of this LSI.
Page 761: Dack/Dreq Setting
14.6.6 DACK/DREQ Setting If the IWRRD, IWRRS, and IWW bits in CSnBCR are set to B'000 (no idle cycles), DACK of two or more DMA transfers may be connected. If DACK of two or more DMA transfers is connected, operation is not guaranteed under the following conditions. In these cases, set the IWRRD, IWRRS, and IWW bits to B'001 to B'111 to insert a minimum of one idle cycle between DMA transfers.
Page 762 14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 732 of 1658 REJ09B0261-0100...
Page 763: Section 15 Clock Pulse Generator (Cpg)
Section 15 Clock Pulse Generator (CPG) The CPG generates clocks provided to the internal and external bus interfaces of the SH7785, and controls power-down mode. The CPG consists of a crystal oscillator circuit, PLLs, dividers, and the control unit. 15.1 Features The CPG has the following features.
Page 764 15. Clock Pulse Generator (CPG) Oscillator circuit Crystal oscillator circuit XTAL EXTAL MODE 10 Control section MODE 4 Clock frequency MODE 3 control circuit MODE 2 MODE 1 FRQCR0 MODE 0 Legend: FRQCR0: Frequency control register 0 FRQCR1: Frequency control register 1 MSTPCR1: Module standby control register 1* Note: * For details about MSTPCR1, see section 17, Power-Down Mode.
Page 765 The function of each block in the CPG is as follows. • PLL circuit 1 PLL circuit 1 multiplies the input clock frequency on the PLL circuit by 36 or 72. • PLL circuit 2 PLL circuit 2 matches the phases of the bus clock (Bck) and the clock of the CLKOUT pin that is used in the local bus.
Page 766: Input/Output Pins
15. Clock Pulse Generator (CPG) 15.2 Input/Output Pins Table 15.1 shows the CPG pin configuration. Table 15.1 CPG Pin Configuration Pin Name Function MODE0, Mode Pins MODE1, 0,1,2,3,4 MODE2, Clock MODE3, operating and MODE4* mode* MODE10 Mode Pin 10 Clock input mode* XTAL Clock Pins...
Page 767: Clock Operating Modes
15.3 Clock Operating Modes Table 15.2 shows the relationship between setting of the mode pins (MODE0 to MODE4) and the clock operating modes. Table 15.2 Clock Operating Modes and Operations of the Oscillator and PLLs Clock Setting of Mode Control Pins* Operating Mode MODE4...
Page 768 15. Clock Pulse Generator (CPG) Table 15.3 Clock Operating Modes and Frequency Multiplication Ratio for Each Clock (Both MODE12 and MODE11 Are Set to High Level) Clock FRQMR1 Clock Operating Initial Mode Value × 36 H'1225 2448 × 36 H'122B 244B ×...
Page 769: Register Descriptions
15.4 Register Descriptions Table 15.5 lists the registers. Table 15.6 shows the register states in each processing mode. Table 15.5 Register Configuration Register Name Frequency control register 0 Frequency control register 1 Frequency display register 1 Sleep control register PLL control register Standby control register 0* Standby control register 1* Standby display register*...
Page 770 15. Clock Pulse Generator (CPG) Table 15.6 Register State in Each Processing Mode Register Name Frequency control register 0 Frequency control register 1 Frequency display register 1 Sleep control register PLL control register Standby control register 0* Standby control register 1* Standby display register* Notes: 1.
Page 771: Frequency Control Register 0 (Frqcr0)
15.4.1 Frequency Control Register 0 (FRQCR0) FRQCR0 is a 32-bit readable and partially writable register that executes a sequence for changing the frequency of each clock. After the sequence is executed, FRQCR0 is automatically cleared to 0. FRQCR0 can only be accessed in longwords. To write to FRQCR0, set the code value (H'CF) in the upper byte and use the longword.
Page 772: Frequency Control Register 1 (Frqcr1)
15. Clock Pulse Generator (CPG) 15.4.2 Frequency Control Register 1 (FRQCR1) FRQCR1 is a 32-bit readable/writable register that can select the division ratio of divider 2 for the CPU clock (lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock (DDRck), the bus clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM clock (Uck).
Page 773 Initial Bit Name Value IFC3 IFC2 IFC1 IFC0 UFC3 UFC2 UFC1 UFC0 SFC3 SFC2 SFC1 SFC0 BFC3 BFC2 BFC1 BFC0 MFC3 MFC2 MFC1 MFC0 Description Frequency division ratio of the CPU clock (Ick) 0000: No change 0001: × 1/2 0010: × 1/4 0011: ×...
Page 774 15. Clock Pulse Generator (CPG) Initial Bit Name Value S2FC3 S2FC2 S2FC1 S2FC0 S3FC3 S3FC2 S3FC1 S3FC0 PFC3 PFC2 PFC1 PFC0 Rev.1.00 Jan. 10, 2008 Page 744 of 1658 REJ09B0261-0100 Description Frequency division ratio of the GDTA clock (GAck) 0000: No change 0100: ×...
Page 775: Frequency Display Register 1 (Frqmr1)
15.4.3 Frequency Display Register 1 (FRQMR1) FRQMR1 is a 32-bit readable register that reads the division ratio of divider 2 for the CPU clock (lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock (DDRck),the bus clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM clock (Uck). FRQMR1 can only be accessed in longwords.
Page 776 15. Clock Pulse Generator (CPG) Initial Bit Name Value BFST3 BFST2 BFST1 BFST0 MFST3 MFST2 MFST1 MFST0 S2FST3 S2FST2 S2FST1 S2FST0 S3FST3 S3FST3 S3FST3 S3FST3 PFST3 PFST2 PFST1 PFST0 Rev.1.00 Jan. 10, 2008 Page 746 of 1658 REJ09B0261-0100 Description Frequency division ratio of the bus clock (Bck) 0101: ×...
Page 777: Pll Control Register (Pllcr)
15.4.4 PLL Control Register (PLLCR) PLLCR is a 32-bit readable/writable register that controls the clock output on the CLKOUT pin. This register can only be accessed in longwords. BIt: ⎯ ⎯ ⎯ ⎯ Initial value: R/W: BIt: ⎯ ⎯ ⎯ ⎯...
Page 778: Calculating The Frequency
15. Clock Pulse Generator (CPG) 15.5 Calculating the Frequency Table 15.7 shows the relationship between the division ratio of divider 2 described for frequency control register FRQCR1 and frequency display register FRQMR1, and the EXTAL input. Table 15.7 Relationship Between the Division Ratio of Divider 2 and the Frequency Division ratio of divider 2 Clock operating mode 0 to 3...
Page 779: How To Change The Frequency
15.6 How to Change the Frequency To change the frequency of the internal clock and the local bus clock (CLKOUT) with software, set frequency control registers FRQCR0 and FRQCR1 according to the following procedure. Tables 15.8 to 15.11 list the selectable combinations of frequencies. 15.6.1 Changing the Frequency of Clocks Other than the Bus Clock When changing the frequency of a clock except the bus clock, disable counting-up by the WDT.
Page 780 15. Clock Pulse Generator (CPG) 4. Set H'CF000001 in FRQCR0 to enable execution of the sequence that changes the frequency. The sequence that changes the frequency starts. 5. The CLKOUTENB pin output changes to low level. After ten cycles of the peripheral clock (Pck), an unstable clock is output to the CLKOUT pin.
Page 781 Table 15.8 Selectable Combinations of Clock Frequency (CPU Clock: × 1/2, DDR Clock: × 1/4) clock clock FRQMR1 read value × 1/2 × 1/4 H'1225 2448 × 1/2 × 1/4 H'1225 2458 × 1/2 × 1/4 H'1225 2488 × 1/2 ×...
Page 782 15. Clock Pulse Generator (CPG) clock clock FRQMR1 read value × 1/2 × 1/4 H'122B 244B × 1/2 × 1/4 H'122B 245B × 1/2 × 1/4 H'122B 246B × 1/2 × 1/4 H'122B 248B × 1/2 × 1/4 H'122B 24BB Table 15.9 Selectable Combinations of Clock Frequency (CPU Clock: ×...
Page 783 clock clock FRQMR1 read value × 1/4 × 1/4 H'2228 2458 × 1/4 × 1/4 H'2228 2488 × 1/4 × 1/4 H'2228 244B × 1/4 × 1/4 H'2228 245B × 1/4 × 1/4 H'2228 246B × 1/4 × 1/4 H'2228 248B ×...
Page 784 15. Clock Pulse Generator (CPG) Table 15.10 Selectable Combinations of Clock Frequency (CPU Clock: × 1/2, DDR Clock: × 1/6) clock clock FRQMR1 read value × 1/2 × 1/6 H'1335 3558 × 1/2 × 1/6 H'1335 3588 × 1/2 × 1/6 H'1335 355A ×...
Page 785 Table 15.11 Selectable Combinations of Clock Frequency (CPU Clock: × 1/6, DDR Clock: × 1/6) clock clock FRQMR1 read value × 1/6 × 1/6 H'3335 3558 × 1/6 × 1/6 H'3335 3588 × 1/6 × 1/6 H'3335 355A × 1/6 ×...
Page 786: Notes On Designing Board
15. Clock Pulse Generator (CPG) 15.7 Notes on Designing Board 1. Note on Using a Crystal Resonator Place the crystal resonator and capacitors close to the EXTAL and XTAL pins as much as possible. No other signal lines should cross the signal line of these pins. Induction may prevent correct oscillation.
Page 787 SH7785 VDD-PLL1 VSS-PLL1 VDDA-PLL1 VSSA-PLL1 VDDQ-PLL1 VSSQ-PLL1 VDD-PLL2 VSS-PLL2 VDDQ-PLL2 VSSQ-PLL2 Recommended values: RCB1 = RCB2 = RCB3 = RCB4 = RCB5 = 10 Ω CPB1 = CPB2 = CPB3 = CPB4 = CPB5 = 10 μF (Tantalum capacitor) CB1 = CB2 = CB3 = CB4 = CB5 = 0.1 μF Figure 15.5 Note on Using a PLL Oscillator Circuit 15.
Page 788 15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 758 of 1658 REJ09B0261-0100...
Page 789: Section 16 Watchdog Timer And Reset (Wdt)
Section 16 Watchdog Timer and Reset (WDT) The watchdog timer and reset module (WDT) comprises a reset control unit and a watchdog timer control unit, and controls the power-on reset sequence and internal reset of the LSI. The WDT is a single-channel timer that can be used either as a watchdog timer or interval timer. 16.1 Features •...
Page 790 16. Watchdog Timer and Reset (WDT) Figure 16.1 is a block diagram of the WDT. Watchdog Timer and Reset module (WDT) PRESET WDTCSR WDTCNT Comparator WDTST Legend: WDTCNT: Watchdog timer counter WDTST: Watchdog timer stop time register WDTBCNT: Watchdog timer base counter WDTBST: Watchdog timer base stop time register WDTCSR: Watchdog timer control/status register...
Page 791: Input/Output Pins
16.2 Input/Output Pins Table 16.1 shows the pin configuration of the WDT module. Table 16.1 Pin Configuration Pin name Function PRESET Power-on reset input MRESETOUT Manual reset output STATUS[1:0] Status output 16. Watchdog Timer and Reset (WDT) Description Input A low level input to this pin places the LSI in the power-on reset state.
Page 792: Register Descriptions
16. Watchdog Timer and Reset (WDT) 16.3 Register Descriptions Table 16.2 shows the registers of the WDT module. Table 16.3 shows the register states in each operating mode. Table 16.2 Register Configuration Register Name Watchdog timer stop time register WDTST Watchdog timer control/status register Watchdog timer base stop time...
Page 793: Watchdog Timer Stop Time Register (Wdtst)
16.3.1 Watchdog Timer Stop Time Register (WDTST) WDTST is a 32-bit readable/writable register that specifies the time until watchdog timer counter WDTCNT overflows. The time until WDTCNT overflows becomes minimum when H'5A00 0001 is set, and maximum when H'5A00 0000 is set. WDTST should be written as a longword unit, with H'5A in the most significant byte.
Page 794: Watchdog Timer Control/Status Register (Wdtcsr)
16. Watchdog Timer and Reset (WDT) 16.3.2 Watchdog Timer Control/Status Register (WDTCSR) WDTCSR is a 32-bit readable/writable register comprising timer mode-selecting bits and overflow flags. WDTCSR should be written to as a longword unit, with H'A5 in the most significant byte. The value read from this byte is always H'00.
Page 795 Initial Bit Name Value RSTS WOVF IOVF ⎯ 2 to 0 All 0 Description Reset Select Specifies the type of reset on WDTCNT overflow in watchdog timer mode. This setting is ignored in interval timer mode. 0: Power-on reset 1: Manual reset Watchdog Timer Overflow Flag Indicates that WDTCNT has overflowed in watchdog timer mode.
Page 796: Watchdog Timer Base Stop Time Register (Wdtbst)
16. Watchdog Timer and Reset (WDT) 16.3.3 Watchdog Timer Base Stop Time Register (WDTBST) WDTBST is a 32-bit readable/writable register that specifies the time until counter WDTBCNT overflows when the bus clock frequency has been changed. The time until WDTBCNT overflows becomes minimum when H'5500 0001 is set, and maximum when H'5500 0000 is set.
Page 797: Watchdog Timer Counter (Wdtcnt)
16.3.4 Watchdog Timer Counter (WDTCNT) WDTCNT is a 32-bit read-only register comprising a 12-bit counter that is incremented by the WDTBCNT overflow signal. When WDTCNT overflows, a reset of the selected type is initiated in watchdog timer mode, or an interrupt is generated in interval timer mode. WDTCNT is only reset by a power-on reset.
Page 798: Watchdog Timer Base Counter (Wdtbcnt)
16. Watchdog Timer and Reset (WDT) 16.3.5 Watchdog Timer Base Counter (WDTBCNT) WDTBCNT is a 32-bit read-only register comprising an 18-bit counter that is incremented by the peripheral clock (Pck). When WDTBCNT overflows, WDTCNT is incremented and WDTBCNT is cleared to H'0000 0000. WDTBCNT is only reset by a power-on reset.
Page 799: Reset Request
16.4 Operation 16.4.1 Reset Request Power-on reset and manual reset are available. Their requesting sources are described below. Power-On Reset • Requesting sources ⎯ A low level input on the PRESET pin ⎯ WDTCNT overflow when the WT/IT bit is 1 and the RSTS bit is 0 in WDTCSR ⎯...
Page 800 16. Watchdog Timer and Reset (WDT) Manual Reset • Requesting sources ⎯ A general exception other than a user break while the BL bit in SR is set to 1. ⎯ WDTCNT overflow when both the WT/IT and RSTS bits in WDTCSR are set to 1 •...
Page 801: Using Watchdog Timer Mode
16.4.2 Using Watchdog Timer Mode 1. Set the WDTCNT overflow time in WDTST. 2. Set the WT/IT bit in WDTCSR to 1, and select the type of reset with the RSTS bit. 3. When the TME bit in WDTCSR is set to 1, the WDT counter starts. 4.
Page 802: Time Until Wdt Counters Overflow
16. Watchdog Timer and Reset (WDT) 16.4.4 Time until WDT Counters Overflow The relationship between WDTCNT and WDTBCNT is shown in figure 16.2. The example shown in the figure is the operation in interval timer mode, where WDTCNT restarts counting after it has overflowed.
Page 803: Clearing Wdt Counters
WDTBCNT is an 18-bit counter that is incremented by the peripheral clock. If the period of peripheral clock Pck is represented as tPck (ns), the overflow time of WDTBCNT is expressed as follows. × [bit] tPck [ns] = 0.262 WDTCNT is a 12-bit counter that is incremented each time WDTBCNT overflows. The time until WDTCNT overflows becomes maximum when 0 is written to all the bits in WDTST.
Page 804: Status Pin Change Timing During Reset
16. Watchdog Timer and Reset (WDT) 16.5 Status Pin Change Timing during Reset Power-On Reset by PRESET Pin 16.5.1 Since the PLL circuit is initialized when the LSI enters the power-on reset state, the PLL oscillation settling time needs to be ensured. This means that a high level must not be input to the PRESET pin during the PLL oscillation settling time.
Page 805 Power-On Reset Caused by PRESET Input during Normal Operation It is necessary to ensure the PLL oscillation settling time when a power-on reset is initiated by low level input on the PRESET pin during normal operation. The timing of reset state indication on the STATUS[1:0] pins is asynchronous. The timing of indicating normal operation is synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin.
Page 806 16. Watchdog Timer and Reset (WDT) Power-On Reset Caused by PRESET Input in Sleep Mode It is necessary to ensure the PLL oscillation settling time when a power-on reset is initiated by a low level input on the PRESET pin during sleep mode. The timing of reset state indication on the STATUS[1:0] pins is asynchronous.
Page 807: Power-On Reset By Watchdog Timer Overflow
16.5.2 Power-On Reset by Watchdog Timer Overflow The time period taken by power-on reset on watchdog timer overflow (WDT reset holding time) is equal to or more than 40 cycles of the peripheral clock (Pck). The transition time from watchdog timer overflow to the power-on reset state (WDT reset setup time) is equal to or more than 40 cycles of the peripheral clock (Pck).
Page 808 16. Watchdog Timer and Reset (WDT) Power-On Reset Caused by Watchdog Timer Overflow in Sleep Mode The timing of indicating the reset state or normal operation on the STATUS[1:0] pins is synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin.
Page 809: Manual Reset By Watchdog Timer Overflow
16.5.3 Manual Reset by Watchdog Timer Overflow The time period taken by manual reset on watchdog timer overflow (WDT manual reset holding time) is equal to or more than 30 cycles of the peripheral clock (Pck). The transition time from watchdog timer overflow to the manual reset state (WDT reset setup time) is equal to or more than eight cycles of the peripheral clock (Pck).
Page 810 16. Watchdog Timer and Reset (WDT) Manual Reset Caused by Watchdog Timer Overflow in Sleep Mode The timing of indicating the reset state or normal operation on the STATUS[1:0] pins is synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin.
Page 811: Section 17 Power-Down Mode
Section 17 Power-Down Mode In power-down mode, some of the on-chip modules and the CPU are stopped. This enables to reduce power consumption. 17.1 Features • Supports sleep mode, deep sleep mode, and module standby mode • Supports DDR2-SDRAM power supply backup mode that turns off the power supplies the 1.8- V power supply 17.1.1 Types of Power-Down Modes...
Page 812 17. Power-Down Mode Table 17.1 States of Power-Down Modes Power- Down Conditions of Mode Transition Sleep SLEEP Operate Stopped mode instruction (contents executed (see of registers section 17.4) retained) Deep Corresponding Operate Stopped sleep bit in MSTPCR (contents mode set to 1 (see of registers section 17.3.2) retained)
Page 813: Input/Output Pins
17.2 Input/Output Pins Table 17.2 shows the pins related to power-down mode. Table 17.2 Pin Configuration Pin name Function STATUS1 Processing state 1 STATUS0 Processing state 2 Note: L means low level, and H means high level. 17.3 Register Descriptions Table 17.3 shows the list of registers.
Page 814 17. Power-Down Mode Table 17.4 Register States of CPG in Each Processing Mode Register Name Standby control register 0* Standby control register 1* Standby display register Notes: 1. For details of MSTPCR0 and MSTPCR1, see figure 15.1. 2. The initial value after a power-on reset depends on the combination of mode pin states (MODE11 and MODE12).
Page 815: Sleep Control Register (Slpcr)
17.3.1 Sleep Control Register (SLPCR) SLPCR is a 32-bit readable/writable register that can specify transition to deep sleep mode. SLPCR can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin or power-on reset by WDT overflow, or H-UDI reset.
Page 816: Standby Control Register 0 (Mstpcr0)
17. Power-Down Mode 17.3.2 Standby Control Register 0 (MSTPCR0) MSTPCR0 is a 32-bit readable/writable register that can specify whether each peripheral module operates or is stopped. MSTPCR can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin or power-on reset by WDT overflow, or H-UDI reset.
Page 817 Initial Bit Name Value 21, 20 MSTP[21:20] All 0 ⎯ 19, 18 All 0 17, 16 MSTP[17:16] All 0 ⎯ 15, 14 All 0 13, 12 MSTP[13:12] All 0 ⎯ 11, 10 All 0 Description Module Stop Bit [21:20] Specify that the clock supply to the module of the corresponding bit is stopped [21]: SSI channel 1, [20]: SSI channel 0 0: The corresponding module operates...
Page 818 17. Power-Down Mode Initial Bit Name Value 9, 8 MSTP[9:8] All 0 ⎯ 7 to 4 All 0 3, 2 MSTP[3:2] All 0 ⎯ 1, 0 All 0 Rev.1.00 Jan. 10, 2008 Page 788 of 1658 REJ09B0261-0100 Description Module Stop Bit [9:8] Specify that the clock supply to the module of the corresponding bit is stopped [9]: TMU channels 3 to 5...
Page 819: Standby Control Register 1 (Mstpcr1)
17.3.3 Standby Control Register 1 (MSTPCR1) MSTPCR1 is a 32-bit readable/writable register that each module of H-UDI, UBC, DMAC, and GDTA operates or is stopped. MSTPCR1 can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin or power-on reset by WDT overflow, or H-UDI reset.
Page 820 17. Power-Down Mode Initial Bit Name Value ⎯ 16 to 6 All 0 5, 4 MSTP All 0 [105:104] ⎯ 3 to 1 All 0 MSTP100 Note: The GDTA should be placed in module standby state after confirming that the operation of the GDTA is completed.
Page 821: Standby Display Register (Mstpmr)
17.3.4 Standby Display Register (MSTPMR) MSTPMR is a 32-bit readable register that indicates whether the PCIC/display unit (DU)/DMAC/GDTA modules are in the module standby state. MSTPMR can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin, power-on reset by WDT overflow, or H-UDI reset.
Page 822 17. Power-Down Mode Initial Bit Name Value 5, 4 MSTPS105 All 0 MSTPS104 ⎯ 3 to 1 All 0 MSTP100 Rev.1.00 Jan. 10, 2008 Page 792 of 1658 REJ09B0261-0100 Description Module Stop Display Bit 105, 104 Indicates the state of clock supply to the DMAC channels of the corresponding bit MSTPS105: DMAC channels 11 to 6 MSTPS104: DMAC channels 5 to 0...
Page 823: Transition To Sleep Mode
17.4 Sleep Mode 17.4.1 Transition to Sleep Mode When the SLEEP instruction is executed, the state is changed from the program execution state to sleep mode. Although the CPU is stopped after the instruction is executed, the contents of the CPU register are retained.
Page 824: Deep Sleep Mode
17. Power-Down Mode 17.5 Deep Sleep Mode 17.5.1 Transition to Deep Sleep Mode If a SLEEP instruction is executed when the DSLP bit in SLPCR is set to 1, the chip switches from the program execution state to deep sleep mode. The procedure for a transition to deep sleep mode is as follows: 1.
Page 825: Releasing Deep Sleep Mode
17.5.2 Releasing Deep Sleep Mode Deep sleep mode is released by means of an interrupt (NMI, IRL, IRQ, GPIO, WDT interval timer, or H-UDI) or a reset. In deep sleep mode, an interrupt request is accepted even if the BL bit in SR is set to 1. The SPC, SSR and other related contents should be saved before execute a SLEEP instruction if necessary.
Page 826: Module Standby Functions
17. Power-Down Mode 17.6 Module Standby Functions This LSI supports the module standby state, where the clock supplied to on-chip modules is stopped. 17.6.1 Transition to Module Standby Mode By setting the MSTP bits in MSPTCR, the clock supply can be stopped to the corresponding module*.
Page 827: Timing Of The Changes On The Status Pins
17.7 Timing of the Changes on the STATUS Pins 17.7.1 Reset For details, see section 16.5, Status Pin Change Timing during Reset. 17.7.2 Releasing Sleep Mode When Sleep Mode Is Released by an Interrupt Figure 17.1 shows the timing of the changes in the STATUS pin. CLKOUT IRQOUT output...
Page 828 17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 798 of 1658 REJ09B0261-0100...
Page 829: Section 18 Timer Unit (Tmu)
Section 18 Timer Unit (TMU) This LSI includes an on-chip 32-bit timer unit (TMU), which has six channels (channels 0 to 5). 18.1 Features The TMU has the following features. • Auto-reload type 32-bit down-counter provided for each channel • Input capture function provided only for channel 2 •...
Page 830 18. Timer Unit (TMU) Figure 18.1 shows a block diagram of the TMU. TCOR TCNT TCOR TCNT TCPR2 TCOR Peripheral TCNT Legend: TCNT: Timer counter TCOR: Timer constant register TCPR2: Input capture register 2 (channel 2 only) TCR: Timer control register TSTR0, TSTR1: Timer start register Rev.1.00 Jan.
Page 831: Input/Output Pins
18.2 Input/Output Pins Table 18.1 shows the TMU pin configuration. Table 18.1 Pin Configuration Pin Name Abbrev. Clock input TCLK Description Input External clock input pin for channels 0, 1 and 2 /input capture control input pin for channel 2 Rev.1.00 Jan.
Page 832: Register Descriptions
18. Timer Unit (TMU) 18.3 Register Descriptions Tables 18.2 and 18.3 show the TMU register configuration. Table 18.2 Register Configuration (1) Channel Register Name Common Timer start register 0 to 0, 1, 2 Timer constant register 0 Timer counter 0 Timer control register 0 Timer constant register 1 Timer counter 1...
Page 833 Table 18.3 Register Configuration (2) Channel Register Name Common Timer start register 0 to 0, 1, 2 Timer constant register 0 Timer counter 0 Timer control register 0 Timer constant register 1 Timer counter 1 Timer control register 1 Timer constant register 2 Timer counter 2 Timer control register 2 Input capture register 2...
Page 834: Timer Start Registers (Tstrn) (N = 0, 1)
18. Timer Unit (TMU) 18.3.1 Timer Start Registers (TSTRn) (n = 0, 1) The TSTR registers are 8-bit readable/writable registers that specifies whether TCNT of the corresponding channel is operated or stopped. • TSTR0 BIt: Initial value: R/W: Initial Bit Name Value 7 to 3 —...
Page 835 • TSTR1 BIt: Initial value: R/W: Initial Bit Name Value 7 to 3 — All 0 STR5 STR4 STR3 — — — — — STR5 Description Reserved These bits are always read as 0. The write value should always be 0. Counter Start 5 Specifies whether TCNT5 is operated or stopped.
Page 836: Timer Constant Registers (Tcorn) (N = 0 To 5)
18. Timer Unit (TMU) 18.3.2 Timer Constant Registers (TCORn) (n = 0 to 5) The TCOR registers are 32-bit readable/writable registers. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value.
Page 837: Timer Control Registers (Tcrn) (N = 0 To 5)
18.3.4 Timer Control Registers (TCRn) (n = 0 to 5) The TCR registers are 16-bit readable/writable registers. Each TCR selects the count clock, specifies the edge when an external clock is selected, and controls interrupt generation when the flag indicating TCNT underflow is set to 1. TCR2 is also used for input capture control and control of interrupt generation in the event of input capture.
Page 838 18. Timer Unit (TMU) Initial Bit Name Value ICPE1* ICPE0* UNIE CKEG1 CKEG0 Rev.1.00 Jan. 10, 2008 Page 808 of 1658 REJ09B0261-0100 Description Input Capture Control These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used.
Page 839: Input Capture Register 2 (Tcpr2)
Initial Bit Name Value TPSC2 TPSC1 TPSC0 Legend: X: Don't care Notes: 1. Reserved bit in channels 0 to 5 (initial value is 0, and can only be read). 2. Writing 1 does not change the value; the previous value is retained. 3.
Page 840: Counter Operation
18. Timer Unit (TMU) 18.4 Operation Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). Each TCNT performs count-down operation. The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function.
Page 841 Auto-Reload Count Operation Figure 18.3 shows the TCNT auto-reload operation. TCNT value TCOR H'0000 0000 STR0 to STR5 Figure 18.3 TCNT Auto-Reload Operation 18. Timer Unit (TMU) TCOR value is set in TCNT on underflow Rev.1.00 Jan. 10, 2008 Page 811 of 1658 REJ09B0261-0100 Time...
Page 842 18. Timer Unit (TMU) TCNT Count Timing • Operating on internal clock Any of five internal count clocks (Pck/4, Pck/16, Pck/64, Pck/256, or Pck/1024) scaled from the peripheral clock can be selected as the count clock by means of the TPSC2 to TPSC0 bits in TCR.
Page 843: Input Capture Function
18.4.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1. Use bits TPSC2 to TPSC0 in TCR2 to set an internal clock as the timer operating clock. 2.
Page 844: Interrupts
18. Timer Unit (TMU) 18.5 Interrupts There are seven TMU interrupt sources: underflow interrupts and the input capture interrupt when the input capture function is used. Underflow interrupts are generated on each of the channels, and input capture interrupts on channel 2 only. An underflow interrupt request is generated (for each channel) when both the UNF bit and the interrupt enable bit (UNIE) for that channel are set to 1.
Page 845: Register Writes
18.6 Usage Notes 18.6.1 Register Writes When writing to a TMU register, timer count operation must be stopped by clearing the start bit (STR5 to STR0) for the relevant channel in TSTR. Note that TSTR can be written to, and the UNF and ICPF bits in TCR can be cleared while the count is in progress.
Page 846 18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 816 of 1658 REJ09B0261-0100...
Page 847: Section 19 Display Unit (Du)
19. Display Unit (DU) Section 19 Display Unit (DU) 19.1 Features The display unit (DU) has the following features. Plane: The display surfaces normally called the foreground, background, and cursor, are called planes in this section. Parameters for each plane can be set independently through the settings of an internal register.
Page 848 19. Display Unit (DU) CRT Scan Mode (CRT Scan Method): Internal register settings can be used to select from among three scan modes. • Non-interlaced mode • Interlaced sync mode • Interlaced sync & video mode YC→RGB Colorspace Conversion Functions: Image data stored in YC format can be converted into the RGB colorspace and displayed in a window.
Page 849 Figure 19.1 shows a block diagram of the display unit (DU). DCLKIN DCLKOUT DUck SHck Legend: byte word Figure 19.1 Block Diagram of the Display Unit (DU) DR5 to DR0 DG5 to DG0 DB5 to DB0 Pin control (output timing adjustment) Superposition (α...
Page 850: Input/Output Pins
19. Display Unit (DU) 19.2 Input/Output Pins Table 19.1 shows the pin configuration of the display unit (DU). Table 19.1 Pin Configuration of the Display Unit (DU) Pin Name Number I/O DCLKIN DCLKOUT Output Output dot clock HSYNC VSYNC ODDF DISP Output Display interval Output Color detection...
Page 851: Register Descriptions
Pin Name Number I/O Output Digital green 5 Output Digital blue 0 Output Digital blue 1 Output Digital blue 2 Output Digital blue 3 Output Digital blue 4 Output Digital blue 5 Note: In this section, unless otherwise noted, "dot clock" refers to the output dot clock. 19.3 Register Descriptions Register update methods include external update and internal update.
Page 852 19. Display Unit (DU) • Display mode register (DSMR) ⎯ VSPM bit (VSYNC pin mode) ⎯ ODPM bit (ODPM pin mode) ⎯ ODDF bit (ODDF pin mode) ⎯ DIPM bit (DISP pin mode) ⎯ CSPM bit (HSYNC pin mode) ⎯ DIL bit (polarity reversal bit of the DISP pin) ⎯...
Page 853 Table 19.2 Register Configuration Register Name Display system control register Display mode register Display status register Display status register clear register Display interrupt enable register Color palette control register Display plane priority order register Display extension function enable register Horizontal display start position register Horizontal display end position register...
Page 854 19. Display Unit (DU) Register Name DE signal start position register DE signal width register Color palette 1 transparent color register Color palette 2 transparent color register Color palette 3 transparent color register Color palette 4 transparent color register Display-off output register Color detection register Base color register Raster interrupt offset register...
Page 855 Register Name Plane 1 wrap-around memory width register Plane 1 blinking period register Plane 1 transparent color 1 register Plane 1 transparent color 2 register Plane 1 memory length register Plane 2 mode register Plane 2 memory width register Plane 2 blend ratio register Plane 2 display size X register Plane 2 display size Y register Plane 2 display position X...
Page 856 19. Display Unit (DU) Register Name Plane 3 memory width register Plane 3 blend ratio register Plane 3 display size X register Plane 3 display size Y register Plane 3 display position X register Plane 3 display position Y register Plane 3 display area start address 0 register Plane 3 display area start...
Page 857 Register Name Plane 4 display area start address 0 register Plane 4 display area start address 1 register Plane 4 start position X register Plane 4 start position Y register Plane 4 wrap-around start position register Plane 4 wrap-around memory width register Plane 4 blinking period register Plane 4 transparent color 1...
Page 858 19. Display Unit (DU) Register Name Plane 5 wrap-around memory width register Plane 5 blinking period register Plane 5 transparent color 1 register Plane 5 transparent color 2 register Plane 5 memory length register Plane 6 mode register Plane 6 memory width register Plane 6 blend ratio register Plane 6 display size X register Plane 6 display size Y register...
Page 859 Register Name Color palette 1 register 000 Color palette 1 register 255 Color palette 2 register 000 Color palette 2 register 255 Color palette 3 register 000 Color palette 3 register 255 Color palette 4 register 000 Color palette 4 register 255 External synchronization control register Output signal timing adjustment...
Page 860 19. Display Unit (DU) Table 19.3 Status of Registers in Each Processing Mode Register Name Abbr. Display system DSYSR control register Display mode DSMR register Display status DSSR register Display status DSRCR register clear register Display interrupt DIER enable register Color palette CPCR control register...
Page 861 Register Name Abbr. Horizontal display HDSR start position register Horizontal display HDER end position register Vertical display VDSR start position register Vertical display VDER end position register Horizontal scan period register Horizontal HSWR synchronous pulse width register Vertical scan period register Vertical VSPR synchronous...
Page 862 19. Display Unit (DU) Register Name Abbr. Color palette 1 CP1TR transparent color register Color palette 2 CP2TR transparent color register Color palette 3 CP3TR transparent color register Color palette 4 CP4TR transparent color register Display-off output DOOR register Color detection CDER register Base color register BPOR...
Page 863 Register Name Abbr. Plane 1 display P1DPYR position Y register Plane 1 display P1DSA0R area start address 0 register Plane 1 display P1DSA1R area start address 1 register Plane 1 start P1SPXR position X register Plane 1 start P1SPYR position Y register Plane 1 wrap- P1WASPR Undefined around start...
Page 864 19. Display Unit (DU) Register Name Abbr. Plane 2 display P2DSXR size X register Plane 2 display P2DSYR size Y register Plane 2 display P2DPXR position X register Plane 2 display P2DPYR position Y register Plane 2 display P2DSA0R area start address 0 register Plane 2 display P2DSA1R...
Page 865 Register Name Abbr. Plane 3 mode P3MR register Plane 3 memory P3MWR width register Plane 3 blend ratio P3ALPHAR Undefined register Plane 3 display P3DSXR size X register Plane 3 display P3DSYR size Y register Plane 3 display P3DPXR position X register Plane 3 display P3DPYR position Y register...
Page 866 19. Display Unit (DU) Register Name Abbr. Plane 3 P3TC2R transparent color 2 register Plane 3 memory P3MLR length register Plane 4 mode P4MR register Plane 4 memory P4MWR width register Plane 4 blend ratio P4ALPHAR Undefined register Plane 4 display P4DSXR size X register Plane 4 display...
Page 867 Register Name Abbr. Plane 4 blinking P4BTR period register Plane 4 P4TC1R transparent color 1 register Plane 4 P4TC2R transparent color 2 register Plane 4 memory P4MLR length register Plane 5 mode P5MR register Plane 5 memory P5MWR width register Plane 5 blend ratio P5ALPHAR Undefined register...
Page 868 19. Display Unit (DU) Register Name Abbr. Plane 5 wrap- P5WASPR Undefined around start position register Plane 5 wrap- P5WAMWR Undefined around memory width register Plane 5 blinking P5BTR period register Plane 5 P5TC1R transparent color 1 register Plane 5 P5TC2R transparent color 2 register...
Page 869 Register Name Abbr. Plane 6 display P6DSA1R area start address 1 register Plane 6 start P6SPXR position X register Plane 6 start P6SPYR position Y register Plane 6 wrap- P6WASPR Undefined around start position register Plane 6 wrap- P6WAMWR Undefined around memory width register Plane 6 blinking...
Page 870 19. Display Unit (DU) Register Name Abbr. Color palette 3 CP3_000R Undefined register 000 Color palette 3 CP3_255R Undefined register 255 Color palette 4 CP4_000R Undefined register 000 Color palette 4 CP4_255R Undefined register 255 External ESCR synchronization control register Output signal OTAR timing adjustment...
Page 871: Display Unit System Control Register
19.3.1 Display Unit System Control Register The display unit system control register (DSYSR) sets the system operation for the display unit (DU). Bit: — — — Initial value: R/W: Internal update: Bit: — — — Initial value: R/W: Internal update: Initial Bit Name Value...
Page 872 19. Display Unit (DU) Initial Bit Name Value IUPD 15 to 10 ⎯ All 0 Rev.1.00 Jan. 10, 2008 Page 842 of 1658 REJ09B0261-0100 Internal Update Description Internal Updating Disable When DRES = 1, internal update is performed regardless of this bit. For details of internal update, see (2) Internal Update in section 19.3, Register Descriptions.
Page 873 Initial Bit Name Value DRES Internal Update Description None Display Reset Display Enable 00: Starts display synchronization operation. In the case of a register not yet set, unexpected operation may occur; hence DRES should be set to 0 after setting all the registers in the display unit (DU).
Page 874 19. Display Unit (DU) Initial Bit Name Value 7, 6 5, 4 ⎯ 3 to 0 All 0 Rev.1.00 Jan. 10, 2008 Page 844 of 1658 REJ09B0261-0100 Internal Update Description None TV Synchronization Mode 00: Master mode HSYNC, VSYNC, CSYNC are output 01: Synchronization method switching mode When switching from TV sync mode to master mode, or from master mode to TV...
Page 875: Display Mode Register (Dsmr)
19.3.2 Display Mode Register (DSMR) The display mode register (DSMR) sets the display operation of the display unit. Bit: — — — Initial value: R/W: Internal update: Bit: CDEL CDEM Initial value: R/W: Internal update: Initial Bit Name Value 31 to 29 ⎯ All 0 VSPM ODPM...
Page 876 19. Display Unit (DU) Initial Bit Name Value CSPM 23 to 20 ⎯ All 0 DDIS CDEL Rev.1.00 Jan. 10, 2008 Page 846 of 1658 REJ09B0261-0100 Internal Update Description CSYNC Pin Mode Settings in DSYSR are given priority over settings in this register. 0: CSYNC signal is output to the HSYNC pin 1: HSYNC signal is output to the HSYNC pin ⎯...
Page 877 Initial Bit Name Value 14, 13 CDEM CDED ⎯ 11 to 9 All 0 ODEV Internal Update Description CDE Output Mode 00: CDE signal is output without change 01: CDE signal is output without change 10: Low level output outside of display interval (interval when DISP signal is inactive) 11: High level output outside of display interval (interval when DISP signal is inactive)
Page 878 19. Display Unit (DU) Initial Bit Name Value 7, 6 ⎯ 5 to 0 All 0 Note: The bit is updated by setting the DRES bit in DSYSR to 1. Rev.1.00 Jan. 10, 2008 Page 848 of 1658 REJ09B0261-0100 Internal Update Description None...
Page 879: Display Status Register (Dssr)
19.3.3 Display Status Register (DSSR) The display status register (DSSR) is a register used to read, from outside, the internal state of the display unit (DU). Bit: — — — Initial value: R/W: Internal update: Bit: — Initial value: R/W: Internal update: Initial Bit Name...
Page 880 19. Display Unit (DU) Initial Bit Name Value DFB5 DFB4 DFB3 DFB2 Rev.1.00 Jan. 10, 2008 Page 850 of 1658 REJ09B0261-0100 Internal Update Description None Display Frame Buffer 5 Flag 0: The address indicated by the plane 5 display area start address 0 register (P5DSA0R) in plane 5 is being used as the display area start address 1: The address indicated by the plane 5 display...
Page 881 Initial Bit Name Value DFB1 Internal Update Description None Display Frame Buffer 1 Flag 0: The address indicated by the plane 1 display area start address 0 register (P1DSA0R) in plane 1 is being used as the display area start address 1: The address indicated by the plane 1 display area start address 0 register (P1DSA1R) in...
Page 882 19. Display Unit (DU) Initial Bit Name Value ⎯ 13, 12 All 0 ⎯ RINT ⎯ 7 to 0 All 0 Rev.1.00 Jan. 10, 2008 Page 852 of 1658 REJ09B0261-0100 Internal Update Description ⎯ Reserved These bits are always read as 0. The write value should always be 0.
Page 883: Display Unit Status Register Clear Register (Dsrcr)
19.3.4 Display Unit Status Register Clear Register (DSRCR) The display unit status register clear register (DSRCR) is a register which clears the various flags in DSSR. Bit: — — — Initial value: R/W: Internal update: Bit: — TVCL FRCL Initial value: —...
Page 884: Display Unit Interrupt Enable Register (Dier)
19. Display Unit (DU) Initial Bit Name Value RICL Undefined W HBCL Undefined W ⎯ 7 to 0 All 0 19.3.5 Display Unit Interrupt Enable Register (DIER) The display unit interrupt enable register (DIER) is a register which enables interrupts to the CPU the causes of which are internal states of the display unit (DU) reflected in DSSR.
Page 885 Initial Bit Name Value 31 to 16 ⎯ All 0 ⎯ 13, 12 All 0 ⎯ ⎯ 7 to 0 All 0 Internal Update Description ⎯ Reserved These bits are always read as 0. The write value should always be 0. None TV Synchronous Signal Error Interrupt Enable 0: Disables interrupt by the TVR flag in DSSR...
Page 886 19. Display Unit (DU) The following are conditions, based on DSSR and this register, for issuing an interrupt to the CPU from the display unit (DU). Conditions for issuing an interrupt = a + b + c + d + e •...
Page 887: Color Palette Control Register (Cpcr)
19.3.6 Color Palette Control Register (CPCR) The color palette control register (CPCR) is a register which enables switching of the color palette. For information on color palette switching, refer to section 19.4.8, Color Palettes. Bit: — — — Initial value: R/W: Internal update: Bit:...
Page 888 19. Display Unit (DU) Initial Bit Name Value CP3CE CP2CE CP1CE ⎯ 15 to 0 All 0 Rev.1.00 Jan. 10, 2008 Page 858 of 1658 REJ09B0261-0100 Internal Update Description Color Palette 3 Change Enable 0: Switching of color palette 3 is not performed. 1: Switching of color palette 3 is performed.
Page 889: Display Plane Priority Register (Dppr)
19.3.7 Display Plane Priority Register (DPPR) The display plane priority register (DPPR) sets the priority order for combining planes and turns the display on and off. Bit: — — — Initial value: R/W: Internal update: Bit: DPE4 DPS4 Initial value: R/W: Internal update: Initial...
Page 890 19. Display Unit (DU) Initial Bit Name Value DPE5 18 to 16 DPS5 DPE4 14 to 12 DPS4 Rev.1.00 Jan. 10, 2008 Page 860 of 1658 REJ09B0261-0100 Internal Update Description Display Plane Priority 5 Enable Display Plane Priority 5 Select 1000: Selects and displays plane 1 in priority 5 1001: Selects and displays plane 2 in priority 5 1010: Selects and displays plane 3 in priority 5...
Page 891 Initial Bit Name Value DPE3 10 to 8 DPS3 DPE2 6 to 4 DPS2 DPE1 2 to 0 DPS1 Internal Update Description Display Plane Priority 3 Enable Display Plane Priority 3 Select 1000: Selects and displays plane 1 in priority 3 1001: Selects and displays plane 2 in priority 3 1010: Selects and displays plane 3 in priority 3 1011: Selects and displays plane 4 in priority 3...
Page 892: Display Unit Extensional Function Enable Register (Defr)
19. Display Unit (DU) 19.3.8 Display Unit Extensional Function Enable Register (DEFR) The display unit extensional function enable register (DEFR) enables extension functions. DEFR should be set during display reset (the DRES bit and DEN bit in DSYSR should be set to 1 and to 0 respectively) for external updates.
Page 893 Initial Bit Name Value ABRE ⎯ 3 to 1 All 0 DSAE Internal Update Description None Alpha Blend Ratio Enable 0: The 31 to 24 bits in the color palette registers 1 to 4 and the PnBRSL bits in the plane n blend ratio registers (PnALPHAR) are disabled.
Page 894: Horizontal Display Start Register (Hdsr)
19. Display Unit (DU) 19.3.9 Horizontal Display Start Register (HDSR) The horizontal display start register (HDSR) sets the horizontal display start position. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit: —...
Page 895: Horizontal Display End Register (Hder)
19.3.10 Horizontal Display End Register (HDER) The horizontal display end register (HDER) sets the horizontal display end position. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit: — — —...
Page 896: Vertical Display Start Register (Vdsr)
19. Display Unit (DU) 19.3.11 Vertical Display Start Register (VDSR) The vertical display start register (VDSR) sets the vertical display start position. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit: —...
Page 897: Vertical Display End Register (Vder)
19.3.12 Vertical Display End Register (VDER) The vertical display end register (VDER) sets the vertical display end position. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit: — — —...
Page 898: Horizontal Cycle Register (Hcr)
19. Display Unit (DU) 19.3.13 Horizontal Cycle Register (HCR) The horizontal cycle register (HCR) sets the horizontal scan cycle.(period). The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit: — —...
Page 899: Horizontal Sync Width Register (Hswr)
19.3.14 Horizontal Sync Width Register (HSWR) The horizontal sync width register (HSWR) sets the low-level pulse width of the horizontal sync signal. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit: —...
Page 900: Vertical Cycle Register (Vcr)
19. Display Unit (DU) 19.3.15 Vertical Cycle Register (VCR) The vertical cycle register (VCR) sets the vertical scan interval. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit: — —...
Page 901: Vertical Sync Point Register (Vspr)
19.3.16 Vertical Sync Point Register (VSPR) The vertical sync point register (VSPR) sets the start position of the vertical sync signal in raster line units. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit:...
Page 902: Equal Pulse Width Register (Eqwr)
19. Display Unit (DU) 19.3.17 Equal Pulse Width Register (EQWR) The equal pulse width register (EQWR) sets the low-level pulse width of a pulse equivalent to the CSYNC signal. The value is retained during power-on reset and manual reset. Bit: —...
Page 903: Separation Width Register (Spwr)
19.3.18 Separation Width Register (SPWR) The separation width register (SPWR) sets the low-level pulse width of the separation pulse for the CSYNC signal. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit: —...
Page 904: Clamp Signal Start Register (Clampsr)
19. Display Unit (DU) 19.3.19 CLAMP Signal Start Register (CLAMPSR) The CLAMP signal start register (CLAMPSR) sets the rising edge position of the CLAMP signal. For timing charts for the CLAMP signal and the DE signal, refer to section 19.5.6, CLAMP Signal and DE Signal.
Page 905: Clamp Signal Width Register (Clampwr)
19.3.20 CLAMP Signal Width Register (CLAMPWR) The CLAMP signal width register (CLAMPWR) sets the high-level width of the CLAMP signal. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit: —...
Page 906: De Signal Start Register (Desr)
19. Display Unit (DU) 19.3.21 DE Signal Start Register (DESR) The DE signal start register (DESR) sets the rising edge position of the DE signal. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit:...
Page 907: De Signal Width Register (Dewr)
19.3.22 DE Signal Width Register (DEWR) The DE signal width register (DEWR) sets the high-level width of the DE signal. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit: —...
Page 908: Color Palette 1 Transparent Color Register (Cp1Tr)
19. Display Unit (DU) 19.3.23 Color Palette 1 Transparent Color Register (CP1TR) The color palette 1 transparent color register (CP1TR) specifies the transparent color for color palette 1. Bit: — — — Initial value: R/W: Internal update: Bit: CP1IF CP1IE CP1ID Initial value: R/W:...
Page 909 Initial Bit Name Value CP1IC CP1IB CP1IA CP1I9 CP1I8 CP1I7 CP1I6 Internal Update Description Color Palette 1 Index C 0: The color with index C in color palette 1 is not set to the transparent color. 1: The color with index C in color palette 1 is set to the transparent color.
Page 910 19. Display Unit (DU) Initial Bit Name Value CP1I5 CP1I4 CP1I3 CP1I2 CP1I1 CP1I0 Rev.1.00 Jan. 10, 2008 Page 880 of 1658 REJ09B0261-0100 Internal Update Description Color Palette 1 Index 5 0: The color with index 5 in color palette 1 is not set to the transparent color.
Page 911: Color Palette 2 Transparent Color Register (Cp2Tr)
19.3.24 Color Palette 2 Transparent Color Register (CP2TR) The color palette 2 transparent color register (CP2TR) specifies the transparent color of color palette 2. Bit: — — — Initial value: R/W: Internal update: Bit: CP2IF CP2IE CP2ID Initial value: R/W: Internal update: Initial Bit Name...
Page 912 19. Display Unit (DU) Initial Bit Name Value CP2IC CP2IB CP2IA CP2I9 CP2I8 CP2I7 CP2I6 Rev.1.00 Jan. 10, 2008 Page 882 of 1658 REJ09B0261-0100 Internal Update Description Color Palette 2 Index C 0: The color with index C in color palette 2 is not set to the transparent color.
Page 913 Initial Bit Name Value CP2I5 CP2I4 CP2I3 CP2I2 CP2I1 CP2I0 Internal Update Description Color Palette 2 Index 5 0: The color with index 5 in color palette 2 is not set to the transparent color. 1: The color with index 5 in color palette 2 is set to the transparent color.
Page 914: Color Palette 3 Transparent Color Register (Cp3Tr)
19. Display Unit (DU) 19.3.25 Color Palette 3 Transparent Color Register (CP3TR) The color palette 3 transparent color register (CP3TR) specifies the transparent color of color palette 3. Bit: — — — Initial value: R/W: Internal update: Bit: CP3IF CP3IE CP3ID Initial value: R/W:...
Page 915 Initial Bit Name Value CP3IC CP3IB CP3IA CP3I9 CP3I8 CP3I7 CP3I6 Internal Update Description Color Palette 3 Index C 0: The color with index C in color palette 3 is not set to the transparent color. 1: The color with index C in color palette 3 is set to the transparent color.
Page 916 19. Display Unit (DU) Initial Bit Name Value CP3I5 CP3I4 CP3I3 CP3I2 CP3I1 CP3I0 Rev.1.00 Jan. 10, 2008 Page 886 of 1658 REJ09B0261-0100 Internal Update Description Color Palette 3 Index 5 0: The color with index 5 in color palette 3 is not set to the transparent color.
Page 917: Color Palette 4 Transparent Color Register (Cp4Tr)
19.3.26 Color Palette 4 Transparent Color Register (CP4TR) The color palette 4 transparent color register (CP4TR) specifies the transparent color of color palette 4. Bit: — — — Initial value: R/W: Internal update: Bit: CP4IF CP4IE CP4ID Initial value: R/W: Internal update: Initial Bit Name...
Page 918 19. Display Unit (DU) Initial Bit Name Value CP4IC CP4IB CP4IA CP4I9 CP4I8 CP4I7 CP4I6 Rev.1.00 Jan. 10, 2008 Page 888 of 1658 REJ09B0261-0100 Internal Update Description Color Palette 4 Index C 0: The color with index C in color palette 4 is not set to the transparent color.
Page 919 Initial Bit Name Value CP4I5 CP4I4 CP4I3 CP4I2 CP4I1 CP4I0 Internal Update Description Color Palette 4 Index 5 0: The color with index 5 in color palette 4 is not set to the transparent color. 1: The color with index 5 in color palette 4 is set to the transparent color.
Page 920: Display Off Mode Output Register (Door)
19. Display Unit (DU) 19.3.27 Display Off Mode Output Register (DOOR) The display off mode output register (DOOR) sets the display data output when the display is turned off. The value is retained during power-on reset and manual reset. Bit: —...
Page 921: Color Detection Register (Cder)
19.3.28 Color Detection Register (CDER) The color detection register (CDER) sets the color for color detection. When the display output data match the settings of this register, high level is output from the CDE pin. For information on the output color data format, please refer to section 19.4.6, Output Data Format.
Page 922: Background Plane Output Register (Bpor)
19. Display Unit (DU) Initial Bit Name Value ⎯ 1, 0 All 0 19.3.29 Background Plane Output Register (BPOR) The background plane output register (BPOR) sets the color for display when there is no plane for display, due to the display size or to a transparent color, etc. For detailed conditions, refer to section 19.4.2, Display On/Off.
Page 923 Initial Bit Name Value ⎯ 9, 8 All 0 7 to 2 BPOB Undefined R/W ⎯ 1, 0 All 0 Internal Update Description ⎯ Reserved These bits are always read as 0. The write value should always be 0. Background Plane Output Blue The blue-color display data to be output when there is no plane for display should be set.
Page 924: Raster Interrupt Offset Register (Rintofsr)
19. Display Unit (DU) 19.3.30 Raster Interrupt Offset Register (RINTOFSR) The raster interrupt offset register (RINTOFSR) sets the raster offset value for raster interrupts. The value is retained during power-on reset and manual reset. Bit: — — — Initial value: R/W: Internal update: Bit:...
Page 925: Plane N Mode Register (Pnmr) (N = 1 To 6)
19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6) The plane n mode registers (PnMR, n = 1 to 6) set the display operation for plane n. Bit: — — — Initial value: R/W: Internal update: Bit: — PnSPIM Initial value: R/W:...
Page 926 19. Display Unit (DU) Initial Bit Name Value 14 to 12 PnSPIM ⎯ 11, 10 All 0 Rev.1.00 Jan. 10, 2008 Page 896 of 1658 REJ09B0261-0100 Internal Update Description Plane n Super Impose Mode 000: Transparent color processing is performed for plane n.
Page 927 Initial Bit Name Value 9, 8 PnCPSL PnDC ⎯ 5, 4 PnBM ⎯ 3, 2 All 0 1, 0 PnDDF Internal Update Description Plane n Color Palette Select When the PnDDF bit is set to 8 bits/pixel, specifies the color palette to be used. 00: Selects the color palette 1 01: Selects the color palette 2 10: Selects the color palette 3...
Page 928: Plane N Memory Width Register (Pnmwr) (N = 1 To 6)
19. Display Unit (DU) 19.3.32 Plane n Memory Width Register (PnMWR) (n = 1 to 6) The plane n memory width registers (PnMWR, n = 1 to 6) set the memory width for plane n. The value is retained during power-on reset and manual reset. Bit: —...
Page 929: Plane N Blending Ratio Register (Pnalphar) (N = 1 To 6)
19.3.33 Plane n Blending Ratio Register (PnALPHAR) (n = 1 to 6) The plane n blending ratio registers (PnALPHAR, n = 1 to 6) set the blend ratios and blend ratio selection for plane n. Bit: — — — Initial value: R/W: Internal update: Bit:...
Page 930 19. Display Unit (DU) Initial Bit Name Value 9, 8 PnBRSL Rev.1.00 Jan. 10, 2008 Page 900 of 1658 REJ09B0261-0100 Internal Update Description R/W Yes Plane n Blending Ratio Select This bit is valid when the following two conditions are satisfied.
Page 931: Plane N Display Size X Register (Pndsxr) (N = 1 To 6)
Initial Bit Name Value 7 to 0 Undefined R/W PnALPHA 19.3.34 Plane n Display Size X Register (PnDSXR) (n = 1 to 6) The plane n display size X registers (PnDSXR, n = 1 to 6) set the display size in the horizontal direction of plane n.
Page 932: Plane N Display Size Y Register (Pndsyr) (N = 1 To 6)
19. Display Unit (DU) 19.3.35 Plane n Display Size Y Register (PnDSYR) (n = 1 to 6) The plane n display size Y registers (PnDSYR, n = 1 to 6) set the display size in the vertical direction for plane n. The value is retained during power-on reset and manual reset. Bit: —...
Page 933: Plane N Display Position X Register (Pndpxr) (N = 1 To 6)
19.3.36 Plane n Display Position X Register (PnDPXR) (n = 1 to 6) The plane n display position X registers (PnDPXR, n = 1 to 6) set the horizontal start positions on the display monitor for plane n. The value is retained during power-on reset and manual reset. Bit: —...
Page 934: Plane N Display Position Y Register (Pndpyr) (N = 1 To 6)
19. Display Unit (DU) 19.3.37 Plane n Display Position Y Register (PnDPYR) (n = 1 to 6) The plane n display position Y registers (PnDPYR, n = 1 to 6) set the vertical start position on the display monitor of plane n. The value is retained during power-on reset and manual reset. Bit: —...
Page 935: Plane N Display Area Start Address 0 Register (Pndsa0R) (N = 1 To 6)
19.3.38 Plane n Display Area Start Address 0 Register (PnDSA0R) (n = 1 to 6) The plane n display area start address 0 registers (PnDSA0R, n = 1 to 6) set the memory area in frame buffer 0 for plane n. The value is retained during power-on reset and manual reset. Bit: Initial value: —...
Page 936: Plane N Display Area Start Address 1 Register (Pndsa1R) (N = 1 To 6)
19. Display Unit (DU) 19.3.39 Plane n Display Area Start Address 1 Register (PnDSA1R) (n = 1 to 6) The plane n display area start address 1 registers (PnDSA1R, n = 1 to 6) set the memory area in frame buffer 1 for plane n. The value is retained during power-on reset and manual reset. Bit: Initial value: —...
Page 937: Plane N Start Position X Register (Pnspxr) (N = 1 To 6)
19.3.40 Plane n Start Position X Register (PnSPXR) (n = 1 to 6) The plane n start position X registers (PnSPXR, n = 1 to 6) set the horizontal start position of plane n in memory. The value is retained during power-on reset and manual reset. Bit: —...
Page 938: Plane N Start Position Y Register (Pnspyr) (N = 1 To 6)
19. Display Unit (DU) 19.3.41 Plane n Start Position Y Register (PnSPYR) (n = 1 to 6) The plane n start position Y registers (PnSPYR, n = 1 to 6) set the vertical start position of plane n in memory. The value is retained during power-on reset and manual reset. Bit: —...
Page 939: Plane N Wrap Around Start Position Register (Pnwaspr) (N = 1 To 6)
19.3.42 Plane n Wrap Around Start Position Register (PnWASPR) (n = 1 to 6) The plane n wrap-around start position registers (PnWASPR, n = 1 to 6) set the Y direction start position of one wrap-around area of plane n. The value is retained during power-on reset and manual reset.
Page 940: Plane N Wrap Around Memory Width Register (Pnwamwr) (N = 1 To 6)
19. Display Unit (DU) 19.3.43 Plane n Wrap Around Memory Width Register (PnWAMWR) (n = 1 to 6) The plane n wrap-around memory width registers (PnWAMWR, n = 1 to 6) set the wrap-around Y-direction memory width for plane n. The value is retained during power-on reset and manual reset.
Page 941: Plane N Blinking Time Register (Pnbtr) (N = 1 To 6)
19.3.44 Plane n Blinking Time Register (PnBTR) (n = 1 to 6) The plane n blinking time registers (PnBTR, n = 1 to 6) set the display interval length for plane n. When the PnBM bit in PnMR is set to the auto display change mode (blinking mode), by setting, in this register, the length of the interval of display of PnDSA0R and PnDSA1R, blinking operation is performed using PnDSA0R and PnDSA1R.
Page 942: Plane N Transparent Color 1 Register (Pntc1R) (N = 1 To 6)
19. Display Unit (DU) 19.3.45 Plane n Transparent Color 1 Register (PnTC1R) (n = 1 to 6) The plane n transparent color 1 registers (PnTC1R, n = 1 to 6) set a transparent color for plane n, in 8 bits/pixel data format. The value is retained during power-on reset and manual reset. Bit: —...
Page 943: Plane N Transparent Color 2 Register (Pntc2R) (N = 1 To 6)
19.3.46 Plane n Transparent Color 2 Register (PnTC2R) (n = 1 to 6) The plane n transparent color 2 registers (PnTC2R, n = 1 to 6) set a transparent color for plane n in the 16 bits/pixel, ARGB data format. The value is retained during power-on reset and manual reset.
Page 944: Plane N Memory Length Register (Pnmlr) (N = 1 To 6)
19. Display Unit (DU) 19.3.47 Plane n Memory Length Register (PnMLR) (n = 1 to 6) The plane n memory length registers (PnMLR, n = 1 to 6) set the memory length (Y-direction memory area) for plane n. Bit: — —...
Page 945: Color Palette 1 Register 000 To 255 (Cp1_000R To Cp1_255R)
19.3.48 Color Palette 1 Register 000 to 255 (CP1_000R to CP1_255R) The color palette 1 registers 000 to 255 (CP1_000R to CP1_255R) are a group of 256 registers which set six bits for each of the RGB components of a color, and are used as a color palette capable of displaying 256 colors among 260,000 possible colors.
Page 946: Color Palette 2 Register 000 To 255 (Cp2_000R To Cp2_255R)
19. Display Unit (DU) Initial Bit Name Value ⎯ 9, 8 All 0 7 to 2 Undefined R/W CP1_000B to CP1_255B ⎯ 1, 0 All 0 19.3.49 Color Palette 2 Register 000 to 255 (CP2_000R to CP2_255R) The color palette 2 registers 000 to 255 (CP2_000R to CP2_255R) are a group of 256 registers which set six bits for each of the RGB components of a color, and are used as a color palette capable of displaying 256 colors among 260,000 possible colors.
Page 947 Initial Bit Name Value 31 to 24 Undefined R/W CP2_000A to CP2_255A 23 to 18 Undefined R/W CP2_000R to CP2_255R ⎯ 17, 16 All 0 15 to 10 Undefined R/W CP2_000G to CP2_255G ⎯ 9, 8 All 0 7 to 2 Undefined R/W CP2_000B to CP2_255B...
Page 948: Color Palette 3 Register 000 To 255 (Cp3_000R To Cp3_255R)
19. Display Unit (DU) 19.3.50 Color Palette 3 Register 000 to 255 (CP3_000R to CP3_255R) The color palette 3 registers 000 to 255 (CP3_000R to CP3_255R) are a group of 256 registers which set six bits for each of the RGB components of a color, and are used as a color palette capable of displaying 256 colors among 260,000 possible colors.
Page 949: Color Palette 4 Register 000 To 255 (Cp4_000R To Cp4_255R)
Initial Bit Name Value ⎯ 9, 8 All 0 7 to 2 Undefined R/W CP3_000B to CP3_255B ⎯ 1, 0 All 0 19.3.51 Color Palette 4 Register 000 to 255 (CP4_000R to CP4_255R) The color palette 4 registers 000 to 255 (CP4_000R to CP4_255R) are a group of 256 registers which set six bits for each of the RGB components of a color, and are used as a color palette capable of displaying 256 colors among 260,000 possible colors.
Page 950 19. Display Unit (DU) Initial Bit Name Value 31 to 24 Undefined R/W CP4_000A to CP4_255A 23 to 18 Undefined R/W CP4_000R to CP4_255R ⎯ 17, 16 All 0 15 to 10 Undefined R/W CP4_000G to CP4_255G ⎯ 9, 8 All 0 7 to 2 Undefined R/W...
Page 951: External Synchronization Control Register (Escr)
19.3.52 External Synchronization Control Register (ESCR) The external synchronization control register (ESCR) controls the dot clock. Bit: — — — Initial value: R/W: Internal update: Bit: — — — Initial value: R/W: Internal update: Initial Bit Name Value 31 to 21 ⎯ All 0 DCLKSEL 19 to 17 ⎯...
Page 952 19. Display Unit (DU) Initial Bit Name Value 4 to 0 FRQSEL 0 R/W None Rev.1.00 Jan. 10, 2008 Page 922 of 1658 REJ09B0261-0100 Internal Update Description Frequency Select To enable this bit, the DCKE bit in DEFR should be set to 1. In the initial state, bit 4 is fixed at 0, and the frequency division ratio is up to 16.
Page 953: Output Signal Timing Adjustment Register (Otar)
19.3.53 Output Signal Timing Adjustment Register (OTAR) The output signal timing adjustment register (OTAR) selects the timing for the output signal. For information on adjustment timing, refer to section 19.5.5, Output Signal Timing Adjustment. Bit: — Initial value: R/W: Internal update: Bit: —...
Page 954 19. Display Unit (DU) Initial Bit Name Value 30 to 28 DEA ⎯ Rev.1.00 Jan. 10, 2008 Page 924 of 1658 REJ09B0261-0100 Internal Update Description None DE Output Timing Adjustment 000: Adjustment of output timing is not performed. The DE signal is output at the rising edge of the dot clock, with the reference timing.
Page 955 Initial Bit Name Value 26 to 24 CLAMPA 0 ⎯ Internal Update Description None CLAMP Output Timing Adjustment 000: Adjustment of output timing is not performed. The CLAMP signal is output at the rising edge of the dot clock, with the reference timing.
Page 956 19. Display Unit (DU) Initial Bit Name Value 22 to 20 DRGBA ⎯ 18 to 16 ⎯ All 0 15 to 11 ⎯ All 0 Rev.1.00 Jan. 10, 2008 Page 926 of 1658 REJ09B0261-0100 Internal Update Description None Digital IRGV Output Timing Adjustment 000: Adjustment of output timing is not performed.
Page 957 Initial Bit Name Value 10 to 8 CDEA ⎯ Internal Update Description None CDE Output Timing Adjustment 000: Adjustment of output timing is not performed. The CDE signal is output at the rising edge of the dot clock, with the reference timing. 001: The CDE signal is output at the rising edge, delayed one dot clock cycle relative to the reference timing.
Page 958 19. Display Unit (DU) Initial Bit Name Value 6 to 4 DISPA ⎯ Rev.1.00 Jan. 10, 2008 Page 928 of 1658 REJ09B0261-0100 Internal Update Description None DISP Output Timing Adjustment 000: Adjustment of output timing is not performed. The DISP signal is output at the rising edge of the dot clock, with the reference timing.
Page 959 Initial Bit Name Value 2 to 0 SYNCA Internal Update Description None SYNC* Output Timing Adjustment 000: Adjustment of output timing is not performed. The SYNC* signal is output at the rising edge of the dot clock, with the reference timing.
Page 960: Configuration Of Output Screen
19. Display Unit (DU) 19.4 Operation 19.4.1 Configuration of Output Screen The display unit (DU) executes window displays with up to a maximum of six window layers. Each of these windows is called a "plane", and the order of stacking of the planes can be set arbitrarily.
Page 961 Table 19.4 Display Functions of Planes Display Data Format Display 8 bits/ bits/ On/Off pixel pixel ARGB Plane 1 O Plane 2 O Plane 3 O Plane 4 O Plane 5 O Plane 6 O × × × Back- ground color* Notes: 1.
Page 962 19. Display Unit (DU) Output planes are combined and displayed according to the superpositioning order and blending mode for each plane. Display side Frame Frame buffer 1 buffer 2 A double-buffer function is used to switch the frame buffer between drawing side and display side Figure 19.2 Block Diagram of Plane Configuration and Superpositioning Rev.1.00 Jan.
Page 963: Display On/Off
19.4.2 Display On/Off All plane display can be turned on and off using the DEN bit in DSYSR. When the DEN bit is 0, the display data set in DOOR is displayed. Display is turned on and off for planes 1 to 6 using DPPR. Under the following display conditions, display data set in BPOR is displayed.
Page 964: Plane Parameter
19. Display Unit (DU) 19.4.3 Plane Parameter For each plane, a display area start position, memory width, display start position, and display size are set using registers. The followings are the schematic diagram of start positions and sizes related to planes and the registers used for setting start positions and sizes.
Page 965 Table 19.6 Memory Parameter/ Monitor Parameter Setting Registers Names Used in the Figure (Plane memory width) (Display area start address) WASPY (Plane n wrap-around start position) WAMWY (Wraparound memory width) (Start position X) (Start position Y) (Display size X) (Display size Y) (Display position X) (Display position Y) (Memory length Y)
Page 966: Memory Allocation
19. Display Unit (DU) 19.4.4 Memory Allocation A display start address for the display screen can be set individually for each plane. Leading addresses for the memory areas used are set in each of the display area start address registers. In the display unit (DU), the display area start addresses 0 and 1 are used for each plane to perform double-buffer control and display each plane.
Page 967: Input Display Data Format
19.4.5 Input Display Data Format The following format is used for input color data used in display. • 8 bit/pixel A color palette index is used. The color palette is used to convert and display image data into RGB data with 6 bits for each RGB color (RGB666). The arrangement of data in memory is as follows.
Page 968 19. Display Unit (DU) • 16 bit/pixel: ARGB The ARGB levels are represented using A:1, R:5, G:5, B:5 bits (ARGB555). In addition to the RGB values, an alpha value is set. Blending control using the A value is valid when the PnSPIM bit in PnMR is set to perform blending;...
Page 969 • UYVY format Address A Address A+4 Address A+8 Little endian • YUYV format Address A Address A+4 Address A+8 Little endian Address A Address A+4 Address A+8 Address A Address A+4 Address A+8 Rev.1.00 Jan. 10, 2008 Page 939 of 1658 19.
Page 970: Output Data Format
19. Display Unit (DU) 19.4.6 Output Data Format When outputting digital RGB data from the display unit (DU), the display data format is expanded into the RGB666 format before output. The format at the time of output is as indicated in the following table.
Page 971 Endian conversion in each of the units indicated below is shown in figure 19.4. Endian Conversion in Byte Units: PnDDF = 0 0: 8 bits/pixel PnDDF = 1 1: YC Address A + 8 Endian Conversion in Word Units: PnDDF = 0 1: 16 bits/pixel PnDDF = 1 0: ARGB Address A + 8...
Page 972: Color Palettes
19. Display Unit (DU) 19.4.8 Color Palettes 8 bits/pixel data employs color palettes. Four color palettes can be used; these are called color palette 1, color palette 2, color palette 3, and color palette 4. The color palette used in each plane can be set to any among color palette 1, color palette 2, color palette 3, and color palette 4 using the PnCPSL bits in PnMR.
Page 973: Superpositioning Of Planes
19.4.9 Superpositioning of Planes For each plane, three types of combined superpositioning are possible: α blending, transparent colors, and EOR operations. By setting the PnSPIM bits in PnMR, the superpositioned display type can be selected. However, α blending and EOR operation cannot be performed simultaneously on the same plane. α...
Page 974 19. Display Unit (DU) Table 19.11 RGB888 Bit Configuration in Each Display Data Format Data Format R (8 bits) 8 bits/pixel R (6 bits) 16 bits/pixel R (5 bits) ARGB R (5 bits) YC→RGB R (8 bits) Plane with priority 1 Plane with priority 2 Plane with priority 3 Plane with priority 4...
Page 975 When the PnDDF bit in PnMR is set to ARGB, and moreover the PnSPIM bit in PnMR is set to perform blending, α blending is performed according to the A value of the input ARGB data format. Transparent Colors: For each plane, transparent color processing can be performed between the specified plane and the lower plane by setting PnSPIM bit in PnMR to 0.
Page 976 19. Display Unit (DU) Table 19.12 Transparent Color Specification Registers Transparent Color Data Format Specification Bit ⎯ (PnMR) /PnTC 8 bits/pixel ⎯ 16 bits/pixel ⎯ ARGB EOR Operation: EOR operation of the specified plane with the lower plane is performed. Rev.1.00 Jan.
Page 977: Display Contention
19.4.10 Display Contention Color Palette Contention: When performing α blending and EOR operations, if the same color palette is selected for both planes with the input display data format at 8 bits/pixel, color palette contention may occur. This is because contention decisions occur not in plane units, but in pixel units.
Page 978 19. Display Unit (DU) Color palette selection Δ: Same color palette selected; X: Different color palette selected Transparent color Non-transparent color Figure 19.7 Results of Display Combining Color Palette Selection and Transparent Colors YC Data Contention: The display unit (DU) has only one YC-RGB conversion circuit internally, and so YC-RGB conversion cannot be performed simultaneously for two or more planes.
Page 979: Blinking
Plane Priority Order: The display priority order for planes is set using DPPR; if one plane is set in two or more places in the priority order, the place with highest priority is selected. For example, if the setting in DPPR is H'00CBD888, then the results of the priority order and display on/off settings are as follows.
Page 980: Scroll Display
19. Display Unit (DU) 19.4.12 Scroll Display By setting display area and display screen sizes and start positions independently for each plane, smooth scroll processing can be performed independently for each plane. The display can be scrolled by cyclically setting the plane n display start position X, Y values (coordinates specified by PnSPXR and PnSPYR), taking as the origin the leading address in memory specified by PnDSA0R and PnDSA1R for each plane.
Page 981: Wraparound Display
19.4.13 Wraparound Display In addition to display scrolling, wrap-around display, which can be used in spherical scrolling, is possible for each plane. When enabling wrap-around display, the PnWAE bit in PnMR is set. As a result of changing the plane n display start position X, Y (the plane n start position X set in PnSPXR and the plane n start position Y set in PnSPYR) in order to scroll the display, even when plane n overflows the wrap-around area, the wrap-around area is seen as a spherical surface in wrap-around display, as in figure 19.10, and the part overflowing is complemented and displayed.
Page 982: Upper-Left Overflow Display
19. Display Unit (DU) 19.4.14 Upper-Left Overflow Display For each plane, a display start position in memory (PnSPXR, PnSPYR) and display size (PnDSXR, PnDSYR) can be set arbitrarily, so that by combining and using these registers, areas overflowing the upper-left relative to the monitor origin (upper-left corner) can be displayed without overwriting display data in memory.
Page 983: Double Buffer Control
19.4.15 Double Buffer Control The double buffer control of the display unit (DU) includes two types of functions, which are a manual display change mode in which display switching is all controlled by software, and an auto display change mode to realize blinking. In the case of manual display change mode, the display change is performed in frame units for non-interlaced and interlaced sync display, and in field units for interlaced sync &...
Page 984: Sync Mode
19. Display Unit (DU) 19.4.16 Sync Mode In order to facilitate synchronization with external equipment, in addition to master mode, a TV synchronization function is provided. Selection of master mode and TV sync mode is performed using the TVM bit in DSYSR. Regardless of the synchronization method, the position of the falling edge of the vertical sync signal (VSYNC) set by VSPR is detected and is reflected in the FRM bit and VBK bit in DSSR.
Page 985 TV (sync signal generation circuit): Master Clock HSYNC VSYNC HSYNC VSYNC DCLKIN This LSI: Slave Figure 19.12 Signal Flow in TV Sync Mode Sync Method Switching Mode: When switching from master mode into TV sync mode, or from TV sync mode into master mode, when necessary this mode should be switched into first. Even if a transition to this mode is not made first, switching of the synchronization method is possible.
Page 986: Display Control
19. Display Unit (DU) 19.5 Display Control 19.5.1 Display Timing Generation In the display unit (DU), display timing is generated for the horizontal direction and vertical direction of the display screen. Display timing is set by using display timing generation registers. Figure 19.13 shows the display timing in non-interlaced mode.
Page 987 Table 19.13 Variables Defined in Display Screen Variables Contents Horizontal scan period Horizontal sync pulse width From rise of HSYNC to display start position in the horizontal direction of the display screen Display width per 1 raster of display screen Vertical scan period Vertical sync pulse width From rise of VSYNC to display start position in the...
Page 988 19. Display Unit (DU) Table 19.14 Correspondence Table of Settings of Display Timing Generation Registers Register Name Horizontal display start position register (HDSR) Horizontal display end position register (HDER) Vertical display start position register (VDSR) Vertical display end position register (VDER) Horizontal synchronous pulse width register (HSWR)
Page 989: Csync
19.5.2 CSYNC When in master mode, a CSYNC (composite sync) signal is output. EQWR is used to set the low- level pulse width of the CSYNC equal pulse. SPWR is used to set the low-level pulse width of the CSYNC separation pulse. The CSYNC waveform is selected using the CSY bit in DSMR.
Page 990 19. Display Unit (DU) HSYNC VSYNC 1/2HC CSYNC (CSY = 00) (CSY = 10) Equivalent pulse: 3 rasters (CSY = 11) 1/2HC Equivalent pulse: 2.5 rasters When HC is odd, it is rounded to an even value. Figure 19.15 CSYNC Timing Chart (Last Half of Interlace Frame) Rev.1.00 Jan.
Page 991: Scan Method
19.5.3 Scan Method The scan method can be selected from among non-interlaced mode, interlaced sync mode, and interlaced sync & video mode. The mode is selected using the SCM bit in DSYSR. • Non-interlaced mode In this scan method, one frame consists of a single field. •...
Page 992 19. Display Unit (DU) Non-interlaced mode Interlaced sync & video mode Figure 19.16 Example of Display in Each Scan Mode Rev.1.00 Jan. 10, 2008 Page 962 of 1658 REJ09B0261-0100 Interlaced sync mode Raster scanned in an odd field Raster scanned in an even field...
Page 993 • Example of vertical scan period Non-interlaced mode: Interlaced mode: Interlaced sync & video mode: 1/30 second/frame • Display in non-interlaced method In this method, all lines are displayed at once without providing intervals between input video signals. This input method is for monitors capable of high-resolution display. Display in non-interlaced mode The ODEV and ODDF pins are not used.
Page 994 19. Display Unit (DU) • Display in interlaced method At every scan period VC of the input video signal, even lines and odd lines are switched and displayed in alternation, and a single screen (one frame) is combined and displayed (with the afterimage of the preceding VC) with a period of 2VC.
Page 995: Color Detection
19.5.4 Color Detection When output display data matches a color set in CDER, high level is output from the CDE pin. The CDEM bit in DSMR can be used to fix the level outside display intervals. Also, the CDEL bit in DSMR can be used to select the polarity of the output level.
Page 996: Output Signal Timing Adjustment
19. Display Unit (DU) 19.5.5 Output Signal Timing Adjustment The display unit (DU) enables selection of output timing, with respect to the output dot clock, of the various output signals (the four sync signals HSYNC, VSYNC, CSYNC, ODDF, as well as DISP, CDE, CLAMP, DE, digital RGB signals).
Page 997: Clamp Signal And De Signal
19.5.6 CLAMP Signal and DE Signal The display unit (DU) generates a CLAMP signal and DE signal, independent of the DISP signal indicating the display interval. The rising-edge start position and high-level width of the CLAMP signal and DE signal, with reference to the HSYNC signal falling edge, can be set in dot clock units.
Page 998: Power-Down Sequence
19. Display Unit (DU) 19.6 Power-Down Sequence When executing the power-down sequence by the following modes or functions, turn off the display in advance. 1. Sleep mode 2. Deep sleep mode 3. Module standby 4. Change of frequency 5. Manual reset Even when the display unit (DU) enters the power-down sequence, the register values are retained.
Page 999: Section 20 Graphics Data Translation Accelerator (Gdta)
Section 20 Graphics Data Translation Accelerator (GDTA) This block incorporates a YUV data conversion processing module (CL) that converts data in the YUV 4:2:0 format to YUV 4:2:2 or ARGB format, as well as a video processing module (MC) that generates estimated images using motion vectors. A GADMAC is provided within the GDTA;...
Page 1000 20. Graphics Data Translation Accelerator (GDTA) Figure 20.1 shows the GDTA block diagram. External memory LBSC (external) GDTA Target interface Response Request queue queue (4 planes) (4 planes) Control register Buffer RAM CL/MC interface interface Rev.1.00 Jan. 10, 2008 Page 970 of 1658 REJ09B0261-0100 SuperHyway bus Initiator interface...

This manual is also suitable for:

Sh7785

Renesas SH7781 Hardware Manual

Section 1 Overview

Section 2 Programming Model

Section 3 Instruction Set

Section 4 Pipelining

Section 5 Exception Handling

Section 6 Floating-Point Unit (FPU)

Section 7 Memory Management Unit (MMU)

Section 8 Caches

Section 9 On-Chip Memory

Section 10 Interrupt Controller (INTC)

Section 11 Local Bus State Controller (LBSC)

Section 12 DDR2-SDRAM Interface (DBSC2)

Section 13 PCI Controller (PCIC)

Section 14 Direct Memory Access Controller (DMAC)

Quick Links

Related Manuals for Renesas SH7781

Summary of Contents for Renesas SH7781