Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7705 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series ™ Rev.2.00 2003.9.19...
Page 3 Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series SH7705 Group Hardware Manual REJ09B0082-0200O...
Page 4 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.
Page 5: General Precautions On Handling Of Product
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 6: Table Of Contents
Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 7: Preface
Renesas Technology original RISC CPU as its core, and the peripheral functions required to configure a system. Target users: This manual was written for users who will be using the SH7705 Micro-Computer Unit (MCU) in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
Page 8 The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ SH7705 manuals: Manual Title ADE No. SH7705 Hardware Manual This manual SH-3/SH-3E/SH3-DSP Programming Manual ADE-602-096 Users manuals for development tools: Manual Title ADE No.
Page 9 Abbreviations Analog to Digital Converter Arithmetic Logic Unit Adaptive System Evaluator ASID Address Space Identifier Advanced User Debugger Binary Coded Decimal bit per second Bus State Controller Cache Memory Controller Compare Match Timer Clock Pulse Generator Central Processing Unit DMAC Direct Memory Access Controller Elementary Time Unit FIFO...
Page 10 SDRAM Synchronous DRAM Test Access Port T.B.D To Be Determined Translation Lookaside Buffer Timer Unit Timer Pulse Unit UART Universal Asynchronous Receiver/Transmitter User Break Controller Universal Serial Bus Watchdog Timer Rev. 2.00, 09/03, page x of xlvi...
Page 11 Main Revisions and Additions in this Edition Item Page Revisions (See Manual for Details) 1.1 SH7705 Features Features of USB function module (USB) amended • Conforms to USB 2.0 full-speed specification Table 1.1 SH7705 Features 1.3 Pin Assignment 13, 15, Note *6, *7 added Table 1.2 Pin Functions...
Page 12 Item Page Revisions (See Manual for Details) 6.1 Features CMT deleted Figure 6.1 Block Diagram of INTC Input/output IRQ5−IRQ0 control PINT15−PINT0 (Interrupt request) DMAC SCIF Legend: DMAC : Direct memory access controller SCIF : Serial communication interface (with FIFO) : A/D converter : USB interface : Timer pulse unit : 16-bit timer pulse unit...
Page 13 Item Page Revisions (See Manual for Details) 7.13 Others In standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At manual reset, the Reset current bus cycle being executed is completed and then the access wait state is entered.
Page 14 Item Page Revisions (See Manual for Details) 9.1 Features Figure amended Figure 9.1 Block Diagram Bus interface of Clock Pulse Generator Peripheral bus Note added 10.2.2 Watchdog Timer Control/Status Register Note: If manual reset is selected using the RSTS bit, a (WTCSR) frequency division ratio of 1/16, 1/32, 1/64, 1/256, 1/1,024, or 1/4,096 is selected using bits CKS2 to CKS0, and a...
Page 15 Item Page Revisions (See Manual for Details) 22.2.10 Execution Times Note added Break Register (BETR) Note: If the channel B brake condition set to during instruction fetch cycles and any of the instructions below perform breaks, BETR is not decremented when the first break occurs. The decremented values are listed below.
Page 16 Item Page Revisions (See Manual for Details) 25.3.1 Clock Timing Figure amended Stable oscillation Figure 25.5 Power-On CKIO, Oscillation Settling Time internal clock RESPW RESPS OSC1 RESETP TRST 25.3.2 Control Signal Conditions amended Timing (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, Table 25.6 Control Signal -PLL1 = V...
Page 17 Item Page Revisions (See Manual for Details) 25.3.4 Basic Timing Note *2 added Figure 25.18 Basic Bus Cycle (One External Wait) WEn * Write WDH1 WDD1 D31 to D0 Notes: 1. DACKn is a waveform when active-low is specified. 2. Output timing is the same when reading byte-selection SRAM. Figure 25.19 Basic Bus Note *2 added Cycle (One Software Wait,...
Page 18 Item Page Revisions (See Manual for Details) A. I/O Port States in Each 682, Note *13 added Processing State Power-Down Reset States Table A.1 I/O Port States Power- Handling in Each Processing State Manual Software Mastership of Unused Category Pin Reset Sleep Released...
Page 19: Contents
Contents Section 1 Overview ..................1 SH7705 Features......................1 Block Diagram......................6 Pin Assignment......................7 Pin Functions....................... 17 Section 2 CPU ....................25 Processing States and Processing Modes............... 25 2.1.1 Processing States ..................... 25 2.1.2 Processing Modes.................... 26 Memory Map ....................... 27 2.2.1...
Page 20 3.3.2 TLB Indexing....................77 3.3.3 TLB Address Comparison ................78 3.3.4 Page Management Information ................ 80 MMU Functions ......................81 3.4.1 MMU Hardware Management ................. 81 3.4.2 MMU Software Management ................81 3.4.3 MMU Instruction (LDTLB)................82 3.4.4 Avoiding Synonym Problems ................83 MMU Exceptions ......................
Page 21 5.1.3 Interrupt Event Register (INTEVT)..............111 5.1.4 Interrupt Event Register 2 (INTEVT2)............. 112 5.1.5 Exception Address Register (TEA) ..............112 Exception Handling Function ..................113 5.2.1 Exception Handling Flow ................113 5.2.2 Exception Vector Addresses ................114 5.2.3 Exception Codes....................114 5.2.4 Exception Request and BL Bit (Multiple Exception Prevention).......
Page 22 Pin Configuration ......................151 Area Overview......................152 7.3.1 Address Map....................152 7.3.2 Memory Bus Width ..................154 7.3.3 Shadow Space ....................155 Register Descriptions....................155 7.4.1 Common Control Register (CMNCR).............. 156 7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)..158 7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) .
Page 23 8.3.3 DMA Transfer Count Registers (DMATCR)............ 243 8.3.4 DMA Channel Control Registers (CHCR)............243 8.3.5 DMA Operation Register (DMAOR) ............... 248 8.3.6 DMA Extended Resource Selectors 0, 1 (DMARS0, DMARS1)....... 250 Operation........................252 8.4.1 Transfer Flow....................252 8.4.2 DMA Transfer Requests .................. 254 8.4.3 Channel Priority ....................
Page 24 11.3 Register Descriptions....................295 11.3.1 Standby Control Register (STBCR) ..............296 11.3.2 Standby Control Register 2 (STBCR2)............. 297 11.3.3 Standby Control Register 3 (STBCR3)............. 298 11.4 Sleep Mode........................299 11.4.1 Transition to Sleep Mode................. 299 11.4.2 Canceling Sleep Mode..................299 11.5 Software Standby Mode ....................
Page 25 13.2.3 Compare Match Counter (CMCNT)..............326 13.2.4 Compare Match Constant Register (CMCOR)..........326 13.3 Operation........................326 13.3.1 Period Count Operation ................... 326 13.3.2 CMCNT Count Timing..................327 13.3.3 Compare Match Flag Set Timing ..............327 Section 14 16-Bit Timer Pulse Unit (TPU) ............ 329 14.1 Features ........................
Page 26 15.3.15 Year Alarm Register (RYRAR) ............... 364 15.3.16 RTC Control Register 1 (RCR1) ..............365 15.3.17 RTC Control Register 2 (RCR2) ..............366 15.3.18 RTC Control Register 3 (RCR3) ..............368 15.4 Operation ........................369 15.4.1 Initial Settings of Registers after Power-On ............. 369 15.4.2 Setting Time....................
Page 27 17.3 Register Description..................... 432 17.3.1 IrDA Mode Register (SCSMR_Ir)..............432 17.4 Operation........................434 17.4.1 Overview......................434 17.4.2 Transmitting....................434 17.4.3 Receiving ......................435 17.4.4 Data Format Specification ................435 Section 18 USB Function Module..............437 18.1 Features ........................437 18.2 Input/Output Pins......................439 18.3 Register Descriptions ....................
Page 28 18.6.2 Forcible Stall by Application ................465 18.6.3 Automatic Stall by USB Function Module ............467 18.7 DMA Transfer ......................468 18.7.1 Overview ......................468 18.7.2 DMA Transfer for Endpoint 1................468 18.7.3 DMA Transfer for Endpoint 2................469 18.8 Example of USB External Circuitry................470 18.9 Usage Notes.........................
Page 29 20.3 Port C .......................... 510 20.3.1 Register Description ..................510 20.3.2 Port C Data Register (PCDR)................510 20.4 Port D.......................... 511 20.4.1 Register Description ..................511 20.4.2 Port D Data Register (PDDR) ................511 20.5 Port E .......................... 513 20.5.1 Register Description ..................513 20.5.2 Port E Data Register (PEDR) ................
Page 30 21.4 Operation ........................533 21.4.1 Single Mode....................533 21.4.2 Multi Mode ..................... 533 21.4.3 Scan Mode ...................... 534 21.4.4 Input Sampling and A/D Conversion Time............534 21.5 Interrupts and DMAC Transfer Request ............... 536 21.6 Definitions of A/D Conversion Accuracy ..............536 21.7 Usage Notes.........................
Page 31: List Of Registers
23.2 Input/Output Pins......................568 23.3 Register Descriptions ....................569 23.3.1 Bypass Register (SDBPR)................569 23.3.2 Instruction Register (SDIR) ................569 23.3.3 Boundary Scan Register (SDBSR) ..............570 23.3.4 ID Register (SDID)..................577 23.4 Operation........................578 23.4.1 TAP Controller....................578 23.4.2 Reset Configuration..................579 23.4.3 TDO Output Timing ..................
Page 32 25.3.16 AC Characteristics Measurement Conditions ........... 677 25.4 A/D Converter Characteristics..................678 Appendix .....................679 I/O Port States in Each Processing State ............... 679 Package Dimensions ....................685 Index .....................687 Rev. 2.00, 09/03, page xxxii of xlvi...
Page 33 Figures Section 1 Overview Figure 1.1 Block Diagram of SH7705 ..................6 Figure 1.2 Pin Assignment (FP-208C) ..................7 Figure 1.3 Pin Assignment (TBP-208A)..................8 Section 2 CPU Figure 2.1 Processing State Transitions..................26 Figure 2.2 Logical Address to External Memory Space Mapping ..........29 Figure 2.3 Register Configuration in Each Processing Mode ............
Page 34 Figure 6.2 Example of IRL Interrupt Connection ..............137 Figure 6.3 Interrupt Operation Flowchart................146 Section 7 Bus State Controller (BSC) Figure 7.1 BSC Functional Block Diagram ................150 Figure 7.2 Address Space ...................... 154 Figure 7.3 Continuous Access for Normal Space (No Wait, WM Bit in CSnWCR = 1, 16-Bit Bus Width, Longword Access, No Wait State between Cycles) ....
Page 35 Section 8 Direct Memory Access Controller (DMAC) Figure 8.1 Block Diagram of DMAC ..................240 Figure 8.2 DMAC Transfer Flowchart ................... 253 Figure 8.3 Round-Robin Mode ....................258 Figure 8.4 Channel Priority in Round-Robin Mode ..............259 Figure 8.5 Data Flow of Dual Address Mode ................. 261 Figure 8.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory)........
Page 36 Figure 11.10 Hardware Standby Mode (When CA Goes Low in Normal Operation)....307 Figure 11.11 Hardware Standby Mode Timing (When CA Goes Low during WDT Operation while Standby Mode Is Canceled) ..........307 Section 12 Timer Unit (TMU) Figure 12.1 TMU Block Diagram ..................310 Figure 12.2 Setting Count Operation..................
Page 37 Figure 16.2 Sample SCIF Initialization Flowchart ..............406 Figure 16.3 Sample Serial Transmission Flowchart ..............407 Figure 16.4 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) ..........409 Figure 16.5 Example of Transmit Data Stop Function ............409 Figure 16.6 Transmit Data Stop Function Flowchart ..............
Page 38: Electrical Characteristics
Figure 18.12 Operation of EP3 Interrupt-In Transfer.............. 463 Figure 18.13 Forcible Stall by Application................466 Figure 18.14 Automatic Stall by USB Function Module............467 Figure 18.15 RDFN Bit Operation for EP1 ................468 Figure 18.16 PKTE Bit Operation for EP2................469 Figure 18.17 Example of USB Function Module External Circuitry (Internal Transceiver) ..
Page 39 Figure 25.3 CKIO Clock Input Timing .................. 632 Figure 25.4 CKIO Clock Output Timing ................632 Figure 25.5 Power-On Oscillation Settling Time ..............633 Figure 25.6 Oscillation Settling Time at Standby Return (Return by Reset) ......633 Figure 25.7 Oscillation Settling Time at Standby Return (Return by NMI) ......633 Figure 25.8 Oscillation Settling Time at Standby Return (Return by IRQ5 to IRQ0, PINT15 to PINT0, and ) ......
Page 40 Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Bank Active Mode: READ Command, Same Row Address, CAS Latency = 2, TRCD = 1 Cycle) ..............655 Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Bank Active Mode: PRE + ACTV + READ Commands, Different Row Address, CAS Latency = 2, TRCD = 1 Cycle)......
Page 41: Appendix
Appendix Figure B.1 Package Dimensions (FP-208C) ................685 Figure B.2 Package Dimensions (TBP-208A) ................ 686 Rev. 2.00, 09/03, page xli of xlvi...
Page 42 Tables Section 1 Overview Table 1.1 SH7705 Features...................... 2 Table 1.2 Pin Functions ......................9 Table 1.3 Pin Functions ......................17 Section 2 CPU Table 2.1 Logical Address Space ................... 28 Table 2.2 Register Initial Values .................... 30 Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions ......
Page 43 Section 7 Bus State Controller (BSC) Table 7.1 Pin Configuration ....................151 Table 7.2 Physical Address Space Map ................152 Table 7.3 Correspondence between External Pins (MD3 and MD4) and Memory Size ..154 Table 7.4 32-Bit External Device/Big Endian Access and Data Alignment......181 Table 7.5 16-Bit External Device/Big Endian Access and Data Alignment......
Page 44 Table 11.2 Pin Configuration ..................... 295 Section 12 Timer Unit (TMU) Table 12.1 Pin Configuration ..................... 311 Table 12.2 TMU Interrupt Sources..................322 Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.1 TPU Functions ....................330 Table 14.2 Pin Configuration ..................... 332 Table 14.3 TPU Clock Sources ..................
Page 45 Section 23 User Debugging Interface (UDI) Table 23.1 Pin Configuration ..................... 568 Table 23.2 UDI Commands ....................570 Table 23.3 SH7705 Pins and Boundary Scan Register Bits ..........571 Table 23.4 Reset Configuration..................579 Section 25 Electrical Characteristics Table 25.1 Absolute Maximum Ratings ................623 Table 25.2...
Page 46 Appendix Table A.1 I/O Port States in Each Processing State............679 Rev. 2.00, 09/03, page xlvi of xlvi...
Page 47: Section 1 Overview
Section 1 Overview SH7705 Features This LSI is a microprocessor that integrates a 32-bit RISC-type SuperH architecture CPU as its core, together with 32-kbyte cache memory as well as peripheral functions required for system configuration such as an interrupt controller.
Page 48 Table 1.1 SH7705 Features Item Features • Original Renesas SuperH architecture • Compatible with SH-1, SH-2 and SH-3 at object code level • 32-bit internal data bus • General-registers Sixteen 32-bit general registers (eight 32-bit shadow registers) Five 32-bit control registers Four 32-bit system registers •...
Page 49 Item Features • Bus state Physical address space is divided into eight areas: area 0, areas 2 to 4; controller (BSC) each a maximum of 64 Mbytes, and areas 5A, 5B, 6A, 6B; each a maximum of 32 Mbytes • The following features are settable for each area Bus size (8, 16, or 32 bits).
Page 50 Item Features Timer unit (TMU) • Three-channel auto-reload-type 32-bit timer • Input capture function (only channel 2) • Five types of counter input clocks can be selected (Pφ/4, Pφ/16, Pφ/64, Pφ/256, TCLK input) • Compare match 16-bit counter timer (CMT) •...
Page 51 Power-supply voltage Product lineup Power Supply Voltage Product On-chip Operating Name Modules Frequency Product Code Package SH7705 3.3 ± 0.3 V 1.5 ± 0.1 V 133 MHz HD6417705F133 208-pin plastic 100 MHz HD6417705F100 LQFP (FP- 208C) 133 MHz HD6417705BP133 208-pin...
Page 52: Block Diagram
Block Diagram Figure 1.1 shows an internal block diagram of the SH7705. CACHE SCIF0/IrDA SCIF2 INTC DMAC CPG/WDT I/O port External bus (PFC) interface Legend: CACHE: Cache memory TMU: Timer unit CCN: Cache memory controller TPU: 16-bit timer pulse unit...
Page 53: Pin Assignment
RD/WR WE3/DQMUU/AH/PTC2 PTN7 WE2/DQMUL/PTC1 TCLK/PTE6 WE1/DQMLU PTE7 TxD0/SCPT0/IrTX WE0/DQMLL SCK0/SCPT1 TxD2/SCPT2 SCK2/SCPT3 RTS2/SCPT4 BS/PTC0 RxD0/SCPT0/IrRX A25/PTK7 A24/PTK6 RxD2/SCPT2 A23/PTK5 SH7705 A22/PTK4 CTS2/SCPT5 FP-208C A21/PTK3 RESETM (Top view) A20/PTK2 IRQ0/IRL0/PTH0 A19/PTK1 IRQ1/IRL1/PTH1 IRQ2/IRL2/PTH2 IRQ3/IRL3/PTH3 IRQ4/PTH4 IRQ5/PTE2 AUDCK/PTG4 DREQ0/PTH5 DREQ1/PTH6 RESETP AN0/PTL0...
Page 54: Figure 1.3 Pin Assignment (Tbp-208A)
SH7705 TBP-208A (Top view) INDEX MARK Note: The terminal area surrounded by the dotted line is the perspective view. Figure 1.3 Pin Assignment (TBP-208A) Rev. 2.00, 09/03, page 8 of 690...
Page 55: Table 1.2 Pin Functions
Table 1.2 Pin Functions Pin No. TBP- 208C 208A Pin Name Description  VssQ I/O power supply (0 V)  Vcc-USB USB power supply (3.3 V) USB data line USB data line  Vss-USB USB power supply (0 V)  Vcc-RTC * RTC power supply (3.3 V) * XTAL2...
Page 56 Pin No. TBP- 208C 208A Pin Name Description  VssQ I/O power supply (0 V) Data bus  VccQ I/O power supply (3.3 V) Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus ...
Page 57 Pin No. TBP- 208C 208A Pin Name Description Address bus Address bus Address bus Address bus Address bus  VssQ I/O power supply (0 V) Address bus  VccQ I/O power supply (3.3 V) Address bus Address bus Address bus Address bus A19/PTK1 O / I/O...
Page 58 Pin No. TBP- 208C 208A Pin Name Description / PTC3 O / I/O Chip select 2 / input/output port C C S 2 / PTC4 O / I/O Chip select 3 / input/output port C C S 3 / PTC5 O / I/O Chip select 4 / input/output port C C S 4...
Page 59 Pin No. TBP- 208C 208A Pin Name Description AUDATA3/PTF3/TO3 O / I/O / O AUD data output / input/output port F / timer output NF * NF * /PTJ0 /output port J NF * NF * /PTJ1 /output port J NF * NF * /PTJ2...
Page 60 Pin No. TBP- 208C 208A Pin Name Description  Vss-PLL2 PLL2 power supply (0 V)  Vcc-PLL2 PLL2 power supply (1.5 V) Endian setting XTAL Crystal oscillator pin EXTAL External clock / crystal oscillator pin  VssQ I/O power supply (0 V) O / I/O / O STATUS0/PTE4/ Processor status / input/output port E / SCIF0...
Page 61 Pin No. TBP- 208C 208A Pin Name Description  VssQ I/O power supply (0 V) / SCPT5 I / I/O SCIF2 transmit clear / SC port C T S 2  I/O power supply (0 V) Manual reset request R E S E T M ...
Page 62 2. The input level of the pin must be high if the E10A emulator is not used. For A S E M D 0 details, refer to section 23.4.2, Reset Configuration. 3. These pins are initialized to the general input port setting in which the pull-up MOS is off at a power-on reset.
Page 63: Pin Functions
Pin Functions Table 1.3 lists the pin functions. Table 1.3 Pin Functions Classification Symbol Name Function  Power supply Power supply Power supply for the internal modules and ports for the system. Connect all Vcc pins to the system power supply. There will be no operation if any pins are open.
Page 64 Classification Symbol Name Function Operating mode MD6 to MD0 Mode set Sets the operating mode. Do not control change values on these pins during operation. MD2 to MD0 set the clock mode, MD3 and MD4 set the bus-width mode of area 0 and MD5 sets the endian.
Page 65 Classification Symbol Name Function Bus control Chip select 0, Chip-select signal for external C S 0 2 to 4, 5A, 5B, memory or devices. C S 2 C S 4 6A, 6B C S 5 A C S 5 B C S 6 A C S 6 B Read...
Page 66 Classification Symbol Name Function Direct memory DREQ0, DMA-transfer Input pin for external requests for access controller DREQ1 request DMA transfer. (DMAC) DACK0, DMA-transfer Output strobe to external I/O, in DACK1 strobe response to external requests for DMA transfer. TEND0 DMA-transfer Transfer end output for DMAC channel 0.
Page 67 Classification Symbol Name Function EXTAL_USB USB clock USB clock input pin. (48-MHz input) XTAL_USB USB clock USB clock pin. XVDATA Data input Receive data input pin from the differential receiver. VBUS USB power USB-cable connection-monitor pin. supply detection TXDPLS D+ output D+ transmit output pin for the driver.
Page 68 Classification Symbol Name Function I/O port PTA7 to PTA0 General 8-bit general-purpose I/O port pins. purpose port PTB7 to PTB0 8-bit general-purpose I/O port pins. General purpose port PTC7 to PTC0 General 8-bit general-purpose I/O port pins. purpose port PTD7 to PTD0 General 8-bit general-purpose I/O port pins.
Page 69 A S E B R K A K acknowledge has entered its break mode. For the connection with the E10A, see the SH7705 E10A Emulator User’s Manual (tentative title). ASE mode Sets ASE mode. A S E M D 0...
Page 70 Rev. 2.00, 09/03, page 24 of 690...
Page 71: Section 2 Cpu
Section 2 CPU Processing States and Processing Modes 2.1.1 Processing States This LSI supports four types of processing states: a reset state, an exception handling state, a program execution state, and a low-power consumption state, according to the CPU processing states.
Page 72: Processing Modes
2.1.2 Processing Modes This LSI supports two processing modes: user mode and privileged mode. These processing modes can be determined by the processing mode bit (MD) of the status register (SR). If the MD bit is cleared to 0, the user mode is selected. If the MD bit is set to 1, the privileged mode is selected.
Page 73: Memory Map
Memory Map 2.2.1 Logical Address Space The LSI supports 32-bit logical addresses and accesses system resources using the 4-Gbytes of logical address space. User programs and data are accessed from the logical address space. The logical address space is divided into several areas as shown in table 2.1. P0/U0 Area: This area is called the P0 area when the CPU is in privileged mode and the U0 area when in user mode.
Page 74: External Memory Space
Table 2.1 Logical Address Space Address Range Name Mode Description H’00000000 to P0/U0 Privileged/user mode 2-Gbyte physical space, cacheable, address H’7FFFFFFF translatable In user mode, only this address space can be accessed. Privileged mode 0.5-Gbyte physical space, cacheable H’80000000 to H’9FFFFFFF H’A0000000 to Privileged mode...
Page 75: Register Descriptions
External memory space H'0000 0000 H'0000 0000 Area 0 Area 1 Area 2 Area 3 Area 4 P0 area Area 5 U0 area Area 6 Area 7 H'8000 0000 H'8000 0000 P1 area H'A000 0000 P2 area Address error H'C000 0000 P3 area H'E000 0000 P4 area...
Page 76: Table 2.2 Register Initial Values
Table 2.2 shows the register values after reset. Figure 2.3 shows the register configurations in each process mode. Table 2.2 Register Initial Values Register Type Registers Initial Values General registers R0_BANK0 to R7_BANK0, Undefined R0_BANK1 to R7_BANK1, R8 to R15 System registers MACH, MACL, PR Undefined...
Page 77: Figure 2.3 Register Configuration In Each Processing Mode
*1 *2 *1 *3 *1 *4 R0_BANK0 R0_BANK1 R0_BANK0 R1_BANK0 R1_BANK1 R1_BANK0 R2_BANK0 R2_BANK1 R2_BANK0 R3_BANK0 R3_BANK1 R3_BANK0 R4_BANK0 R4_BANK1 R4_BANK0 R5_BANK0 R5_BANK1 R5_BANK0 R6_BANK0 R6_BANK1 R6_BANK0 R7_BANK0 R7_BANK1 R7_BANK0 MACH MACH MACH MACL MACL MACL *1 *4 *1 *3 R0_BANK0 R0_BANK1 R1_BANK0...
Page 78: General Registers
2.3.1 General Registers There are twenty-four 32-bit general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15. R0 to R7 are banked. The process mode and the register bank (RB) bit in the status register (SR) define which set of banked registers (R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1) are accessed as general registers.
Page 79: System Registers
*1 *2 General Registers: Undefined after reset Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. In some instructions, only R0 can be used as the source or destination register. 2.
Page 80: Program Counter
2.3.3 Program Counter The program counter (PC) stores the value obtained by adding 4 to the current instruction address. There is no instruction to read the PC directly. Before an exception handling state is entered, the PC is saved in the save program counter (SPC). Before a subroutine call is executed, the PC is saved in the procedure register (PR).
Page 81: Control Registers
2.3.4 Control Registers The control registers (SR, GBR, SSR, SPC, and VBR) can be accessed by the LDC or STC instruction in privileged mode. The GBR register can be accessed in the user mode. The control registers are described below. Status Register (SR): The status register (SR) indicates the system status as shown below.
Page 82 Initial Bit Name Value Description  M Bit  Q Bit These bits are used by the DIV0S, DIV0U, and DIV1 instructions. These bits can be changed even in user mode by using the DIV0S, DIV0U, and DIV1 instructions. These bits are undefined at reset.
Page 83: Data Formats
Vector Base Register (VBR): The global base register (GBR) can be accessed only in privileged mode. If a transition from reset state to exception handling state occurs, this register is referenced as a base address. For details, refer to section 5, Exception Handling. At reset, the VBR is initialized as H'00000000.
Page 84: Memory Data Formats
2.4.2 Memory Data Formats Memory data formats are classified into byte, word, and longword. Memory can be accessed in byte, word, and longword. When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. An address error will occur if word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed.
Page 85: Figure 2.8 Data Format On Memory (Little Endian Mode)
The little endian mode can also be specified as data format. Either big-endian or little-endian mode can be selected according to the MD5 pin at reset. When MD5 is low at reset, the processor operates in big-endian mode. When MD5 is high at reset, the processor operates in little-endian mode.
Page 86: Features Of Cpu Core Instructions
Features of CPU Core Instructions 2.5.1 Instruction Execution Method Instruction Length: All instructions have a fixed length of 16 bits and are executed in the sequential pipeline. In the sequential pipeline, almost all instructions can be executed in one cycle. All data items are handles in longword (32 bits).
Page 87 Literal Constant: Byte literal constant is placed inside the instruction code as immediate data. Since the instruction length is fixed to 16 bits, word and longword literal constant is not placed inside the instruction code, but in a table in memory. The table in memory is referenced with a MOV instruction using PC-relative addressing mode with displacement.
Page 88: Cpu Instruction Addressing Modes
2.5.2 CPU Instruction Addressing Modes The following table shows addressing modes and effective address calculation methods for instructions executed by the CPU core. Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Effective address is register Rn.
Page 89 Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Indexed @(R0, Rn) Effective address is sum of register Rn and R0 Rn + R0 register indirect contents. Rn + R0 GBR indirect @(disp:8, Effective address is register GBR contents with Byte: GBR + disp GBR) with...
Page 90 Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC + disp × 2 PC-relative disp:8 Effective address is PC with 8-bit displacement disp added after being sign-extended and multiplied by 2. disp PC + disp × 2 (sign-extended) ×...
Page 91: Cpu Instruction Formats
2.5.3 CPU Instruction Formats Table 2.4 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the CPU core. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: Instruction code mmmm: Source register...
Page 92 Source Destination Instruction Format Operand Operand Sample Instruction nm type mmmm: register nnnn: register Rm,Rn direct direct xxxx nnnn xxxx mmmm MOV.L Rm,@Rn mmmm: register nnnn: register indirect indirect mmmm: post- MACH, MACL MAC.W @Rm+,@Rn+ increment register indirect (multiply- and-accumulate operation) nnnn: * post- increment register...
Page 93 Source Destination Instruction Format Operand Operand Sample Instruction d type dddddddd: GBR R0 (register direct) MOV.L @(disp,GBR),R0 indirect with displacement xxxx xxxx dddd dddd R0 (register direct) dddddddd: GBR MOV.L R0,@(disp,GBR) indirect with displacement dddddddd: R0 (register direct) MOVA @(disp,PC),R0 PC-relative with displacement dddddddd:...
Page 94: Instruction Set
Instruction Set 2.6.1 CPU Instruction Set Based on Functions The CPU instruction set consists of 68 basic instruction types divided into six functional groups, as shown in table 2.5. Tables 2.6 to 2.11 show the instruction notation, machine code, execution time, and function.
Page 95 Kinds of Number of Type Instruction Op Code Function Instructions Signed multiplication (16 × 16 bits) Arithmetic MULS operation Unsigned multiplication (16 × 16 bits) MULU instructions Sign inversion NEGC Sign inversion with borrow Binary subtraction SUBC Binary subtraction with carry SUBV Binary subtraction with underflow Logic...
Page 96 Kinds of Number of Type Instruction Op Code Function Instructions Branch Conditional branch, delayed conditional instructions branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch BRAF Unconditional branch Branch to subroutine procedure BSRF Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure...
Page 97 The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using the format shown below. Execution Instruction Instruction Code Operation Privilege T Bit States Indicated in MSB ↔ Indicated by mnemonic.
Page 98: Table 2.6 Data Transfer Instructions
Table 2.6 Data Transfer Instructions Privileged Instruction Instruction Code Operation Mode Cycles T Bit Imm → Sign extension → Rn #imm,Rn – – 1110nnnniiiiiiii MOV.W @(disp,PC),Rn (disp x 2+PC)→Sign extension – – 1001nnnndddddddd → Rn MOV.L @(disp,PC),Rn (disp x 4+PC)→Rn –...
Page 99 Privileged Instruction Instruction Code Operation Mode Cycles T Bit MOV.B @(R0,Rm),Rn (R0+Rm)→Sign extension→Rn – – 0000nnnnmmmm1100 MOV.W @(R0,Rm),Rn (R0+Rm)→Sign extension→Rn – – 0000nnnnmmmm1101 MOV.L @(R0,Rm),Rn (R0+Rm)→Rn – – 0000nnnnmmmm1110 MOV.B R0,@(disp,GBR) R0→(disp+GBR) – – 11000000dddddddd MOV.W R0,@(disp,GBR) R0→(disp x 2+GBR) –...
Page 100: Table 2.7 Arithmetic Operation Instructions
Table 2.7 Arithmetic Operation Instructions Privileged Instruction Instruction Code Operation Mode Cycles T Bit Rm,Rn Rn+Rm→Rn – – 0011nnnnmmmm1100 #imm,Rn Rn+imm→Rn – – 0111nnnniiiiiiii ADDC Rm,Rn Rn+Rm+T→Rn, Carry→T – Carry 0011nnnnmmmm1110 ADDV Rm,Rn Rn+Rm→Rn, Overflow→T – Overflow 0011nnnnmmmm1111 If R0 = imm, 1 → T CMP/EQ #imm,R0 –...
Page 101 Privileged Instruction Instruction Code Operation Mode Cycles T Bit A byte in Rm is sign-extended → EXTS.B Rm,Rn – – 0110nnnnmmmm1110 EXTS.W Rm,Rn A word in Rm is sign-extended – – 0110nnnnmmmm1111 → Rn A byte in Rm is zero-extended → EXTU.B Rm,Rn –...
Page 102: Table 2.8 Logic Operation Instructions
Table 2.8 Logic Operation Instructions Instruction Privileged Instruction Code Operation Mode Cycles T Bit Rn & Rm → Rn Rm,Rn – – 0010nnnnmmmm1001 R0 & imm → R0 #imm,R0 – – 11001001iiiiiiii (R0+GBR) & imm → (R0+GBR) AND.B #imm,@(R0, – –...
Page 103: Table 2.9 Shift Instructions
Table 2.9 Shift Instructions Privileged Instruction Instruction Code Operation Mode Cycles T Bit ROTL T←Rn←MSB – 0100nnnn00000100 ROTR LSB→Rn→T – 0100nnnn00000101 ROTCL T←Rn←T – 0100nnnn00100100 ROTCR T→Rn→T – 0100nnnn00100101 Rn ≥ 0: Rn << Rm → Rn SHAD Rm, Rn –...
Page 104: Table 2.10 Branch Instructions
Table 2.10 Branch Instructions Privileged Instruction Instruction Code Operation Mode Cycles T Bit If T = 0, disp × 2 + PC → PC; 3/1 * disp – – 10001011dddddddd if T = 1, nop 2/1 * BF/S disp Delayed branch, –...
Page 105: Table 2.11 System Control Instructions
Table 2.11 System Control Instructions Privileged Instruction Instruction Code Operation Mode Cycles T Bit CLRM 0→MACH,MACL – – 0000000000101000 CLRS 0→S – – 0000000001001000 CLRT 0→T – 0000000000001000 √ Rm,SR Rm→SR 0100mmmm00001110 Rm,GBR Rm→GBR – – 0100mmmm00011110 √ Rm,VBR Rm→VBR –...
Page 106 Privileged Instruction Instruction Code Operation Mode Cycles T Bit (Rm)→R6_BANK, Rm+4→Rm √ LDC.L @Rm+, – 0100mmmm11100111 R6_BANK (Rm)→R7_BANK, Rm+4→Rm √ LDC.L @Rm+, – 0100mmmm11110111 R7_BANK Rm,MACH Rm→MACH – – 0100mmmm00001010 Rm,MACL Rm→MACL – – 0100mmmm00011010 Rm,PR Rm→PR – – 0100mmmm00101010 LDS.L @Rm+,MACH (Rm)→MACH, Rm+4→Rm...
Page 107 Instruction Privileged Instruction Code Operation Mode Cycles T Bit √ STC.L SSR,@–Rn Rn–4→Rn, SSR→(Rn) – 0100nnnn00110011 √ STC.L SPC,@–Rn Rn–4→Rn, SPC→(Rn) – 0100nnnn01000011 √ STC.L R0_BANK,@–Rn Rn–4→Rn, R0_BANK→(Rn) – 0100nnnn10000011 √ STC.L R1_BANK,@–Rn Rn–4→Rn, R1_BANK→(Rn) – 0100nnnn10010011 √ STC.L R2_BANK,@–Rn Rn–4→Rn, R2_BANK→(Rn) –...
Page 108: Operation Code Map
2.6.2 Operation Code Map Table 2.12 shows the operation code map. Table 2.12 Operation Code Map Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111 LSB MD: 00 MD: 01 MD: 10 MD: 11 0000 Rn 0000 0000 Rn 0001 0000 Rn...
Page 109 Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111 LSB MD: 00 MD: 01 MD: 10 MD: 11 0011 Rn 01MD DIV1 Rm, Rn DMULU.L Rm,Rn CMP/HI Rm, Rn CMP/GT Rm, Rn 0011 Rn 10MD Rm, Rn SUBC Rm, Rn SUBV...
Page 110 Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111 LSB MD: 00 MD: 01 MD: 10 MD: 11 0100 Rn 1100 SHAD Rm, Rn 0100 Rn 1101 SHLD Rm, Rn 0100 Rm 00MD 1110 Rm, SR Rm, GBR LDC Rm, VBR LDC Rm, SSR 0100 Rm...
Page 111: Section 3 Memory Management Unit (Mmu)
Section 3 Memory Management Unit (MMU) This LSI has an on-chip memory management unit (MMU) that supports a virtual memory system. The on-chip translation look-aside buffer (TLB) caches information for user-created address translation tables located in external memory. It enables high-speed translation of virtual addresses into physical addresses.
Page 112: Figure 3.1 Mmu Functions
result in poor efficiency. For this reason, a buffer for address translation (translation look-aside buffer: TLB) is provided in hardware to hold frequently used address translation information. The TLB can be described as a cache for storing address translation information. Unlike cache memory, however, if address translation fails, that is, if an exception is generated, switching of address translation information is normally performed by software.
Page 113: Mmu Of This Lsi
3.1.1 MMU of This LSI Virtual Address Space: This LSI supports a 32-bit virtual address space that enables access to a 4-Gbyte address space. As shown in figures 3.2 and 3.3, the virtual address space is divided into several areas. In privileged mode, a 4-Gbyte space comprising areas P0 to P4 is accessible. In user mode, a 2-Gbyte space of U0 area is accessible.
Page 114: Figure 3.2 Virtual Address Space (Mmucr.at = 1)
H'0000 0000 External address space H'0000 0000 Area 0 Area 1 Area 2 Area 3 Area P0 Area U0 cacheable Area 4 cacheable address translation possible address translation possible Area 5 Area 6 Area 7 H'8000 0000 H'8000 0000 Area P1 cacheable address translation not possible H'A000 0000...
Page 115: Figure 3.3 Virtual Address Space (Mmucr.at = 0)
External address space H'0000 0000 H'0000 0000 Area 0 Area 1 Area 2 Area 3 Area U0 Area P0 Area 4 cacheable cacheable Area 5 Area 6 Area 7 H'8000 0000 H'8000 0000 Area P1 cacheable H'A000 0000 Area P2 non-cacheable Address error H'C000 0000...
Page 116: Figure 3.5 External Memory Space
The area from H'F000 0000 to H'F0FF FFFF is for direct access to the cache address array. For more information, see section 4.4, Memory-Mapped Cache. The area from H'F100 0000 to H'F1FF FFFF is for direct access to the cache data array. For more information, see section 4.4, Memory-Mapped Cache.
Page 117 Address Transition: When the MMU is enabled, the virtual address space is divided into units called pages. Physical addresses are translated in page units. Address translation tables in external memory hold information such as the physical address that corresponds to the virtual address and memory protection codes.
Page 118: Register Descriptions
In single virtual memory mode, the ASID is used to provide memory protection for processes running simultaneously and using the virtual address space exclusively (see section 3.3.3, TLB Address Comparison). Register Descriptions There are four registers for MMU processing. These are all on-chip module control registers, so they are located in address space area P4 and can only be accessed from privileged mode by specifying the address.
Page 119: Page Table Entry Register Low (Ptel)
3.2.2 Page Table Entry Register Low (PTEL) The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to store the physical page number and page management information to be recorded in the TLB by the LDTLB instruction. The contents of this register are only modified in response to a software command.
Page 120 Initial Name Value Description  31 to 9 Reserved These bits are always read as 0. The write value should always be 0.  Single Virtual Memory Mode 0: Multiple virtual memory mode 1: Single virtual memory mode  7, 6 Reserved These bits are always read as 0.
Page 121: Tlb Functions
TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the logical page number and the corresponding physical number, the address space identifier, and the control information for the page, which is the unit of address translation.
Page 122: Figure 3.7 Virtual Address And Tlb Structure
Offset Virtual address (1-kbyte page) Offset Virtual address (4-kbyte page) (15) (19) (1) (1) (1) (1) VPN (31-17) VPN (11-0) ASID V PR SZ TLB entry Legend: VPN: Virtual page number Upper 22 bits of virtual address for a 1-kbyte page, or upper 20 bits of virtual address for a 4-kbyte page.
Page 123: Tlb Indexing
3.3.2 TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 are used as the index number regardless of the page size. The index number can be generated in two different ways depending on the setting of the IX bit in MMUCR.
Page 124: Tlb Address Comparison
Virtual address Index Ways 0 to 3 VPN(31-17) VPN(11-10) ASID(7-0) PPN(28-10) PR(1-0) SZ C D SH Address array Data array Figure 3.9 TLB Indexing (IX = 0) 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB.
Page 125: Figure 3.10 Objects Of Address Comparison
The object compared varies depending on the page management information (SZ, SH) in the TLB entry. It also varies depending on whether the system supports multiple virtual memory or single virtual memory. The page-size information determines whether VPN (11 to 10) is compared. VPN (11 to 10) is compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1).
Page 126: Page Management Information
3.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception.
Page 127: Mmu Functions
MMU Functions 3.4.1 MMU Hardware Management There are two kinds of MMU hardware management as follows. 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR settings. 2.
Page 128: Mmu Instruction (Ldtlb)
3.4.3 MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the index number.
Page 129: Avoiding Synonym Problems
3.4.4 Avoiding Synonym Problems When a 1- or 4-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity.
Page 130: Figure 3.12 Synonym Problem (32-Kbyte Cache)
The above restrictions apply only when performing accesses using the cache. Note: When multiple items of address translation information use the same physical memory to provide for future SuperH RISC engine family expansion, ensure that the VPN bits 20 to 10 are the same.
Page 131: Mmu Exceptions
MMU Exceptions When the address translation unit of the MMU is enabled, occurrence of the MMU exception is checked following the CPU address error check. There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write, and these MMU exceptions are checked in this order.
Page 132: Tlb Protection Violation Exception
2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return from exception handler (RTE) instruction to terminate the handler routine and return to the instruction stream.
Page 133: Tlb Invalid Exception
3.5.3 TLB Invalid Exception A TLB invalid exception results when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception processing includes both hardware and software operations.
Page 134: Initial Page Write Exception
3.5.4 Initial Page Write Exception An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial page write exception processing includes both hardware and software operations.
Page 135: Figure 3.13 Mmu Exception Generation Flowchart
Start Address error? CPU address error SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? VPNs match? VPNs and ASIDs match? V=1? TLB invalid TLB miss exception exception User or User mode Privileged mode privileged? 00/01 01/11 00/10 R/W? R/W? R/W?
Page 136: Memory-Mapped Tlb
Memory-Mapped TLB In order for TLB operations to be managed by software, TLB contents can be read or written to in the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the virtual address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000 to H'F2FFFFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000 to H'F3FFFFFF.
Page 137: Figure 3.14 Specifying Address And Data For Memory-Mapped Tlb Access
(1) TLB address array access • Read access 24 23 17 16 12 1110 9 8 7 * ... . * * ..* 1 1 1 1 0 0 1 0 Address field 17 16...
Page 138: Usage Examples
3.6.3 Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C R1=H'F201 3000 ; MMUCR.IX=0 ; the V bit of way 0 of the entry selected by the VPN(16–12)=B'1 0011 ;...
Page 139: Section 4 Cache
Section 4 Cache Features • Capacity: 16 or 32 kbytes • Structure: Instructions/data mixed, 4-way set associative • Locking: Way 2 and way 3 are lockable • Line size: 16 bytes • Number of entries: 256 entries/way in 16-kbyte mode or 512 entries/way in 32-kbyte mode •...
Page 140: Figure 4.1 Cache Structure (32-Kbyte Mode)
Address array (ways 0−3) Data array (ways 0−3) Entry 0 V U Tag address Entry 1 Entry 511 128 (32 × 4) bits 24 (1 + 1 + 22) bits 6 bits LW0 to LW3: Longword data 0−3 Figure 4.1 Cache Structure (32-kbyte Mode) Address Array: The V bit indicates whether the entry data is valid.
Page 141: Register Descriptions
Table 4.2 LRU and Way Replacement (when Cache Locking Mechanism Is Disabled) LRU (Bits 5 to 0) Way to be Replaced 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 Register Descriptions The cache has the following registers.
Page 142: Cache Control Register 1 (Ccr1)
4.2.1 Cache Control Register 1 (CCR1) The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which invalidates all cache entries), and WT and CB bits (which select either write-through mode or write-back mode).
Page 143: Cache Control Register 2 (Ccr2)
4.2.2 Cache Control Register 2 (CCR2) The CCR2 register controls the cache locking mechanism in cache lock mode only. The CPU enters the cache lock mode when the lock enable bit (bit 16) in the cache control register 2 (CCR2) is set to 1.
Page 144 Initial Name Value Description 31 to 17 — Reserved These bits are always read as 0. The write value should always be 0. Lock Enable (LE) Controls cache lock mode. 0: Does not enter cache lock mode. 1: Enters cache lock mode. 15 to 10 —...
Page 145: Table 4.3 Way Replacement When A Pref Instruction Misses The Cache
Table 4.3 Way Replacement when a PREF Instruction Misses the Cache DSP Bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced Determined by LRU (table 4.2) Determined by LRU (table 4.2) Determined by LRU (table 4.5) Determined by LRU (table 4.6) Determined by LRU (table 4.7) Way 2 Way 3...
Page 146: Cache Control Register 3 (Ccr3)
Table 4.7 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1) LRU (Bits 5 to 0) Way to be Replaced 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 4.2.3 Cache Control Register 3 (CCR3)
Page 147: Operation
Operation 4.3.1 Searching the Cache If the cache is enabled (the CE bit in CCR1 = 1), whenever instructions or data in spaces P0, P1, P3, and U0 are accessed the cache will be searched to see if the desired instruction or data is in the cache.
Page 148: Read Access
4.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The LRU i updated to indicate that the hit way is the most recently hit way. Read Miss: An external bus cycle starts and the entry is updated. The way to be replaced is shown in table 4.3.
Page 149: Write-Back Buffer
4.3.5 Write-Back Buffer When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory.
Page 150: Memory-Mapped Cache
Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions in privileged mode. The cache is mapped onto the P4 area in virtual address space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data array onto addresses H'F1000000 to H'F1FFFFFF.
Page 151: Data Array
address and LRU bits remain unchanged. When there is no way that receives a hit, nothing is written and there is no operation. This operation is used to invalidate the address specification for a cache. When the U bit of the entry that has received a hit is 1 at this point, writing back should be performed.
Page 152: Figure 4.4 Specifying Address And Data For Memory-Mapped Cache Access (32-Kbyte Mode)
(1) Address array access (a) Address specification Read access 1111 0000 *--------* Entry address Write access 1111 0000 Entry address *--------* (b) Data specification (both read and write accesses) Tag address (31 to 10) (2) Data array access (both read and write accesses) (a) Address specification 1111 0001 Entry address...
Page 153: Usage Examples
4.4.3 Usage Examples Invalidating a Specific Entry: A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0 to the entry’s U and V bits. The A bit is cleared to 0, and an address is specified for the entry address and the way. If the U bit of the way of the entry in question was set to 1, the entry is written back and the V and U bits specified by the write data are written to.
Page 154: Usage Note
Invalidating an Address Specification: An address specification can be invalidated by accessing the memory allocation cache and writing a 0 to the entry’s V bit. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address.
Page 155: Section 5 Exception Handling
Section 5 Exception Handling Exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. For example, if an attempt is made to execute an undefined instruction code or an instruction protected by the CPU processing mode, a control function may be required to return to the source program by executing the appropriate operation or to report an abnormality and carry out end processing.
Page 156: Trapa Exception Register (Tra)
Figure 5.1 shows the bit configuration of each register. 10 9 2 1 0 12 11 EXPEVT EXPEVT 12 11 INTEVT INTEVT 12 11 INTEVT2 INTEVT2 Figure 5.1 Register Bit Configuration 5.1.1 TRAPA Exception Register (TRA) TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the TRAPA instruction.
Page 157: Exception Event Register (Expevt)
5.1.2 Exception Event Register (EXPEVT) EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception codes to be specified in EXPEVT are those for resets and general exceptions. These exception codes are automatically specified the hardware when an exception occurs. Only bits 11 to 0 of EXPEVT can be re-written using the software.
Page 158: Interrupt Event Register 2 (Intevt2)
5.1.4 Interrupt Event Register 2 (INTEVT2) INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified using the software.
Page 159: Exception Handling Function
Exception Handling Function 5.2.1 Exception Handling Flow In exception handling, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the exception handler is invoked from a vector address. The return from exception handler (RTE) instruction is issued by the exception handler routine on completion of the routine, restoring the contents of PC and SR to return to the processor state at the point of interruption and the address where the exception occurred.
Page 160: Exception Vector Addresses
The above operations from 1 to 3 are executed in sequence. During these operations, no other exceptions may be accepted. By changing the SPT and SSR before executing the RTE instruction, a status different from that in effect before the exception handling can also be specified. Notes: 1.
Page 161: Exception Source Acceptance Timing And Priority
To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to 0. Before restoring the SPC and SSR, the BL bit must be set to 1. 5.2.5 Exception Source Acceptance Timing and Priority Exception Request of Instruction Synchronous Type and Instruction Asynchronous Type:...
Page 162: Table 5.1 Exception Event Vectors
4. An exception caused by an instruction decode (General illegal instruction exceptions and slot illegal instruction exceptions: re-execution type, unconditional trap: processing-completion type) 5. An exception related to data access (CPU address error and MMU related exceptions: re- execution type) 6.
Page 163 Exception Current Exception Process Vector Vector Priority * Type Instruction Exception Event Order at BL=1 Code Offset TLB invalid * General Re-executed (data access) Reset H'040/ H'00000100 exception H'060 events TLB protection violation * Reset H'0A0/ H'00000100 (data access) H'0C0 Initial page write * Reset H'080...
Page 164: Individual Exception Operations
Individual Exception Operations This section describes the conditions for specific exception handling and the processor operations for resets and general exceptions. For interrupts, refer to section 6, Interrupt Controller (INTC). 5.3.1 Resets Power-On Reset: • Conditions Power-on reset is request •...
Page 165 • Exception code An exception occurred during read: H'0E0 An exception occurred during write: H'1E0 • Remarks The logical address (32 bits) that caused the exception is set in TEA. Illegal General Instruction Exception: • Conditions  When undefined code not in a delay slot is decoded Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Note: For details on undefined code, refer to section 2.6.2, Operation Code Map.
Page 166 • Save address A delayed branch instruction address • Exception code H'1A0 • Remarks None Unconditional Trap: • Conditions TRAPA instruction executed • Types Instruction synchronous, processing-completion type • Save address An address of an instruction following TRAPA • Exception code H'160 •...
Page 167: General Exceptions (Mmu Exceptions)
• Remarks For details on user break controller, refer to section 22, User Break Controller (UBC). DMA Address Error: • Conditions  Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)  Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + •...
Page 168 • Save address Instruction fetch: An instruction address to be fetched when an exception occurred Data access: An instruction address where an exception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) • Exception code An exception occurred during read: H'040 An exception occurred during write: H'060 •...
Page 169 • Exception code An exception occurred during read: H'0A0 An exception occurred during write: H'0C0 • Remarks The logical address (32 bits) that caused the exception is set in TEA and the MMU registers are updated. Initial Page Write Exception: •...
Page 170: Usage Notes
Usage Notes 1. An instruction assigned at a delay slot of the RTE instruction is executed after the contents of the SSR is restored into the SR. An acceptance of an exception related to instruction access is determined according to the SR before restore. An acceptance of other exceptions is determined by the SR after restore, processing mode, and BL bit value.
Page 171: Section 6 Interrupt Controller (Intc)
Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. Features •...
Page 172: Figure 6.1 Block Diagram Of Intc
Figure 6.1 shows a block diagram of the INTC. Input/output IRQ5−IRQ0 control PINT15−PINT0 Interrupt (Interrupt request) Com- DMAC request parator SCIF Priority identifier I3 I2 I1 I0 PINTER interface INTC Legend: DMAC : Direct memory access controller : Watchdog timer SCIF : Serial communication interface (with FIFO) : User debugging interface...
Page 173: Input/Output Pins
Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbreviation Description Nonmaskable interrupt input pin Input Input of interrupt request signal, not maskable by the interrupt mask bits in SR Interrupt input pins IRQ5 to IRQ0, Input Input of interrupt request signals I R L 3...
Page 174: Interrupt Priority Level Setting Registers A To H (Ipra To Iprh)
6.3.1 Interrupt Priority Level Setting Registers A to H (IPRA to IPRH) IPRA to IPRH are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module, and IRQ and PINT interrupts. Bit Name Initial Value Description 15 to 0...
Page 175: Interrupt Control Register 0 (Icr0)
6.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a register that sets the input signal detection mode of external interrupt input pin NMI, and indicates the input signal level at the NMI pin. Bit Name Initial Value Description 0/1 * NMIL NMI Input Level Sets the level of the signal input at the NMI pin.
Page 176: Interrupt Control Register 1 (Icr1)
6.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to IRQ5 individually: rising edge, falling edge, high level, or low level. Bit Name Initial Value Description Mask All Interrupts When set to 1, masks all interrupt requests when a low level is being input to the NMI pin.
Page 177 Bit Name Initial Value Description 11 to 0 IRQ51S to IRQn Sense Select IRQ00S Select whether the interrupt signals to the IRQ5 to IRQ0 pins are detected at the falling edge, at the rising edge, at low level, or at high level. Bit 2n+1 Bit 2n IRQn1S IRQn0S An interrupt request is...
Page 178: Interrupt Control Register 2 (Icr2)
6.3.4 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT15 to PINT0. Bit Name Initial Value Description 15 to 0 PINT15S to PINT15 to PINT0 Sense Select PINT0S Select whether interrupt request signals to PINT15 to PINT0 are detected at low levels or high levels.
Page 179: Interrupt Request Register 0 (Irr0)
6.3.6 Interrupt Request Register 0 (IRR0) IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5 and PINT0 to PINT15. Bit Name Initial Value Description PINT0R PINT0 to PINT7 Interrupt Request Indicates whether interrupt requests are input to PINT0 to PINT7 pins.
Page 180: Interrupt Request Register 1 (Irr1)
6.3.7 Interrupt Request Register 1 (IRR1) IRR1 is an 8-bit register that indicates whether DMAC or SCIF0 interrupt requests are generated. Initial Name Value Description TXI0R TXI0 Interrupt Request Indicates whether a TXI0 (SCIF0) interrupt request is generated. 0: A TXI0 interrupt request is not generated 1: A TXI0 interrupt request is generated ...
Page 181: Interrupt Request Register 2 (Irr2)
Initial Name Value Description DEI0R DEI0 Interrupt Request Indicates whether a DEI0 (DMAC) interrupt request is generated. 0: A DEI0 interrupt request is not generated 1: A DEI0 interrupt request is generated 6.3.8 Interrupt Request Register 2 (IRR2) IRR2 is an 8-bit register that indicates whether SCIF2 or ADC interrupt requests are generated. Initial Name Value...
Page 182: Interrupt Sources
Interrupt Sources There are five types of interrupt sources: NMI, IRQ, IRL, PINT, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks an interrupt, so the interrupt request is ignored. 6.4.1 NMI Interrupt The NMI interrupt has the highest priority level of 16.
Page 183: Irl Interrupts
6.4.3 IRL Interrupts IRL interrupts are input by level at pins . The priority level is the higher of those I R L 3 I R L 0 indicated by pins . An value of 0 (0000) indicates the highest-level I R L 3 I R L 0 I R L 3...
Page 184: Pint Interrupt
Table 6.3 Pins and Interrupt Levels I R L 3 I R L 0 Interrupt Priority Level Interrupt Request I R L 3 I R L 2 I R L 1 I R L 0 Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request...
Page 185: Interrupt Exception Handling And Priority
• USB interface (USB) • Timer unit (TMU) • 16-bit timer pulse unit (TPU) • Watchdog timer (WDT) • Bus state controller (BSC) • User-debugging interface (UDI) • Realtime clock (RTC) Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the interrupt event registers (INTEVT and INTEVT2).
Page 186: Table 6.4 Interrupt Exception Handling Sources And Priority (Irq Mode)
Table 6.4 Interrupt Exception Handling Sources and Priority (IRQ Mode) Interrupt Priority Priority within IPR Default Interrupt Code * Interrupt Source (Initial Value) (Bit Numbers) Setting Unit Priority   H'1C0 * High   H'5E0 *  H'600 * IRQ0 0 to 15 (0) IPRC (3 to 0)
Page 187 Interrupt Priority Priority within IPR Default Interrupt Code * Interrupt Source (Initial Value) (Bit Numbers) Setting Unit Priority H'400 * TMU0 TUNI0 0 to 15 (0) IPRA (15 to 12) — High H'420 * TMU1 TUNI1 0 to 15 (0) IPRA (11 to 8) —...
Page 188 Table 6.5 Interrupt Exception Handling Sources and Priority (IRL Mode) Interrupt Priority Priority IPR (Bit within IPR Default Interrupt Code * Interrupt Source (Initial Value) Numbers) Setting Unit Priority H'1C0 * — — High H'5E0 * — — ( 3:0) = 0000 H'200 * —...
Page 189 Interrupt Priority Priority IPR (Bit within IPR Default Interrupt Code * Interrupt Source (Initial Value) Numbers) Setting Unit Priority H'900 * SCIF2 ERI2 0 to 15 (0) IPRE (7 to 4) High High H'920 * RXI2 H'960 * TXI2 H'980 * 0 to 15 (0) IPRE (3 to 0) —...
Page 190: Operation
Table 6.6 Interrupt Level and INTEVT Code Interrupt level INTEVT Code H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 Operation 6.5.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 6.3 is a flowchart of the operations.
Page 191 5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2). 6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8.
Page 192: Figure 6.3 Interrupt Operation Flowchart
Program execution state ICR1.MAI = 1? NMI = low? Interrupt generated? ICR1.BLMSK = 1? SR.BL=0 or sleep mode or software standby mode? NMI? NMI? Level 15 interrupt? Level 14 interrupt? I3-I0 level Level 1 14 or lower? interrupt? Set interrupt source in I3-I0 level INTEVT and INTEVT2 13 or lower?
Page 193: Multiple Interrupts
6.5.2 Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT or INTEVT2. The code in INTEVT or INTEVT2 can be used as an offset for branching to the specific handler.
Page 194 Rev. 2.00, 09/03, page 148 of 690...
Page 195: Section 7 Bus State Controller (Bsc)
Section 7 Bus State Controller (BSC) Overview The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices. 7.1.1 Features The BSC has the following features:...
Page 196: Block Diagram
• Bus arbitration  Shares all of the resources with other CPU and outputs the bus enable after receiving the bus request from external devices. 7.1.2 Block Diagram BSC functional block diagram is shown in figure 7.1. Internal Internal address bus data bus Output CMNCR...
Page 197: Pin Configuration
Pin Configuration Table 7.1 Pin Configuration Name Function A25 to A0 Address bus D31 to D0 Data bus Bus cycle start Asserted when a normal space, byte-selection SRAM, burst ROM, or address/data multiplex I/O is accessed. Asserted by the same timing in SDRAM access.
Page 198: Area Overview
Name Function Connects to CKE pin when SDRAM is connected. Holds the address in address/data multiplex I/O mode. External wait input W A I T Bus request input B R E Q Bus acknowledge output B A C K MD3, MD4 Area 0 bus width (8/16/32 bits) Specifies endian 0: Big endian...
Page 199 Memory to be Access Area Connected Physical Address Capacity Size Area 1 Internal I/O register * H'04000000 to H'07FFFFFF H'04000000 to H'07FFFFFF (n:1 to 6) +H'20000000×n +H'20000000×n Area 2 H'08000000 to H'0BFFFFFF 64 Mbytes 8, 16, 32 * Normal memory * Synchronous DRAM H'08000000 to H'0BFFFFFF...
Page 200: Memory Bus Width
H'00000000 Area 0 (CS0) H'00000000 Internal I/O H'04000000 H'20000000 H'08000000 Area 2 (CS2) Area 3 (CS3) H'0C000000 H'40000000 H'10000000 Area 4 (CS4) H'14000000 Area 5A (CS5A) H'16000000 H'60000000 Area 5B (CS5B) H'18000000 Area 6A (CS6A) H'1A000000 H'80000000 Area 6B (CS6B) H'1BFFFFFF Reserved area H'A0000000...
Page 201: Shadow Space
When port A or B is used, set the bus width of all areas to 8-bit or 16-bit. For details see section 7.4.2, CSn Space Bus Control Register (CSnBCR). 7.3.3 Shadow Space Areas 0, 2 to 4, 5A, 5B, 6A, and 6B are decoded by physical addresses A28 to A26, which correspond to areas 000 to 110.
Page 202: Common Control Register (Cmncr)
• Wait control register for CS6B space (CS6BWCR) • SDRAM control register (SDCR) • Refresh timer control/status register (RTCSR) * • Refresh timer counter (RTCNT) * • Refresh time constant register (RTCOR) * • SDRAM mode register for CS2 space (SDMR2) * •...
Page 203 Initial Name Value Description DMAIWA 0 Method of inserting wait states between access cycles when DMA single address transfer is performed. Specifies the method of inserting the idle cycles specified by the DMAIW1 and DMAIW0 bits. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it.
Page 204: Csn Space Bus Control Register (Csnbcr) (N = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B) CSnBCR is a 32-bit readable/writable register that specifies the function of each area, the number of idle cycles between bus cycles, and the bus-width. Do not access external memory other than area 0 until CSnBCR register initialization is completed.
Page 205 Initial Name Value Description  Reserved This bit is always read as 0. The write value should always be IWRWS1 Idle Cycles for Read-write in the Same Space IWRWS0 Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space.
Page 206 Initial Name Value Description  Reserved This bit is always read as 0. The write value should always be TYPE2 Memory Type TYPE1 Specify the type of memory connected to a space. TYPE0 000: Normal space 001: Burst ROM 010: Address/data multiplex I/O (MPX) 011: Byte-selection SRAM 100: SDRAM 101: Setting prohibited...
Page 207 Initial Name Value Description  8 to 0 Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. When the CS5B space is specified as address/data multiplex I/O (MPX), specify the bus size to 16 bits. 2.
Page 208 1. Normal Space, Byte-Selection SRAM, Address/Data Multiplex I/O (MPX) CS0WCR, CS6AWCR, CS6BWCR Initial Bit Name Value Description 31 to 13  Reserved These bits are always read as 0. The write value should always be 0. Number of Delay Cycles from Address, Assertion to C S n Assertion...
Page 209 Initial Bit Name Value Description External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored ...
Page 210 CS2WCR, CS3WCR Initial Name Value Description 31 to 11  Reserved These bits are always read as 0. The write value should always be 0. Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access.
Page 211 CS4WCR, CS5AWCR Initial Name Value Description 31 to 19  Reserved These bits are always read as 0. The write value should always be 0. Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access.
Page 212 Initial Name Value Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles...
Page 213 CS5BWCR Initial Name Value Description 31 to 21  Reserved These bits are always read as 0. The write value should always be 0. MPXW MPX Interface Address Wait Specifies the wait to be inserted between address cycles for address/data multiplex I/O. This specification is valid only when area 5B is specified to address/data multiplex I/O.
Page 214 Initial Name Value Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles...
Page 215 2. Burst ROM CS0WCR Initial Name Value Description 31 to 18  Reserved These bits are always read as 0. The write value should always be 0. Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or later access cycles in burst access.
Page 216 Initial Name Value Description External Wait Mask Specification Specify whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait is valid 1: External wait is ignored ...
Page 217 Initial Name Value Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first read/write access cycle. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles...
Page 218 3. SDRAM* CS2WCR Initial Name Value Description 31 to 11  Reserved These bits are always read as 0. The write value should always be 0.  Reserved This bit is always read as 1. The write value should always be ...
Page 219 CS3WCR Initial Name Value Description 31 to 15  Reserved These bits are always read as 0. The write value should always be 0. TRP1 Number of Cycles from Auto-precharge/PRE Command to ACTV Command TRP0 Specify the number of minimum cycles from the start of auto- precharge or issuing of PRE command to the issuing of ACTV command for the same bank.
Page 220: Sdram Control Register (Sdcr)
Initial Name Value Description  6, 5 Reserved These bits are always read as 0. The write value should always be 0. TRWL1 Number of Cycles from WRITA/WRIT Command to Auto- precharge/PRE Command TRWL0 Specifies the number of cycles from issuing WRITA/WRIT command to the start of auto-precharge or to issuing PRE command.
Page 221 Initial Name Value Description 31 to 21  Reserved These bits are always read as 0. The write value should always be 0. A2ROW1 Number of Bits of Row Address for Area 2 A2ROW0 Specifies the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits...
Page 222 Initial Name Value Description RFSH Refresh Control Specifies whether or not the refresh operation of the SDRAM is performed. 0: No refresh 1: Refresh RMODE 0 Refresh Control Specifies whether to perform auto-refresh or self-refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately.
Page 223: Refresh Timer Control/Status Register (Rtcsr)
Initial Name Value Description  Reserved This bit is always read as 0. The write value should always be A3COL1 Number of Bits of Column Address for Area 3 A3COL0 Specifies the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits...
Page 224 Initial Name Value Description CKS2 Clock Select CKS1 Select the clock input to count-up the refresh timer counter (RTCNT). CKS0 000: Stop the counting-up 001: Bφ/4 010: Bφ/16 011: Bφ/64 100: Bφ/256 101: Bφ/1024 110: Bφ/2048 111: Bφ/4096 RRC2 Refresh Count RRC1 Specify the number of continuous refresh cycles, when the refresh request occurs after the coincidence of the values of...
Page 225: Refresh Timer Counter (Rtcnt)
7.4.6 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter that counts up using the clock selected by bits CKS2 to CKS0 in RTCSR. This register only accepts 32-bit writing to prevent incorrect writing. In this case, the upper 16 bits of the data must be H'A55A, otherwise writing cannot be performed.
Page 226: Reset Wait Counter (Rwtcnt)
Initial Name Value Description 31 to 8  Reserved These bits are always read as 0. The write value should always be 0.  7 to 0 Maximum Counter Value (eight bits) 7.4.8 Reset Wait Counter (RWTCNT) RWTCNT is a 16-bit register. The lower seven bits of this register (bits 6 to 0) are valid as a counter and the upper nine bits (bits 15 to 7) are reserved.
Page 227: Table 7.4 32-Bit External Device/Big Endian Access And Data Alignment
Table 7.4 32-Bit External Device/Big Endian Access and Data Alignment Data Bus Strobe Signals D7 to D0 D31 to D23 to D15 to W E 3 W E 2 W E 1 W E 0 Operation DQMUU DQMUL DQMLU DQMLL ...
Page 228: Table 7.5 16-Bit External Device/Big Endian Access And Data Alignment
Table 7.5 16-Bit External Device/Big Endian Access and Data Alignment Data Bus Strobe Signals D7 to D0 D31 to D23 to D15 to W E 3 W E 2 W E 1 W E 0 Operation DQMUU DQMUL DQMLU DQMLL ...
Page 229: Table 7.6 8-Bit External Device/Big Endian Access And Data Alignment
Table 7.6 8-Bit External Device/Big Endian Access and Data Alignment Data Bus Strobe Signals D7 to D0 D31 to D23 to D15 to W E 3 W E 2 W E 1 W E 0 Operation DQMUU DQMUL DQMLU DQMLL ...
Page 230: Table 7.7 32-Bit External Device/Little Endian Access And Data Alignment
Table 7.7 32-Bit External Device/Little Endian Access and Data Alignment Data Bus Strobe Signals D7 to D0 D31 to D23 to D15 to W E 3 W E 2 W E 1 W E 0 Operation DQMUU DQMUL DQMLU DQMLL ...
Page 231: Table 7.8 16-Bit External Device/Little Endian Access And Data Alignment
Table 7.8 16-Bit External Device/Little Endian Access and Data Alignment Data Bus Strobe Signals D7 to D0 D31 to D23 to D15 to W E 3 W E 2 W E 1 W E 0 Operation DQMUU DQMUL DQMLU DQMLL ...
Page 232: Table 7.9 8-Bit External Device/Little Endian Access And Data Alignment
Table 7.9 8-Bit External Device/Little Endian Access and Data Alignment Data Bus Strobe Signals D7 to D0 D31 to D23 to D15 to W E 3 W E 2 W E 1 W E 0 Operation DQMUU DQMUL DQMLU DQMLL ...
Page 233: Normal Space Interface
Normal Space Interface 7.6.1 Basic Timing For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see section 7.10, Byte-Selection SRAM Interface. Figures 7.3 and 7.4 show the basic timings of normal space accesses.
Page 234: Figure 7.3 Continuous Access For Normal Space (No Wait, Wm Bit In Csnwcr = 1, 16-Bit Bus Width, Longword Access, No Wait State Between Cycles)
CKIO A25 to A0 RD/WR Read Data Write Data DACK Figure 7.3 Continuous Access for Normal Space (No Wait, WM Bit in CSnWCR = 1, 16-Bit Bus Width, Longword Access, No Wait State between Cycles) Rev. 2.00, 09/03, page 188 of 690...
Page 235: Figure 7.4 Continuous Access For Normal Space (No Wait, One Wait State Between Cycles)
CKIO A25 to A0 Read Data Write Data DACKn WAIT Figure 7.4 Continuous Access for Normal Space (No Wait, One Wait State between Cycles) Rev. 2.00, 09/03, page 189 of 690...
Page 236: Figure 7.5 Example Of 32-Bit Data-Width Sram Connection
Figures 7.5 to 7.7 show examples of connection to 32-bit, 16-bit, and 8-bit data-width SRAM, respectively. 128k × 8-bit This LSI SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 7.5 Example of 32-Bit Data-Width SRAM Connection Rev. 2.00, 09/03, page 190 of 690...
Page 237: Figure 7.6 Example Of 16-Bit Data-Width Sram Connection
128k × 8-bit This LSI SRAM I/O7 I/O0 I/O7 I/O0 Figure 7.6 Example of 16-Bit Data-Width SRAM Connection 128k × 8-bit This LSI SRAM I/O7 I/O0 Figure 7.7 Example of 8-Bit Data-Width SRAM Connection Rev. 2.00, 09/03, page 191 of 690...
Page 238: Access Wait Control
7.6.2 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in read access and in write access.
Page 239: Figure 7.9 Wait State Timing For Normal Space Access (Wait State Insertion By W A I T Signal)
When the WM bit in CSnWCR is cleared to 0, the external wait input signal is also W A I T sampled. pin sampling is shown in figure 7.9. A 2-cycle wait is specified as a software W A I T wait.
Page 240: C S N Assert Period Expansion
7.6.3 C S n Assert Period Expansion The number of cycles from assertion to assertion can be specified by setting bits C S n W E n SW1 and SW0 in CSnWCR. The number of cycles from negation to negation can W E n C S n be specified by setting bits HW1 and HW0.
Page 241: Address/Data Multiplex I/O Interface
Address/Data Multiplex I/O Interface The address/data multiplex (MPX) I/O interface can be selected by setting bits TYPE2 to TYPE0 to 010 in CS5BBCR. Do not set this value to the bits in CSnBCR other than those in area 5B, otherwise the operation of the LSI is not guaranteed. Access timing for the MPX space is shown below.
Page 242: Figure 7.12 Access Timing For Mpx Space (Address Cycle Wait 1, Data Cycle No Wait)
Tadw CKIO A25 to A16 CS5B RD/WR Read D15 to D0 Address Data Write Address Data D15 to D0 DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 7.12 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait) Rev.
Page 243: Figure 7.13 Access Timing For Mpx Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)
Tadw CKIO A25 to A16 CS5B RD/WR Read D15 to D0 Address Data Write Address Data D15 to D0 WAIT DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 7.13 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1) Rev.
Page 244: Sdram Interface
SDRAM Interface 7.8.1 SDRAM Direct Connection Since synchronous DRAM can be selected by the signal, physical space areas 2 and 3 can be connected using and other control signals in common. If the TYPE[2:0] bits in CSnBCR (n = R A S 2 or 3) are set to 100, the synchronous DRAM interface can be selected.
Page 245: Figure 7.14 Example Of 64-Mbit Synchronous Dram Connection (32-Bit Data Bus)
64M synchronous DRAM (1M × 16-bit × 4-bank) This LSI CKIO RASx CASx RD/WR DQ15 DQMU DQMUU DQML DQMUL DQMLU DQMLL DQ15 DQMU DQML Note: x is U or L Figure 7.14 Example of 64-MBit Synchronous DRAM Connection (32-Bit Data Bus) Rev.
Page 246: Address Multiplexing
64M synchronous DRAM (1M × 16-bit × 4-bank) This LSI CKIO RASx CASx RD/WR DQ15 DQMLU DQMU DQMLL DQML Note: x is U or L Figure 7.15 Example of 64-MBit Synchronous DRAM (16-Bit Data Bus) 7.8.2 Address Multiplexing An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, AxROW[1:0] and AxCOL[1:0] in SDCR.
Page 247: Table 7.10 Relationship Between A2/3Bsz[1:0], A2/3Row[1:0], And Address Multiplex Output (1)-1
Table 7.10 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (1)-1 Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 248 Table 7.10 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (1)-2 Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 11 (32 bits) 01 (12 bits) 00 (8 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 249: Table 7.11 Relationship Between A2/3Bsz[1:0], A2/3Row[1:0], And Address Multiplex Output (2)-1
Table 7.11 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (2)-1 Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 11 (32 bits) 01 (12 bits) 01 (9 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 250 Table 7.11 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (2)-2 Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 11 (32 bits) 01 (12 bits) 10 (10 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 251: Table 7.12 Relationship Between A2/3Bsz[1:0], A2/3Row[1:0], And Address Multiplex Output (3)
Table 7.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (3) Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 11 (32 bits) 10 (13 bits) 01 (9 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 252: Table 7.13 Relationship Between A2/3Bsz[1:0], A2/3Row[1:0], And Address Multiplex Output (4)-1
Table 7.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (4)-1 Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 10 (16 bits) 00 (11 bits) 00 (8 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 253 Table 7.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (4)-2 Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 10 (16 bits) 01 (12 bits) 00 (8 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 254: Table 7.14 Relationship Between A2/3Bsz[1:0], A2/3Row[1:0], And Address Multiplex Output (5)-1
Table 7.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (5)-1 Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 255 Table 7.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (5)-2 Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 10 (16 bits) 01 (12 bits) 10 (10 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 256: Table 7.15 Relationship Between A2/3Bsz[1:0], A2/3Row[1:0], And Address Multiplex Output (6)-1
Table 7.15 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (6)-1 Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 257 Table 7.15 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], and Address Multiplex Output (6)-2 Setting A2/3 BSZ[1:0] A2/3 ROW[1:0] A2/3 COL[1:0] 10 (16 bits) 10 (13 bits) 10 (10 bits) Output Pin of Row Address Column Address Synchronous DRAM This LSI Output Cycle Output Cycle Function Unused...
Page 258: Burst Read
7.8.3 Burst Read A burst read occurs in the following cases in this LSI. • 16-byte transfer in cache miss. • 16-byte transfer in DMAC (access to non-cacheable region) • Access size in reading is larger than data bus width. This LSI always accesses the SDRAM with burst length 1.
Page 259: Figure 7.16 Synchronous Dram Burst Read Wait Specification Timing (Auto Precharge)
Figure 7.16 shows a timing chart in burst read. In burst read, an ACTV command is output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external clock (CKIO) in the Td1 to Td4 cycles.
Page 260: Single Read
7.8.4 Single Read A read access ends in one cycle when data exists in non-cacheable region and the data bus width is larger than or equal to access size. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output.
Page 261: Burst Write
7.8.5 Burst Write A burst write occurs in the following cases in this LSI. • Copyback of the cache • 16-byte transfer in DMAC (access to non-cacheable region) • Access size in writing is larger than data bus width. This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is connected to a 32-bit data bus.
Page 262: Figure 7.18 Basic Timing For Synchronous Dram Burst Write (Auto Precharge)
Figure 7.18 shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output simultaneously with the write command.
Page 263: Single Write
7.8.6 Single Write A write access ends in one cycle when data is written in non-cacheable region and the data bus width is larger than or equal to access size. This is called single write. Figure 7.19 shows the basic timing chart for single write.
Page 264: Bank Active
7.8.7 Bank Active The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the BACTV bit in SDCR is 1, accesses are performed using commands (READ, WRIT) without auto-precharge. This function is called bank-active function. This function is valid only for either the upper or lower bits of area 3.
Page 265: Figure 7.20 Burst Read Timing (No Auto Precharge)
CKIO A25 to A0 A12/A11 * RASU/L CASU/L RD/WR DQMxx * D31 to D0 DACKn * Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. xx is UU, UL, LU, or LL. 3. The waveform for DACKn is when active low is specified. Figure 7.20 Burst Read Timing (No Auto Precharge) Rev.
Page 266: Figure 7.21 Burst Read Timing (Bank Active, Same Row Address)
CKIO A25 to A0 A12/A11 * RASU/L CASU/L RD/WR DQMxx * D31 to D0 DACKn * Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. xx is UU, UL, LU, or LL. 3. The waveform for DACKn is when active low is specified. Figure 7.21 Burst Read Timing (Bank Active, Same Row Address) Rev.
Page 267: Figure 7.22 Burst Read Timing (Bank Active, Different Row Addresses)
CKIO A25 to A0 A12/A11 * RASU/L CASU/L RD/WR DQMxx * D31 to D0 DACKn * Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. xx is UU, UL, LU, or LL. 3. The waveform for DACKn is when active low is specified. Figure 7.22 Burst Read Timing (Bank Active, Different Row Addresses) Rev.
Page 268: Figure 7.23 Single Write Timing (No Auto Precharge)
CKIO A25 to A0 A12/A11 * RASU/L CASU/L RD/WR DQMxx * D31 to D0 DACKn * Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. xx is UU, UL, LU, or LL. 3. The waveform for DACKn is when active low is specified. Figure 7.23 Single Write Timing (No Auto Precharge) Rev.
Page 269: Figure 7.24 Single Write Timing (Bank Active, Same Row Address)
Tnop CKIO A25 to A0 A12/A11 * RASU/L CASU/L RD/WR DQMxx * D31 to D0 DACKn * Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. xx is UU, UL, LU, or LL. 3. The waveform for DACKn is when active low is specified. Figure 7.24 Single Write Timing (Bank Active, Same Row Address) Rev.
Page 270: Figure 7.25 Single Write Timing (Bank Active, Different Row Addresses)
CKIO A25 to A0 A12/A11 * RASU/L CASU/L RD/WR DQMxx * D31 to D0 DACKn * Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. xx is UU, UL, LU, or LL. 3. The waveform for DACKn is when active low is specified. Figure 7.25 Single Write Timing (Bank Active, Different Row Addresses) Rev.
Page 271: Refreshing
7.8.8 Refreshing This LSI has a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC[2:0] bits in RTCSR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1.
Page 272: Figure 7.26 Auto-Refresh Timing
CKIO A25 to A0 A12/A11 * RASU/L CASU/L RD/WR DQMxx * D31 to D0 Hi-Z DACKn * Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. xx is UU, UL, LU, or LL. 3. The waveform for DACKn is when active low is specified. Figure 7.26 Auto-Refresh Timing 2.
Page 273: Figure 7.27 Self-Refresh Timing
After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the LSI standby function, and is maintained even after recovery from standby mode other than through a power-on reset. In case of a power-on reset, the bus state controller’s registers are initialized, and therefore the self-refresh state is cleared.
Page 274: Low-Frequency Mode
7.8.9 Low-Frequency Mode When the SLOW bit in SDCR is set to 1, output of commands, addresses, and write data, and fetch of read data are performed at a timing suitable for operating SDRAM at a low frequency. Figure 7.28 shows the access timing in low-frequency mode. In this mode, commands, addresses, and write data are output in synchronization with the falling edge of CKIO, which is half a cycle delayed than the normal timing.
Page 275: Power-On Sequence
7.8.10 Power-On Sequence In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the C S n R A S...
Page 276 (2) Setting for Area 3 (SDMR3) Burst read/single write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits H'A4FD5440 H'0000440 H'A4FD5460 H'0000460 32 bits H'A4FD5880 H'0000880 H'A4FD58C0 H'00008C0 Burst read/burst write (burst length 1): Data Bus Width CAS Latency Access Address...
Page 277: Burst Rom Interface
Tnop CKIO PALL A25 to A0 A12/A11 * RASU/L CASU/L RD/WR DQMxx * D31 to D0 Hi-Z DACKn * Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. xx is UU, UL, LU, or LL. 3.
Page 278: Figure 7.30 Burst Rom Access (Bus Width 8 Bits, Access Size 32 Bits (Number Of Burst 4), Access Wait For The 1St Time 2, Access Wait For 2Nd Time And After 1)
Table 7.18 Relationship between Bus Width, Access Size, and Number of Bursts Bus Width Access Size Number of Bursts 8 bits 8 bits 16 bits 32 bits 16 bytes 16 bits 8 bits 16 bits 32 bits 16 bytes CKIO Address RD/WR Data...
Page 279: Byte-Selection Sram Interface
7.10 Byte-Selection SRAM Interface The byte-selection SRAM interface is for outputting the byte-selection signal ( ) in both read W E n and write bus cycles. This interface has 16-bit data pins and accesses SRAM that has an upper byte-selection pin and a lower byte-selection pin, such as UB and LB. The write access timing is the same as that for the normal space interface.
Page 280: Figure 7.32 Example Of Connection With 32-Bit Data-Width Byte-Selection Sram
64k × 16-bit This LSI SRAM RD/WR I/O15 I/O0 I/O15 I/O0 Figure 7.32 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM 64k × 16-bit This LSI SRAM RD/WR I/O 15 I/O 0 Figure 7.33 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM Rev.
Page 281: Wait Between Access Cycles
7.11 Wait between Access Cycles As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur.
Page 282 1. 16-byte transition because of a cache miss 2. During copyback operation for the cache 3. Between the read and write cycles of a TAS instruction 4. Multiple bus cycles generated when data bus width is smaller than the access size (For example, between bus cycles when longword access is made to memory with a data bus width of 8 bits.) 5.
Page 283: Others
CKIO BREQ BACK A25 to A0 Data Other bus control signals Figure 7.34 Bus Arbitration In an original slave device designed by the user, multiple bus accesses are generated continuously to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM refresh correctly, the slave device must be designed to release the bus mastership within the refresh interval time.
Page 284 Rev. 2.00, 09/03, page 238 of 690...
Page 285: Section 8 Direct Memory Access Controller (Dmac)
Section 8 Direct Memory Access Controller (DMAC) This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices with DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip peripheral modules.
Page 286: Figure 8.1 Block Diagram Of Dmac
Figure 8.1 shows the block diagram of the DMAC. DMAC module SAR_n Transfer count control DAR_n Register control On-chip DMATCR_n peripheral module Start-up control CHCR_n DMAOR DREQ0, DREQ1 Request SCIF0, SCIF2 priority CMT, USB control A/D converter DMARS0−1 DEIn DACK0, DACK1 TEND0 External interface...
Page 287: Input/Output Pins
Input/Output Pins The external pins for the DMAC are described below. Table 8.1 lists the configuration of the pins that are connected to external bus. The DMAC has pins for 2 channels (channels 0 and 1) for external bus use. Channel 0 has the DMA transfer end signal.
Page 288: Dma Source Address Registers (Sar)
3. Channel 2 • DMA source address register_2 (SAR_2) • DMA destination address register_2 (DAR_2) • DMA transfer count register_2 (DMATCR_2) • DMA channel control register_2 (CHCR_2) 4. Channel 3 • DMA source address register_3 (SAR_3) • DMA destination address register_3 (DAR_3) •...
Page 289: Dma Transfer Count Registers (Dmatcr)
8.3.3 DMA Transfer Count Registers (DMATCR) DMATCR are 32-bit readable/writable registers that specify the DMA transfer count. The number of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers indicate the remaining transfer count.
Page 290 Initial Name Value Descriptions Acknowledge Mode Selects whether DACK is output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK is always output regardless of the specification by this bit. This bit is valid only in CHCR_0 and CHCR_1. This bit is always read as 0 in CHCR_2 and CHCR_3.
Page 291 Initial Name Value Descriptions Source Address Mode Specifies whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, the SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.) 00: Fixed source address (setting prohibited in 16-byte transfer) 01: Source address is incremented (+1 in byte-size transfer, +2...
Page 292 Initial Name Value Descriptions DREQ Level and DREQ Edge Select Select the detection method of the DREQ pin input and the detection level. These bits are valid only in CHCR_0 and CHCR_1. These bits are always read as 0 in CHCR_2 and CHCR_3. The write value should always be 0.
Page 293 Initial Name Value Descriptions R/(W) * Transfer End Flag Indicates that the DMA transfer ends. The TE bit is set to 1 when data transfer ends when DMATCR becomes to 0. The TE bit is not set to 1 in the following cases. •...
Page 294: Dma Operation Register (Dmaor)
8.3.5 DMA Operation Register (DMAOR) DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register shows the DMA transfer status. Initial Name Value Description  15, 14 Reserved These bits are always read as 0. The write value should always be 0.
Page 295 Initial Name Value Description R/(W) * Address Error Flag Indicates that an address error occurred by the DMAC. If this bit is set, DMA transfer is not enabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. This bit can only be cleared by writing 0 after reading 1.
Page 296: Dma Extended Resource Selectors 0, 1 (Dmars0, Dmars1)
8.3.6 DMA Extended Resource Selectors 0, 1 (DMARS0, DMARS1) DMARS is a 16-bit readable/writable register that specifies the DMA transfer request sources from peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 for channels 2 and 3. This register can set the transfer request of SCIF0, SCIF2, and USB. When MID/RID other than the values listed in table 8.2 is set, the operation of this LSI is not guaranteed.
Page 297: Table 8.2 Transfer Request Sources
• DMARS1 Initial Name Value Description 15 to 10 C3MID5 to Transfer request resource module ID5 to ID0 for DMA C3MID0 channel 3 (MID) See table 8.2. C3RID1 Transfer request resource register ID1 and ID0 for DMA channel 3 (RID) C3RID0 See table 8.2.
Page 298: Operation
Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request.
Page 299: Figure 8.2 Dmac Transfer Flowchart
Figure 8.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) DE, DME = 1 and NMIF, AE, TE = 0? Transfer request occurs? * Bus mode, transfer request mode, DREQ detection method Transfer (1 transfer unit); DMATCR −...
Page 300: Dma Transfer Requests
8.4.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by external devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request.
Page 301: Table 8.4 Selecting External Request Detection With Dl, Ds Bits
Table 8.4 Selecting External Request Detection with DL, DS Bits CHCR_0 or CHCR_1 Detection of External Request Low level detection Falling edge detection High level detection Rising edge detection When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept enabled state.
Page 302: Table 8.6 Selecting On-Chip Peripheral Module Request Modes With Rs3 To Rs0 Bits
On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal of an on-chip peripheral module. Transfer request signals comprise the transmit data empty transfer request and receive data full transfer request from the SCIF0 and SCIF2 set by DMARS0/1, the compare-match timer transfer request from the CMT, and transfer requests from the USB.
Page 303: Channel Priority
8.4.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Two modes (fixed mode and round-robin mode) are selected by bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In these modes, the priority levels among the channels remain fixed.
Page 304: Figure 8.3 Round-Robin Mode
Round-Robin Mode: Each time one byte, word, longword, or 16-byte is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority order. The round-robin mode operation is shown in figure 8.3. The priority of round-robin mode is CH0 >...
Page 305: Figure 8.4 Channel Priority In Round-Robin Mode
Figure 8.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2.
Page 306: Dma Transfer Types
8.4.4 DMA Transfer Types DMA transfer has two types; single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to source and destination. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. The DMAC supports the transfers shown in table 8.8.
Page 307: Figure 8.5 Data Flow Of Dual Address Mode
Address Modes • Dual Address Mode In dual address mode, both the transfer source and destination are accessed by an address. The source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle.
Page 308: Figure 8.6 Example Of Dma Transfer Timing In Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory)
CKIO Transfer source Transfer destination A25 to A0 address address D31 to D0 DACKn (Active-Low) Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 8.6 Example of DMA Transfer Timing in Dual Mode (Source: Ordinary Memory, Destination: Ordinary Memory) •...
Page 309: Figure 8.7 Data Flow In Single Address Mode
External address bus External data bus This LSI External DMAC memory External device with DACK DACK DREQ Data flow Figure 8.7 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory.
Page 310: Figure 8.9 Dma Transfer Example In Cycle-Steal Normal Mode
Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TB bits of channel control register (CHCR). a. Cycle-Steal Mode • Normal mode In the normal mode of cycle-steal, the bus right is given to another bus master after a one- transfer-unit (byte, word, long-word, or 16 bytes unit) DMA transfer.
Page 311: Figure 8.10 Example Of Dma Transfer In Cycle Steal Intermittent Mode
Figure 8.10 shows an example of DMA transfer timing in cycle steal intermittent mode. Transfer conditions shown in the figure are:  Dual address mode  DREQ low level detection DREQ More than 16 or 64 Bφ (change by the CPU's condition of using bus) Bus cycle DMAC DMAC CPU CPU DMAC DMAC CPU...
Page 312: Table 8.9 Relationship Of Request Modes And Bus Modes By Dma Transfer Category
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 8.9 shows the relationship between request modes and bus modes by DMA transfer category. Table 8.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Request Transfer Usable...
Page 313: Number Of Bus Cycle States And Dreq Pin Sampling Timing
On the other hand, if channel 0 is operating in cycle-steal mode, channel 1 will begin operating again after channel 0 completes the transfer of one transfer unit, and without the internal bus being released. Transfer will then alternate between the two channels in the order channel 0, channel 1, channel 0, channel 1, and so on.
Page 314: Figure 8.14 Example Of Dreq Input Detection In Cycle Steal Mode Level Detection
CKIO DMAC Bus cycle 1st acceptance 2nd acceptance DREQ Non sensitive period (Overrun 0 at high level) DACK (Active-high) Acceptance start CKIO Bus cycle DMAC 1st acceptance 2nd acceptance DREQ Non sensitive period (Overrun 1 at high level) DACK (Active-high) Acceptance start Figure 8.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection...
Page 315: Figure 8.16 Example Of Dreq Input Detection In Burst Mode Level Detection
CKIO Bus cycle DMAC DREQ 1st acceptance 2nd acceptance (Overrun 0 at Non sensitive high level) DACK (Active-high) Acceptance start CKIO DMAC DMAC Bus cycle 1st acceptance 2nd acceptance DREQ acceptance (Overrun 1 at Non sensitive high level) DACK (Active-high) Acceptance Acceptance start...
Page 316: Precautions
CKIO Address Data DACKn TEND0 WAIT Note: TEND0 is asserted during the last transfer unit of DMA transfer. When the transfer unit is divided into several bus cycles and CS is negated between bus cycles, TEND0 is also divided. Figure 8.18 BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) Precautions 8.5.1...
Page 317: Section 9 Clock Pulse Generator (Cpg)
Section 9 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock (Pφ), and a bus clock (Bφ). The CPG consists of oscillators, PLL circuits, and divider circuits. Features •...
Page 318: Figure 9.1 Block Diagram Of Clock Pulse Generator
CPG oscillator circuit unit Crystal XTAL_USB Oscillator USB clock EXTAL_USB Divider 1 ×1 ×1/2 PLL circuit 1 Internal clock ×1/3 (×1, 2, 3, 4) (Iφ) ×1/4 Bus clock CKIO (Bφ = CKIO) Crystal Peripheral clock XTAL Oscillator PLL circuit 2 (Pφ) (×1, 2, 4) EXTAL...
Page 319 The clock pulse generator blocks function as follows: 1. PLL Circuit 1 PLL circuit 1 doubles, triples, quadruples, or leaves unchanged the input clock frequency from the CKIO pin or PLL circuit 2. The multiplication rate is set by the frequency control register. When this is done, the phase of the rising edge of the internal clock is controlled so that it will synchronize with the phase of the rising edge of the CKIO pin.
Page 320: Input/Output Pins
Input/Output Pins Table 9.1 lists the CPG pins and their functions. Table 9.1 Clock Pulse Generator Pins and Functions Pin Name Symbol Description Mode control pins Set the clock-operating mode. Set the clock-operating mode. Set the clock-operating mode. XTAL Connects a crystal resonator. Crystal oscillator pins for system clock EXTAL...
Page 321: Clock Operating Modes
Clock Operating Modes Table 9.2 shows the relationship between the mode control pins (MD2 to MD0) combinations and the clock operating modes. Table 9.3 shows the usable frequency ranges in the clock operating modes and the frequency range of the input clock. Table 9.2 Clock Operating Modes Pin Values...
Page 322: Table 9.3 Possible Combination Of Clock Modes And Frqcr Values
Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and executes waveform shaping, and also frequency multiplication according to the setting, by PLL circuit 1 before being supplied to this LSI. As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM.
Page 323 Input Clock / Crystal Resonator Clock Rate * Clock Frequency FRQCR * Mode PLL1 PLL2 CKIO Frequency Range Range (I:B:P) H'1000 2:2:2 10.00 MHz to 16.67 MHz 20.00 MHz to 33.34 MHz ON (× 1) ON (× 2) H'1001 2:2:1 10.00 MHz to 33.34 MHz 20.00 MHz to 66.67 MHz ON (×...
Page 324 Input Clock / Crystal Resonator Clock Rate * Clock Frequency FRQCR * Mode PLL1 PLL2 CKIO Frequency Range Range (I:B:P) H'1000 1:1:1 20.00 MHz to 33.34 MHz 20.00 MHz to 33.34 MHz ON (× 1) H'1001 1:1:1/2 20.00 MHz to 66.67 MHz 20.00 MHz to 66.67 MHz ON (×...
Page 325: Register Descriptions
Register Descriptions The CPG has the following registers. Refer to section 24, List of Registers, for the addresses of the registers and the state of each register in each processor state. • Frequency control register (FRQCR) • USB clock control register (UCLKCR) 9.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify...
Page 326 Initial Name Value Description STC1 Frequency Multiplication Ratio 00: × 1 time STC0 01: × 2 times 10: × 3 times 11: × 4 times  7, 6 Reserved These bits are always read as 0. The write value should always be 0. IFC1 Internal Clock Frequency Division Ratio IFC0...
Page 327: Usb Clock Frequency Control Register (Uclkcr)
9.4.2 USB Clock Frequency Control Register (UCLKCR) UCLKCR is an 8-bit readable/writable register. Word-size access is used to write to this register. This writing should be performed with H'A5 in the upper byte and the write data in the lower byte. Initial Name Value...
Page 328: Changing Frequency
Changing Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider 1. All of these are controlled by software through the frequency control register. The methods are described below. 9.5.1 Changing Multiplication Rate A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed.
Page 329: Usage Notes
Usage Notes When Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2, and damping resistance R as close as possible to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components.
Page 330: Figure 9.3 Points For Attention When Using Pll Oscillator Circuit
Avoid crossing signal lines -PLL2 Power supply -PLL2 -PLL1 -PLL1 Figure 9.3 Points for Attention when Using PLL Oscillator Circuit −PLL1, Notes on Wiring Power Supply Pins: To avoid crossing signal lines, wire V −PLL2, V −PLL1, and V −PLL2 as three patterns from the power supply source on the board so that they are independent of digital V and V Rev.
Page 331: Section 10 Watchdog Timer (Wdt)
Section 10 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT) and can be reset by the overflow of the counter when the value of the counter has not been updated because of an erroneous system operation. The WDT is a single-channel timer that uses a peripheral clock as an input and counts the clock settling time when clearing software standby mode and temporary standbys, such as frequency changes.
Page 332: Register Descriptions
Figures 10.1 shows a block diagram of the WDT. Standby Standby Standby mode cancellation control Peripheral clock Internal Reset Divider reset control request Clock selection Clock selector Overflow Interrupt Interrupt request control Clock WTCSR WTCNT Bus interface Legend WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter Figure 10.1 Block Diagram of WDT...
Page 333: Watchdog Timer Control/Status Register (Wtcsr)
Note: WTCNT differs from other registers in that it is more difficult to write to. See section 10.2.3, Notes on Register Access, for details. 10.2.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and enable bits.
Page 334 Initial Name Value Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT in software standby mode or when changing the clock frequency. 0: Timer disabled: Count-up stops and WTCNT value is retained 1: Timer enabled Timer Mode Select Selects whether to use the WDT as a watchdog timer...
Page 335: Notes On Register Access
Initial Name Value Description CKS2 Clock Select 2 to 0 CKS1 These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the CKS0 peripheral clock. The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (Pφ) is 15 MHz.
Page 336: Operation
WTCNT write H'5A Write data WTCSR write H'A5 Write data Figure 10.2 Writing to WTCNT and WTCSR 10.3 Operation 10.3.1 Canceling Software Standbys The WDT is used to cancel software standby mode with an interrupt such as an NMI. The procedure when using an NMI interrupt is described below.
Page 337: Changing Frequency
10.3.2 Changing Frequency To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
Page 338 Rev. 2.00, 09/03, page 292 of 690...
Page 339: Section 11 Power-Down Modes
Section 11 Power-Down Modes This LSI has four types of the power-down modes: sleep mode, software standby mode, module standby function, and hardware standby mode. 11.1 Features This LSI has the following power-down modes and function: 1. Sleep mode 2. Software standby mode 3.
Page 340: Table 11.1 States Of Power-Down Modes
Table 11.1 States of Power-Down Modes State On-Chip Transition Peripheral External Canceling Mode Conditions CPG CPU Register Modules Pins Memory Condition Sleep mode Execute SLEEP Halt Held Refresh 1. Interrupt instruction with 2. Reset STBY bit cleared to 0 in STBCR Halt * Software Execute SLEEP...
Page 341: Input/Output Pins
11.2 Input/Output Pins Table 11.2 lists the pins used for the power-down modes. Table 11.2 Pin Configuration Pin Name Symbol Description Processing state STATUS1, Operating state of the processor. STATUS0 HH: Reset HL: Sleep mode LH: Standby mode LL: Normal operation Note: H means high level, and L means low level.
Page 342: Standby Control Register (Stbcr)
11.3.1 Standby Control Register (STBCR) STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. Bit Name Initial Value R/W Description STBY Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction puts chip into sleep mode 1: Executing SLEEP instruction puts chip into software standby mode...
Page 343: Standby Control Register 2 (Stbcr2)
11.3.2 Standby Control Register 2 (STBCR2) STBCR2 is an 8-bit readable/writable register that controls the operation of modules in the power- down mode. Bit Name Initial Value R/W Description MSTP10 Module Stop Bit 10 When the MSTP10 bit is set to 1, the clock supply to the UDI is halted.
Page 344: Standby Control Register 3 (Stbcr3)
Bit Name Initial Value R/W Description  1, 0 Reserved These bits are always read as 0. The write value should always be 0. 11.3.3 Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of modules in the power- down mode.
Page 345: Sleep Mode
Bit Name Initial Value R/W Description MSTP32 Module Stop Bit 32 When the MSTP32 bit is set to 1, the clock supply to the IrDA is halted. 0: IrDA runs 1: Clock supply to IrDA is halted MSTP31 Module Stop Bit 31 When the MSTP31 bit is set to 1, the clock supply to the SCIF2 is halted.
Page 346: Software Standby Mode
11.5 Software Standby Mode 11.5.1 Transition to Software Standby Mode The LSI switches from a program execution state to software standby mode by executing the SLEEP instruction when the STBY bit is 1 in STBCR. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
Page 347: Module Standby Function
Notes: 1. Only when the RTC is being used can standby mode be canceled using IRQ, IRL, PINT, or RTC. 2. Use a power-on reset to cancel software standby mode. Interrupt WDT overflow and branch to request interrupt handling routine Crystal oscillator settling Clear the STBY bit in STBCR before time and PLL synchronization...
Page 348: Canceling Module Standby Function
11.6.2 Canceling Module Standby Function The module standby function can be canceled by clearing the MSTP bits to 0 or by a power-on reset. When canceling the module standby function by clearing the corresponding MSTP bit, be sure to read the relevant MSTP bit to confirm that it has been cleared to 0. 11.7 Hardware Standby Mode 11.7.1...
Page 349: Timing Of Status Pin Changes
11.8 Timing of STATUS Pin Changes The timing of the STATUS0 and STATUS1 pin changes is shown in figures 11.2 to 11.9. In Case of A Reset: a. Power-on reset CKIO PLL settling time RESETP Normal * Reset * Normal * STATUS 0 to 5 Bcyc * 0 to 30 Bcyc *...
Page 350: Figure 11.4 Canceling Software Standby By Interrupt Status Output
In Case of Canceling Software Standby: a. Canceling software standby by interrupt Oscillation stops Interrupt request WDT overflow CKIO WDT count Normal * Standby * Normal * STATUS Notes: 1. Standby: LH (STATUS1 low, STATUS0 high) 2. Normal: LL (STATUS1 low, STATUS0 low) Figure 11.4 Canceling Software Standby by Interrupt STATUS Output b.
Page 351: Figure 11.6 Canceling Software Standby By Manual Reset Status Output
c. Canceling software standby by manual reset Oscillation stops Reset CKIO RESETM * Normal * Standby * Reset * Normal * STATUS 0 to 20 Bcyc * Notes: 1. When software standby mode is cleared with a manual reset, the WDT does not count. Keep RESETM low during the PLL’s oscillation settling time.
Page 352: Figure 11.8 Canceling Sleep By Power-On Reset Status Output
b. Canceling sleep by power-on reset Reset CKIO RESETP * Normal * Sleep * Reset * Normal * STATUS 0 to 10 Bcyc * 0 to 30 Bcyc * Notes: 1. When the PLL1's multiplication ratio is changed by a power-on reset, keep RESETP low during the PLL's oscillation settling time.
Page 353: Figure 11.10 Hardware Standby Mode (When Ca Goes Low In Normal Operation)
a. Normal operation to hardware standby CKIO RESETP Normal * Standby * Reset * Normal * STATUS Undefined 0−10Bcyc * 2 Rcyc or more * 0−30Bcyc Notes: 1. Reset: HH (STATUS1 high, STATUS0 high) 2. Standby: LH (STATUS1 low, STATUS0 high) 3.
Page 354 Rev. 2.00, 09/03, page 308 of 690...
Page 355: Section 12 Timer Unit (Tmu)
Section 12 Timer Unit (TMU) This LSI includes a three-channel 32-bit timer unit (TMU). 12.1 Features • Each channel is provided with an auto-reload 32-bit down counter • All channels are provided with 32-bit constant registers and 32-bit down counters for an auto- reload function that can be read or written to at any time •...
Page 356: Figure 12.1 Tmu Block Diagram
Figure 12.1 shows a block diagram of the TMU. Bus interface Prescaler Pφ TCLK Clock controller TSTR Ch. 0 TCR_0 Counter controller TCNT_0 TCOR_0 Interrupt TUNI0 controller Ch. 1 TCR_1 Counter controller TCNT_1 TCOR_1 Interrupt TUNI1 controller Ch. 2 TCR_2 Counter TCPR_2 controller...
Page 357: Input/Output Pin
12.2 Input/Output Pin Table 12.1 shows the pin configuration of the TMU. Table 12.1 Pin Configuration Name Abbreviation I/O Description Clock input TCLK External clock input pin/input capture control input pin 12.3 Register Descriptions The TMU has the following registers. Refer to section 24, List of Registers, for more details of the addresses of these registers and state of these registers in each processing state.
Page 358: Timer Start Register (Tstr)
12.3.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects whether to run or halt the timer counters (TCNT). TSTR is initialized by satisfying the initialization conditions shown in section 24, List of Registers, changing the multiplication ratio of PLL1, or setting the MSTP2 bit in STBCR to 1. Bit Name Initial Value Description...
Page 359: Timer Control Registers (Tcr)
12.3.2 Timer Control Registers (TCR) TCR are 16-bit readable/writable registers that control the timer counters (TCNT) and interrupts. TCR control the issuance of interrupts when the flag indicating timer counter (TCNT) underflow has been set to 1, and also carry out counter clock selection. When the external clock has been selected, they also select its edge.
Page 360 Bit Name Initial Value Description CKEG1 Clock Edge CKEG0 Select an input edge of the external clock when the external clock is selected. 00: Count on rising edge 01: Count on falling edge 1X: Count on both rising and falling edges Note: X: Don’t care TPSC2 Timer Prescaler...
Page 361 TCR_2: Bit Name Initial Value Description 15 to 10  Reserved These bits are always read as 0. The write value should always be 0. R/(W) * Input Capture Interrupt Flag ICPF A function of channel 2 only: the flag is set when input capture is requested via the TCLK pin.
Page 362 Bit Name Initial Value Description ICPE1 Input Capture Control ICPE0 A function of channel 2 only: determines whether the input capture function can be used, and when used, whether or not to enable interrupts. Use the CKEG1 and CKEG0 bits to designate use of either the rising or falling edge of the TCLK pin to set the value of TCNT_2 in TCPR_2.
Page 363: Timer Constant Registers (Tcor)
Bit Name Initial Value Description TPSC2 Timer Prescaler TPSC1 Select the TCNT_2 count clock. TPSC0 000: Count on Pφ/4 001: Count on Pφ/16 010: Count on Pφ/64 011: Count on Pφ/256 100: Setting prohibited 101: Count on TCLK pin input 110: Setting prohibited 111: Setting prohibited Note: * Only 0 can be written for clearing the flags.
Page 364: Operation
12.4 Operation Each of the three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). The TCNT counts down. The auto-reload function enables synchronized counting and counting by external events. Channel 2 has an input capture function. 12.4.1 Counter Operation When the STR0 to STR2 bits in the timer start register (TSTR) are set to 1, the corresponding...
Page 365: Figure 12.3 Auto-Reload Count Operation
Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation. TCOR value set to TCNT value TCNT during underflow TCOR H'00000000 Time STR0−STR2 Figure 12.3 Auto-Reload Count Operation TCNT Count Timing: 1. Internal Clock Operation: Set the TPSC2 to TPSC0 bits in TCR to select whether one of the four internal clocks created by dividing the peripheral module clock is used (Pφ/4, Pφ/16, Pφ/64, Pφ/256).
Page 366: Input Capture Function
2. External Clock Operation: Set the TPSC2 to TPSC0 bits in TCR to select the external clock (TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection edge. Rise, fall or both may be selected. The pulse width of the external clock must be at least 2 peripheral module clock cycles (Pφ) for single edges or 3 peripheral module clock cycles (Pφ) for both edges.
Page 367: Interrupts
12.5 Interrupts There are two sources of TMU interrupts: underflow interrupts (TUNI) and interrupts when using the input capture function (TICPI2). 12.5.1 Status Flag Set Timing The UNF bit is set to 1 when the TCNT underflows. Figure 12.7 shows the timing. Pφ...
Page 368: Interrupt Sources And Priorities
12.5.3 Interrupt Sources and Priorities The TMU generates underflow interrupts for each channel. When the interrupt request flag and interrupt enable bit are both set to 1, the relevant interrupt is requested. Codes are set in the interrupt event register (INTEVT and INTEVT2) for these interrupts and interrupt processing must be executed according to the codes.
Page 369: Section 13 Compare Match Timer (Cmt)
Section 13 Compare Match Timer (CMT) The DMAC has an on-chip compare match timer (CMT) to generate a DMA transfer request. The CMT has 16-bit counter. Figure 13.1 shows a CMT block diagram. 13.1 Features • Four types of counter input clock can be selected. One of four internal clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) can be selected.
Page 370: Register Descriptions
13.2 Register Descriptions The CMT has the following registers. Refer to section 24, List of Registers, for more detail of the addresses and access size. • Compare match timer start register (CMSTR) • Compare match timer control/status register (CMCSR) • Compare match counter (CMCNT) •...
Page 371: Compare Match Timer Control/Status Register (Cmcsr)
13.2.2 Compare Match Timer Control/Status Register (CMCSR) CMCSR is a 16-bit register that indicates the occurrence of compare matches, and sets the enable/disable of DMA transfer requests and the clock used for incrementation. Bit Name Initial Value Description 15 to 8 —...
Page 372: Compare Match Counter (Cmcnt)
13.2.3 Compare Match Counter (CMCNT) CMCNT is a 16-bit register used as an up-counter. When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT value matches that of CMCOR, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1.
Page 373: Cmcnt Count Timing
13.3.2 CMCNT Count Timing One of four clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) obtained by dividing the peripheral clock (Pφ) can be selected by the CKS1 and CKS0 bits in CMCSR. Figure 13.3 shows the timing. Pφ Internal clock CMCNT input clock CMCNT Figure 13.3 Count Timing...
Page 374 Rev. 2.00, 09/03, page 328 of 690...
Page 375: Section 14 16-Bit Timer Pulse Unit (Tpu)
Section 14 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises four 16-bit timer channels. 14.1 Features • Maximum 4-pulse output A total of 16 timer general registers (TGRA to TGRD × 4 ch.) are provided (four each for channels).
Page 376: Table 14.1 Tpu Functions
Table 14.1 lists the functions of the TPU. Table 14.1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Count clock Pφ/1 Pφ/1 Pφ/1 Pφ/1 Pφ/4 Pφ/4 Pφ/4 Pφ/4 Pφ/16 Pφ/16 Pφ/16 Pφ/16 Pφ/64 Pφ/64 Pφ/64 Pφ/64 General registers TGR0A TGR1A TGR2A...
Page 377: Figure 14.1 Block Diagram Of Tpu
Pφ/1 Pφ/4 Counter Clock Edge Pφ Divider Pφ/16 selection selection Output Pφ/64 control Channel 0 clear TGRA Buffer TGRB Comparator TGRC TGRD Channel 1 Same as channel 0 Clock Edge Counter selection selection Output control clear Channel 2 TGRA Buffer TGRB Comparator TGRC...
Page 378: Input/Output Pins
14.2 Input/Output Pins Table 14.2 shows the pin configuration of the TPU. Table 14.2 Pin Configuration Channel Name Symbol Function Output compare TGR0A output compare output/PWM output match 0 Output compare TGR1A output compare output/PWM output match 1 Output compare TGR2A output compare output/PWM output match 2 Output compare...
Page 379 • Timer counter_1 (TCNT_1) • Timer general register A_1 (TGRA_1) • Timer general register B_1 (TGRB_1) • Timer general register C_1 (TGRC_1) • Timer general register D_1 (TGRD_1) 3. Channel 2 • Timer control register_2 (TCR_2) • Timer mode register_2 (TMDR_2) •...
Page 380: Timer Control Registers (Tcr)
14.3.1 Timer Control Registers (TCR) TCR are 16-bit registers that control the TCNT channels. TCR register settings should be made only when TCNT operation is stopped. Initial Bit Name Value Description 15 to 8  Reserved These bits are always read as 0 and cannot be modified. CCLR2 Counter Clear CCLR1...
Page 381: Table 14.3 Tpu Clock Sources
Table 14.3 TPU Clock Sources Internal Clock Pφ φ φ φ /1 Pφ φ φ φ /4 Pφ φ φ φ /16 Pφ φ φ φ /64 Channel [Legend] : Setting Blank: No setting Table 14.4 TPSC2 to TPSC0 (1) Bit 2 Bit 1 Bit 0...
Page 382: Table 14.4 Tpsc2 To Tpsc0 (3)
Table 14.4 TPSC2 to TPSC0 (3) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 Setting prohibited Note: X: Don’t care Table 14.4 TPSC2 to TPSC0 (4) Bit 2 Bit 1...
Page 383: Timer Mode Registers (Tmdr)
14.3.2 Timer Mode Registers (TMDR) TMDR are 16-bit readable/writable registers that are used to set the operating mode for each channel. TMDR register settings should be made only when TCNT operation is stopped. Initial Bit Name Value Description 15 to 7  Reserved These bits are always read as 0 and cannot be modified.
Page 384: Timer I/O Control Registers (Tior)
14.3.3 Timer I/O Control Registers (TIOR) TIOR are 16-bit registers that control the TO pin. TIOR register settings should be made only when TCNT operation is stopped. Care is required since TIOR is affected by the TMDR setting. Initial Bit Name Value Description 15 to 3 ...
Page 385: Timer Interrupt Enable Registers (Tier)
14.3.4 Timer Interrupt Enable Registers (TIER) TIER are 16-bit registers that control enabling or disabling of interrupt requests for each channel. Initial Bit Name Value Description 15 to 5  Reserved These bits are always read as 0 and cannot be modified. TCIEV Overflow Interrupt Enable Enables or disables interrupt requests by the TCFV bit when...
Page 386: Timer Status Registers (Tsr)
14.3.5 Timer Status Registers (TSR) TSR are 16-bit registers that indicate the status of each channel. Initial Bit Name Value R/W Description 15 to 5  Reserved These bits are always read as 0 and cannot be modified. R/(W) * Overflow Flag TCFV Status flag that indicates that TCNT overflow has occurred.
Page 387: Timer Counters (Tcnt)
Initial Bit Name Value R/W Description R/(W) * Output Compare Flag A TGFA Status flag that indicates the occurrence of TGRA compare match. [Clearing condition] When 0 is written to TGFA after reading TGFA = 1 [Setting condition] When TCNT = TGRA Note: * Only 0 can be written for clearing the flags.
Page 388: Operation
14.4 Operation 14.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation and periodic counting. Buffer Operation: When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR.
Page 389: Basic Functions
14.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST3 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 14.2 shows an example of the count operation setting procedure.
Page 390: Figure 14.3 Free-Running Counter Operation
• Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
Page 391: Figure 14.5 Example Of Setting Procedure For Waveform Output By Compare Match
Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin (TO pin) using TGRA compare match. • Example of setting procedure for waveform output by compare match Figure 14.5 shows an example of the setting procedure for waveform output by compare match [1] Select initial value 0 output or 1 output, and Output selection compare match output value 0 output, 1 output,...
Page 392: Buffer Operation
Figure 14.7 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by compare match A. TCNT value Counter cleared by TGRB compare match H'FFFF...
Page 393: Figure 14.9 Example Of Buffer Operation Setting Procedure
Example of Buffer Operation Setting Procedure: Figure 14.9 shows an example of the buffer operation setting procedure. [1] Designate TGR for buffer operation with bits Buffer operation BFA and BFB in TMDR. [2] Set rewriting timing from the buffer register with Set buffer operation bit BFWT in TMDR.
Page 394: Pwm Modes
TCNT value N (TGRB+1) TGRB N (B) N (A) TGRA Time H'0000 N (A) N (B) N (TGRB+1) TGRC N (TGRB+1) N (A) N (B) TGRA TO pin Figure 14.10 Example of Buffer Operation 14.4.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0 or 1 output can be selected as the output level in response to compare match of each TGRA.
Page 395: Figure 14.11 Example Of Pwm Mode Setting Procedure
Example of PWM Mode Setting Procedure: Figure 14.11 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 396: Figure 14.12 Example Of Pwm Mode Operation (1)
Examples of PWM Mode Operation: Figure 14.12 shows an example of PWM mode operation. In this example, TGRB compare match is set as the TCNT clearing source, 0 is set as the initial output value of the TO pin by TGRA, and 1 is set as the output value by TGRA compare match. In this case, the value set in TGRB is used as the period, and the value set in TGRA as the duty.
Page 397: Section 15 Realtime Clock (Rtc)
Section 15 Realtime Clock (RTC) This LSI has a realtime clock (RTC) with its own 32.768 kHz crystal oscillator. A block diagram of the RTC is shown in figure 15.1. 15.1 Features The RTC has the following features: • Clock and calendar functions (BCD format): seconds, minutes, hours, date, day of the week, month, and year •...
Page 398: Figure 15.1 Rtc Block Diagram
Externally connected circuit EXTAL2 second Reset 128 Hz Oscillator circuit XTAL2 R64CNT 32.768 kHz interface RSECCNT Prescaler RMINCNT (÷ 2) RHRCNT 16.384 kHz RWKCNT RDAYCNT Prescaler (÷ 128) RMONCNT RYRCNT Interrupt Comparator control circuit RSECAR RMINAR Carry RHRAR detection RWKAR circuit RDAYAR RMONAR...
Page 399: Input/Output Pins
15.2 Input/Output Pins Table 15.1 shows the RTC pin configuration. Table 15.1 Pin Configuration Abbreviation I/O Function Connects crystal to RTC oscillator * Crystal oscillator for RTC EXTAL2 Connects crystal to RTC oscillator * Crystal oscillator for RTC XTAL2 Power-supply for RTC -RTC —...
Page 400: 64-Hz Counter (R64Cnt)
15.3.1 64-Hz Counter (R64CNT) The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the state of the divider circuit between 64 Hz and 1 Hz. R64CNT is reset to H'00 by setting the RESET bit in RCR2 or the ADJ bit in RCR2 to 1. R64CNT is not initialized by a power-on reset or manual reset, or in standby mode.
Page 401: Minute Counter (Rmincnt)
Bit Name Initial Value Description  Reserved This bit is always read as 0. The write value should always be 0.   6 to 4 10-unit of the second counter in the BCD-code. The range that can be set is 0 to 5 (decimal). ...
Page 402: Day Of Week Counter (Rwkcnt)
Bit Name Initial Value Description  7, 6 Reserved These bits are always read as 0. The write value should always be 0.   5, 4 10-unit of the hour counter in the BCD-code. The range that can be set is 0 to 2 (decimal). ...
Page 403: Date Counter (Rdaycnt)
15.3.6 Date Counter (RDAYCNT) The date counter (RDAYCNT) is an 8-bit readable/writable register used for setting/counting in the BCD-coded date section. The count operation is performed by a carry for each day of the hour counter. The range of date that can be set changes within 01 to 31 (decimal) with some months and in leap years.
Page 404: Year Counter (Ryrcnt)
15.3.8 Year Counter (RYRCNT) The year counter (RYRCNT) is a 16-bit readable/writable register used for setting/counting in the BCD-coded year section. The four digits of the western calendar year are counted. The count operation is performed by a carry for each year of the month counter. The range for year that can be set is 0000 to 9999 (decimal).
Page 405: Minute Alarm Register (Rminar)
Bit Name Initial Value Description Second Alarm Enable Specifies whether to compare RSECCNT with RSECAR to generate a second alarm. 0: Not compared 1: Compared   6 to 4 10-unit of second alarm setting in the BCD-code. The range that can be set is 0 to 5 (decimal). ...
Page 406: Hour Alarm Register (Rhrar)
15.3.11 Hour Alarm Register (RHRAR) The hour alarm register (RHRAR) is an 8-bit readable/writable register, and an alarm register corresponding to the hour counter RHRCNT. When the ENB bit is set to 1, a comparison with the RHRCNT value is performed. For alarm registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR, a comparison with the corresponding counter value is performed for those whose ENB bit is set to 1, and for RCR3, a comparison is performed when the YAEN bit is set to 1.
Page 407: Day Of Week Alarm Register (Rwkar)
15.3.12 Day of Week Alarm Register (RWKAR) The day of week alarm register (RWKAR) is an 8-bit readable/writable register, and an alarm register corresponding to the day of week counter RWKCNT. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed.
Page 408: Date Alarm Register (Rdayar)
15.3.13 Date Alarm Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit readable/writable register, and an alarm register corresponding to the date counter RDAYCNT. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. For alarm registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR, a comparison with the corresponding counter value is performed for those whose ENB bit is set to 1, and for RCR3, a comparison is performed when the YAEN bit is set to 1.
Page 409: Month Alarm Register (Rmonar)
15.3.14 Month Alarm Register (RMONAR) The month alarm register (RMONAR) is an 8-bit readable/writable register, and an alarm register corresponding to the month counter RMONCNT. When the ENB bit is set to 1, a comparison with the RMONCNT value is performed. For alarm registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR, a comparison with the corresponding counter value is performed for those whose ENB bit is set to 1, and for RCR3, a comparison is performed when the YAEN bit is set to 1.
Page 410: Year Alarm Register (Ryrar)
15.3.15 Year Alarm Register (RYRAR) The year alarm register (RYRAR) is a 16-bit readable/writable register, and an alarm register corresponding to the year counter RYRCNT. When the YAEN bit in RCR3 is set to 1, a comparison with the RYRCNT value is performed. For alarm registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR, a comparison with the corresponding counter value is performed for those whose ENB bit is set to 1, and for RCR3, a comparison is performed when the YAEN bit is set to 1.
Page 411: Rtc Control Register 1 (Rcr1)
15.3.16 RTC Control Register 1 (RCR1) The RTC control register 1 (RCR1) is an 8-bit readable/writable register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. Because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. RCR1 is initialized to H'00 by a power-on reset or a manual reset.
Page 412: Rtc Control Register 2 (Rcr2)
Bit Name Initial Value Description 2, 1 — Reserved These bits are always read as 0. The write value should always be 0. Alarm Flag The AF flag is set to 1 when the alarm time set in an alarm register (only registers with ENB bit of the corresponding alarm registers and YAEN bit in RCR3 set to 1) matches the clock and calendar time.
Page 413 Bit Name Initial Value Description PES2 Periodic Interrupt Interval PES1 These bits specify the periodic interrupt interval. PES0 000: No periodic interrupts generated 001: Periodic interrupt generated every 1/256 second 010: Periodic interrupt generated every 1/64 second 011: Periodic interrupt generated every 1/16 second 100: Periodic interrupt generated every 1/4 second...
Page 414: Rtc Control Register 3 (Rcr3)
Bit Name Initial Value Description START Start Bit Halts and restarts the counter (clock). 0: Second/minute/hour/day/week/month/year counter halts. * 1: Second/minute/hour/day/week/month/year counter runs normally. * Note: * The 64-Hz counter always runs unless stopped with the RTCEN bit. 15.3.18 RTC Control Register 3 (RCR3) The RTC control register 3 (RCR3) is an 8-bit readable/writable register that controls the comparison between the BCD-coded year section counter RYRCNT of the RTC and the year alarm register RYRAR.
Page 415: Operation
15.4 Operation 15.4.1 Initial Settings of Registers after Power-On All the registers should be set after the power is turned on. 15.4.2 Setting Time Figure 15.2 shows how to set the time when the clock is stopped. Write 1 to RESET and 0 to Stop clock, START in the RCR2 register reset divider circuit...
Page 416: Reading The Time
15.4.3 Reading the Time Figure 15.3 shows how to read the time. If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 15.3 shows the method of reading the time without using interrupts;...
Page 417: Alarm Function
15.4.4 Alarm Function Figure 15.4 shows how to use the alarm function. Alarms can be generated using seconds, minutes, hours, day of the week, date, month, year, or any combination of these. Set the ENB or YAEN bit for the register on which the alarm is placed to 1, and then set the alarm time in the lower bits.
Page 418: Crystal Oscillator Circuit
15.4.5 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 15.2, and the RTC crystal oscillator circuit in figure 15.5. Table 15.2 Recommended Oscillator Circuit Constants (Recommended Values) 32.768 kHz 10 to 22 pF 10 to 22 pF This LSI EXTAL2 XTAL2...
Page 419: Notes For Usage
15.5 Notes for Usage 15.5.1 Register Writing during RTC Count The following RTC registers cannot be written to during an RTC count (while the START bit in RCR2 = 1). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCNT The RTC count must be halted before writing to any of the above registers. 15.5.2 Use of Realtime Clock (RTC) Periodic Interrupts The method of using the periodic interrupt function is shown in figure 15.6.
Page 420 Rev. 2.00, 09/03, page 374 of 690...
Page 421: Section 16 Serial Communication Interface With Fifo (Scif)
Section 16 Serial Communication Interface with FIFO (SCIF) This LSI has a two-channel serial communication interface with on-chip FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous and clock synchronous serial communication. 64-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication.
Page 422 There are six interrupt sourcestransmit-data-stop, transmit-FIFO-data-empty, receive-FIFO- data-full, receive-error (framing/parity error), break-receive, and receive-data-ready interrupts. • Two interrupt sources in clock synchronous mode There are two interrupt sourcestransmit-FIFO-data-empty and receive-FIFO-data-full interrupts. • The DMA controller (DMAC) can be activated to execute a data transfer in the event of a transmit-FIFO-data-empty, transmit-data-stop, or receive-FIFO-data-full interrupt.
Page 423: Figure 16.1 Block Diagram Of Scif
Figure 16.1 shows a block diagram of the SCIF. Peripheral Module data bus SCFDR SCFRDR SCFTDR SCFCR SCBRR (64-stage) (64-stage) SCFER SCSSR SCRSR SCTSR SCSCR Baud rate Pφ SCSMR generator Pφ/4 SCTDSR Pφ/16 Transmission/ reception control Pφ/64 Parity generation Clock Parity check External clock SCIF...
Page 424: Input/Output Pins
16.2 Input/Output Pins Table 16.1 shows the SCIF pin configuration. Table 16.1 Pin Configuration Abbreviation * Channel Pin Name Function Serial clock SCK0 Input/output Clock input/output RxD * Receive data RxD0 Input Receive data input TxD * Transmit data TxD0 Output Transmit data output Modem control...
Page 425: Register Descriptions
16.3 Register Descriptions The SCIF has the following internal registers. For details on register addresses and register states in each processing state, refer to section 24, List of Registers. 1. Channel 0 • Serial mode register 0 (SCSMR_0) • Bit rate register 0 (SCBRR_0) •...
Page 426: Receive Shift Register (Scrsr)
16.3.1 Receive Shift Register (SCRSR) SCRSR is the register used to receive serial data. The SCIF sets serial data input from the RxD pin in SCRSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to the receive FIFO data register, SCFRDR, automatically.
Page 427: Transmit Fifo Data Register (Scftdr)
16.3.4 Transmit FIFO Data Register (SCFTDR) SCFTDR is an 8-bit 64-stage FIFO data register that stores data for serial transmission. If SCTSR is empty when transmit data is written to SCFTDR, the SCIF transfers the transmit data written in SCFTDR to SCTSR and starts serial transmission. SCFTDR is a write-only register, and cannot be read by the CPU.
Page 428 Initial Name Value Description  15 to 11 Reserved These bits are always read as 0. The write value should always be 0. SRC2 Sampling Control SRC1 Select the sampling rate in asynchronous mode. This setting is valid only in asynchronous mode. SRC0 000: Sampling rate 1/16 001: Sampling rate 1/5...
Page 429 Initial Name Value Description Parity Enable Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. This setting is only valid in asynchronous mode. In synchronous mode, parity bit addition and checking is not performed, regardless of the PE setting.
Page 430 Initial Name Value Description STOP Stop Bit Length Selects one or two bits as the stop bit length. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit;...
Page 431: Serial Control Register (Scscr)
16.3.6 Serial Control Register (SCSCR) SCSCR is a 16-bit readable/writable register that enables or disables the SCIF transfer operations and interrupt requests, and selects the serial clock source. Initial Name Value Description  15 to 12 Reserved These bits are always read as 0. The write value should always be 0.
Page 432 Initial Name Value Description BRIE Break Interrupt Enable Enables or disables generation of a break-receive interrupt when the BRK flag in SCSSR is set to 1. 0: Break-receive interrupt disabled * 1: Break-receive interrupt enabled Note: * The interrupt request is cleared by clearing the BRK flag to 0 after reading 1 from it or clearing the BRIE bit to 0.
Page 433 Initial Name Value Description Transmit Enable Enables or disables the start of serial transmission by the SCIF. 0: Transmission disabled 1: Transmission enabled * Note: * The serial mode register (SCSMR) and FIFO control register (SCFCR) settings must be made, the transmit format decided, and the transmit FIFO reset, before the TE bit is set to 1.
Page 434 Initial Name Value Description CKE1 Clock Enable CKE0 Select the SCIF clock source. The CKE1 and CKE0 bits must be set before determining the SCIF operating mode with SCSMR. 00: Internal clock/SCK pin functions as input pin (input signal ignored) 01: Internal clock/SCK pin functions as serial clock output * 10: External clock/SCK pin functions as clock input *...
Page 435: Fifo Error Count Register (Scfer)
16.3.7 FIFO Error Count Register (SCFER) SCFER is a 16-bit read-only register that indicates the number of receive errors (framing or parity error). Initial Name Value Description  15, 14 Reserved These bits are always read as 0. The write value should always be 0.
Page 436: Serial Status Register (Scssr)
16.3.8 Serial Status Register (SCSSR) SCSSR is a 16-bit readable/writable register that indicates the SCIF status. However, 1 cannot be written to the ORER, TSF, ER, TDFE, BRK, RDF, and DR flags. Also note that in order to clear these flags to 0, they must be read as 1 beforehand. The TEND, FER, and PER flags are read-only flags and cannot be modified.
Page 437 Initial Name Value Description R/(W) * Transmit Data Stop Indicates that the number of transmit data matches the value of SCTDSR. 0: Number of transmit data does not match the value of SCTDSR [Clearing conditions] • Power-on reset or manual reset •...
Page 438 Initial Name Value Description TEND Transmit End Indicates that there is no valid data in SCFTDR when the last bit of the transmit character is sent, and transmission has been ended. 0: Transmission is in progress [Clearing condition] When data is written to SCFTDR 1: Transmission has been ended [Setting condition] When there is no transmit data in SCFTDR on transmission...
Page 439 Initial Name Value Description R/(W) * Break Detect Indicates that a receive data break signal has been detected in asynchronous mode. 0: A break signal has not been received [Clearing conditions] • Power-on reset or manual reset • When 0 is written to BRK after reading BRK = 1 1: A break signal has been received * [Setting condition] When data with a framing error is received, followed by the...
Page 440 Initial Name Value Description Parity Error Indicates a parity error in the data read from SCFRDR in asynchronous mode. 0: There is no parity error in the receive data read from SCFRDR [Clearing conditions] • Power-on reset or manual reset •...
Page 441: Bit Rate Register (Scbrr)
Initial Name Value Description R/(W) * Receive Data Ready Indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR and no further data will arrive in asynchronous mode. 0: Reception is in progress or has ended successfully and there is no receive data left in SCFRDR [Clearing conditions] •...
Page 442 Asynchronous Mode: 1. When sampling rate is 1/16 Pφ × 10 32 × 2 2n-1 × B 2. When sampling rate is 1/5 Pφ × 10 2n-1 10 × 2 × B 3. When sampling rate is 1/11 Pφ × 10 22 ×...
Page 443 The bit rate error in asynchronous mode is found from the following equation: 1. When sampling rate is 1/16 Pφ × 10 - 1 × 100 Error (%) = (1+N) × B × 32 × 2 2n-1 2. When sampling rate is 1/5 Pφ...
Page 444: Fifo Control Register (Scfcr)
16.3.10 FIFO Control Register (SCFCR) SCFCR is a 16-bit readable/writable register that resets the data count and sets the trigger data number for the transmit and receive FIFO registers, and also contains a loopback test enable bit. Initial Name Value Description Transmit Data Stop Enable Enables or disables the transmit data stop function.
Page 445 Initial Name Value Description RTRG1 Receive FIFO Data Number Trigger RTRG0 Set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status register (SCSSR). The RDF flag is set when the number of receive data bytes in SCFRDR is equal to or greater than the trigger set number shown in below.
Page 446 Initial Name Value Description TFRST Transmit FIFO Data Register Reset Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. 0: Reset operation disabled * 1: Reset operation enabled Note:* A reset operation is performed in the event of a power-on reset or manual reset.
Page 447: Fifo Data Count Register (Scfdr)
16.3.11 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit read-only register that indicates the number of data bytes stored in the transmit FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR). Bits 14 to 8 show the number of transmit data bytes in SCFTDR, and bits 6 to 0 show the number of receive data bytes in SCFRDR.
Page 448: Operation
16.4 Operation 16.4.1 Overview The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character, and in clock synchronous mode, in which synchronization is achieved with clock pulses. 64-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed.
Page 449: Table 16.2 Scsmr Settings For Serial Transfer Format Selection
Table 16.2 SCSMR Settings for Serial Transfer Format Selection SCSMR Settings SCIF Transfer Format Bit 6: Bit 5: Bit 3: Data Multiprocessor Parity Stop Bit STOP Mode Length Length Asynchronous mode 8-bit data None 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit...
Page 450: Serial Operation In Asynchronous Mode
16.4.3 Serial Operation in Asynchronous Mode 1. Data Transfer Format Table 16.3 shows the transfer formats that can be used in asynchronous mode. Any of eight transfer formats can be selected according to the SCSMR settings. Table 16.3 Serial Transfer Formats SCSMR Settings Serial Transfer Format and Frame Length STOP...
Page 451 2. Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the serial clock for the SCIF, according to the setting of the CKE1 and CKE0 bits in SCSCR. When an external clock is input at the SCK pin, a clock must be input according to the sampling rate.
Page 452: Figure 16.2 Sample Scif Initialization Flowchart
Figure 16.2 shows a sample SCIF initialization flowchart. Initialization Clear TE and RE bits in SCSCR to 0 [1] Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, TE, and RE to 0. [2] Set the transmit and receive format in SCSMR. Set TFRST and RFRST bits in SCFCR to 1 [3] Write a value corresponding to the bit rate into...
Page 453: Figure 16.3 Sample Serial Transmission Flowchart
b. Serial Data Transmission Figure 16.3 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start of transmission [1] SCIF status check and transmit data write: Read TDFE bit in SCSSR Read the serial status register (SCSSR) and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, read 1 from the TDFE...
Page 454 In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in the serial status register (SCSSR) is set to 1 before writing transmit data to SCFTDR.
Page 455: Figure 16.4 Example Of Transmit Operation (Example With 8-Bit Data, Parity, One Stop Bit)
Figure 16.4 shows an example of the operation for transmission in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Serial Idle state data (mark state) TDFE TEND TXI interrupt Data written to SCFTDR TXI interrupt request and TDFE flag read as request 1 and then cleared to 0 by TXI interrupt handler...
Page 456: Figure 16.6 Transmit Data Stop Function Flowchart
Figure 16.6 shows a flowchart for the transmit data stop function. Start of transmission [1] Set the transmit data stop number in SCTDSR, then set the TSE bit in SCFCR to 1.When an interrupt is enabled, Set transmit data stop also set the TSIE bit to 1.
Page 457: Figure 16.7 Sample Serial Reception Flowchart (1)
c. Serial Data Reception Figures 16.7 and 16.8 show sample flowcharts for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. [1] Receive error handling and break detection: Start of reception Read the DR, ER, and BRK flags in SCSSR to identify any error, perform the appropriate error handling, then clear the DR, ER, and BRK flags to 0.
Page 458: Figure 16.8 Sample Serial Reception Flowchart (2)
Error handling ER = 1? [1] Whether a framing error or parity error has Receive error handling occurred in the receive data read from SCFRDR can be ascertained from the FER and PER bits in SCSSR. [2] When a break signal is received, receive data is not transferred to SCFRDR while the BRK BRK = 1? flag is set.
Page 459 In serial reception, the SCIF operates as described below. 1. The SCIF monitors the communication line, and if 0 of a start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3.
Page 460: Figure 16.9 Example Of Scif Receive Operation (Example With 8-Bit Data, Parity, One Stop Bit)
Figure 16.9 shows an example of the operation for reception in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Serial Idle state data (mark state) Data read and RDF flag RXI interrupt ERI interrupt request read as 1 then cleared request generated by receive to 0 by RXI interrupt...
Page 461: Clock Synchronous Mode
When using a modem function and the receive FIFO (SCFRDR) is at least the number of the R T S output trigger, the signal goes high. R T S Figure 16.11 shows an example of operation for the control. R T S Start Parity Stop...
Page 462: Serial Operation In Clock Synchronous Mode
16.4.5 Serial Operation in Clock Synchronous Mode One unit of transfer data (character or frame) Serial clock Don't care Don't care Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Note: * High except in continuous transmission/reception Figure 16.12 Data Format in Clock Synchronous Communication In clock synchronous serial communication, data on the communication line is output from a falling edge of the serial clock to the next falling edge.
Page 463 When the clock source, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the transmit shift register (SCTSR) is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCSSR, SCFTDR, or SCFRDR.
Page 464: Figure 16.13 Sample Scif Initialization Flowchart (1) (Transmission)
Figure 16.13 shows sample SCIF initialization flowcharts. Initialization [1] Be sure to set the TFRST bit in Clear TE and RE bits in SCSCR to 0 SCFCR to 1, to reset the FIFOs. [2] Set the clock selection in SCSCR. Set TFRST bit in SCFCR to 1 Be sure to clear bits RIE, TIE, TE, and RE to 0.
Page 465: Figure 16.13 Sample Scif Initialization Flowchart (2) (Reception)
Initialization [1] Be sure to set the RFRST bit in Clear TE and RE bits in SCSCR to 0 SCFCR to 1, to reset the FIFOs. [2] Set the clock selection in SCSCR. Set RFRST bit in SCFCR to 1 Be sure to clear bits RIE, TIE, TE, and RE to 0.
Page 466: Figure 16.13 Sample Scif Initialization Flowchart (3) (Simultaneous Transmission And Reception)
Initialization Clear TE and RE bits in SCSCR to 0 [1] Be sure to set the TFRST bit in SCFCR to 1, to reset the FIFOs. Set TFRST and RFRST bits in SCFCR to 1 [2] Set the clock selection in SCSCR. Be sure to clear bits RIE, TIE, TE, and RE to 0.
Page 467: Figure 16.14 Sample Serial Transmission Flowchart (1) (First Transmission After Initialization)
b. Serial Data Transmission: Figure 16.14 shows sample flowcharts for serial transmission. Start of transmission [1] Write the remaining transmit Write remaining transmit data to SCFTDR data to SCFTDR. [2] Transmission is started when the TE bit in SCSCR is set to 1. Set TE bit in SCSCR When using transmit FIFO data interrupt, [3] After the end of transmission,...
Page 468: Figure 16.15 Sample Serial Reception Flowchart (1) (First Reception After Initialization)
c. Serial Data Reception Figure 16.15 shows sample flowcharts for serial reception. Start of reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR [1] Set the receive trigger number in SCFCR. Set RE bit in SCSCR [2] Reception is started when the When using receive FIFO data interrupt, RE bit in SCSCR is set to 1.
Page 469: Figure 16.15 Sample Serial Reception Flowchart (2) (Second And Subsequent Reception)
Start of reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR [1] Set the receive trigger number in SCFCR. Set RFRST bit in SCFCR to 1 [2] Reset the receive FIFO. [3] Wait for one bit interval. Clear RFRST bit in SCFCR to 0 Wait [4] Reception is started when the RE bit in SCSCR is set to 1.
Page 470: Figure 16.16 Sample Simultaneous Serial Transmission And Reception Flowchart (2) (Second And Subsequent Transfer)
d. Simultaneous Serial Data Transmission and Reception Figure 16.16 shows sample flowcharts for simultaneous serial transmission and reception. Start of simultaneous transmission/reception Set receive trigger number in RTRG1 and RTRG0 in SCFCR [1] Set the receive trigger number in SCFCR. Write remaining transmit data to SCFTDR [2] Write the remaining transmit data to SCFTDR, and if there is receive...
Page 471: Figure 16.16 Sample Simultaneous Serial Transmission And Reception Flowchart (1) (First Transfer After Initialization)
Start of simultaneous transmission/reception Set receive trigger number in RTRG1 [1] Set the receive trigger number and and RTRG0 in SCFCR, and set transmit transmit trigger number in SCFCR. trigger number in TTRG1 and TTRG0 [2] Reset the receive FIFO and transmit Set TFRST and RFRST bits in FIFO.
Page 472: Scif Interrupt Sources And Dmac
16.5 SCIF Interrupt Sources and DMAC The SCIF supports six interrupts in asynchronous mode—transmit-FIFO-data-empty (TXI), transmit-data-stop (TDI), receive-error (ERI), receive-FIFO-data-full (RXI), break-receive (BRI), and receive-data-ready (DRI). The vectors of transmit-data-stop and transmit-FIFO-data-empty interrupts are the same. The vectors of receive-error and break-receive interrupts are the same. The vectors of receive-FIFO-data-full and receive-data-ready interrupts are the same.
Page 473: Table 16.4 Scif Interrupt Sources
Table 16.4 SCIF Interrupt Sources Interrupt Source Description DMAC Activation Not possible Interrupt initiated by receive error flag (ER) or break flag (BRK) Possible * Interrupt initiated by receive FIFO data full flag (RDF) or receive data ready (DR) Possible * Interrupt initiated by transmit FIFO data empty flag (TDFE) or transmit data stop flag (TSF) Notes: 1.
Page 474: Notes On Usage
16.6 Notes on Usage Note the following when using the SCIF. a. SCFTDR Writing and the TDFE Flag: The TDFE flag in the serial status register (SCSSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR).
Page 475 d. Receive Data Sampling Timing and Receive Margin: As an example, when the sampling rate is 1/16, the SCIF operates on a base clock with a frequency of 8 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock.
Page 476 Rev. 2.00, 09/03, page 430 of 690...
Page 477: Section 17 Infrared Data Association Module (Irda)
Section 17 Infrared Data Association Module (IrDA) This LSI has an on-chip Infrared Data Association (IrDA) interface that is based on the IrDA 1.0 system and can perform infrared communication. The IrDA is an optional module used for modulation and demodulation of signals for the SCIF module, and it must always be used together with the SCIF module.
Page 478: Input/Output Pins
17.2 Input/Output Pins Table 17.1 shows the IrDA pin configuration. Table 17.1 Pin Configuration Pin Name Signal Name Function Receive data pin IrRx Input Receive data input Transmit data pin IrTx Output Transmit data output Note: Clock input from the serial clock pin cannot be set in IrDA mode. 17.3 Register Description The IrDA has the following internal registers.
Page 479 Bit Name Initial Value Description  15 to 8 Reserved These bits are always read as 0. The write value should always be 0. IRMOD IrDA Mode Selects whether this module operates as an IrDA serial communication interface or as an SCIF.
Page 480: Operation
17.4 Operation The IrDA module can perform infrared communication conforming to IrDA 1.0 by connecting infrared transmit/receive units. The serial communication interface unit includes a buffer in the transmit unit and the receive unit, allowing CPU overhead to be reduced and continuous high- speed communication to be performed.
Page 481: Receiving
17.4.3 Receiving Received 3/16 IR frame bit-width pulses are demodulated and converted to a UART frame, as shown in figure 17.2. Demodulation to 0 is performed for pulse output, and demodulation to 1 is performed for no pulse output. UART frame UART frame Start bit Stop bit...
Page 482 Rev. 2.00, 09/03, page 436 of 690...
Page 483: Section 18 Usb Function Module
Section 18 USB Function Module This LSI incorporates a USB function module (USB). 18.1 Features • The UDC (USB device controller) conforming to USB2.0 and transceiver process USB protocol automatically. Automatic processing of USB standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) •...
Page 484: Figure 18.1 Block Diagram Of Usb
Figure 18.1 shows the block diagram of the USB. Peripheral bus USB function module Interrupt requests Status and DMA transfer requests control registers Transceiver FIFO Clock (48 MHz) Legend: UDC: USB device controller Figure 18.1 Block Diagram of USB Rev. 2.00, 09/03, page 438 of 690...
Page 485: Input/Output Pins
18.2 Input/Output Pins Table 18.1 shows the USB pin configuration. Table 18.1 Pin Configuration XVEROFF Pin Name Function Condition XVDATA Input Input pin for receive data from differential receiver 1 DPLS Input Input pin to driver for D+ signal from receiver DMNS Input Input pin to driver for D–...
Page 486: Register Descriptions
18.3 Register Descriptions The USB has following registers. For the information on the addresses of these registers and the state of the register in each processing condition, see section 24, List of Registers. • Interrupt flag register 0 (IFR0) • Interrupt flag register 1 (IFR1) •...
Page 487: Interrupt Flag Register 0 (Ifr0)
18.3.1 Interrupt Flag Register 0 (IFR0) IFR0, together with interrupt flag register 1 (IFR1), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1 and an interrupt request is sent to the CPU according to the combination with interrupt enable register 0 (IER0).
Page 488: Interrupt Flag Register 1 (Ifr1)
Initial Bit Name Value Description EP0iTR EP0i Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 0 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
Page 489: Interrupt Select Register 0 (Isr0)
18.3.3 Interrupt Select Register 0 (ISR0) ISR0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0 (IFR0). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the interrupt corresponding to the bit will be USI0 (USB interrupt 0).
Page 490: Interrupt Enable Register 0 (Ier0)
18.3.5 Interrupt Enable Register 0 (IER0) IER0 enables the interrupt requests of interrupt flag register 0 (IFR0). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU.
Page 491: Ep0I Data Register (Epdr0I)
18.3.7 EP0i Data Register (EPDR0i) EPDR0i is an 8-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in the trigger register. When an ACK handshake is returned from the host after the data has been transmitted, EP0iTS in interrupt flag register 0 is set.
Page 492: Ep1 Data Register (Epdr1)
18.3.10 EP1 Data Register (EPDR1) EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When one packet of data is received successfully, EP1FULL in interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP1 receive data size register.
Page 493: Ep0O Receive Data Size Register (Epsz0O)
18.3.13 EP0o Receive Data Size Register (EPSZ0o) EPSZ0o indicates the number of bytes received at endpoint 0 from the host. Bit Name Initial Value Description 7 to 0 — Number of receive data for endpoint 0 18.3.14 EP1 Receive Data Size Register (EPSZ1) EPSZ1 is a receive data size resister for endpoint 1.
Page 494: Trigger Register (Trg)
18.3.15 Trigger Register (TRG) TRG generates one-shot triggers to control the transfer sequence for each endpoint. Bit Name Initial Value Description   Undefined Reserved The write value should always be 0. EP3PKTE Undefined EP3 Packet Enable After one packet of data has been written to the endpoint 3 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit.
Page 495: Data Status Register (Dasts)
18.3.16 Data Status Register (DASTS) DASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set when data is written to the corresponding FIFO buffer and the packet enable state is set, and cleared when all data has been transmitted to the host. Bit Name Initial Value Description...
Page 496: Dma Transfer Setting Register (Dmar)
Bit Name Initial Value Description EP2CLR Undefined EP2 Clear Writing 1 to this bit initializes both sides of the endpoint 2 transmit FIFO buffer.   3, 2 Undefined Reserved The write value should always be 0. EP0oCLR Undefined EP0o Clear Writing 1 to this bit initializes the endpoint 0 receive FIFO buffer.
Page 497 Bit Name Initial Value R/W Description EP2DMAE R/W Endpoint 2 DMA Transfer Enable When this bit is set, DMA transfer is enabled from memory to the endpoint 2 transmit FIFO buffer. If there is at least one byte of space in the FIFO buffer, a transfer request is asserted for the DMAC.
Page 498 Bit Name Initial Value R/W Description EP1DMAE R/W Endpoint 1 DMA Transfer Enable When this bit is set, DMA transfer is enabled from the endpoint 1 receive FIFO buffer to memory. If there is at least one byte of receive data in the FIFO buffer, a transfer request is asserted for the DMAC.
Page 499: Endpoint Stall Register (Epstl)
18.3.19 Endpoint Stall Register (EPSTL) The bits in EPSTL are used to forcibly stall the endpoints on the application side. While a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0 is cleared automatically on reception of 8-byte command data for which decoding is performed by the function and the EP0 STL bit is cleared.
Page 500: Operation
18.4 Operation 18.4.1 Cable Connection USB function Application Cable disconnected USB module interrupt VBUS pin = 0 V setting UDC core reset Initial settings As soon as preparations are completed, enable D+ pull-up USB cable connection in general output port General output port D+ pull-up enabled? Interrupt request...
Page 501: Cable Disconnection
18.4.2 Cable Disconnection USB function Application Cable connected VBUS pin = 1 USB cable disconnection VBUS pin = 0 UDC core reset Figure 18.3 Cable Disconnection Operation The above flowchart shows the operation in section 18.8, Example of USB External Circuitry. 18.4.3 Control Transfer Control transfer consists of three stages: setup, data (not always included), and status (figure 18.4).
Page 502: Figure 18.5 Setup Stage Operation
1. Setup Stage Application USB function SETUP token reception Receive 8-byte command data in EP0s Command Automatic to be processed by processing by application? this module Clear SETUP TS flag Set setup command Interrupt request (IFR0.SETUP TS = 0) reception complete flag Clear EP0i FIFO (CLR.EP0iCLR = 1) (IFR0.SETUP TS = 1) Clear EP0o FIFO (CLR.EP0oCLR = 1)
Page 503: Figure 18.6 Data Stage (Control-In) Operation
2. Data Stage (Control-In) USB function Application IN token reception From setup stage Write data to EP0i 1 written data register (EPDR0i) to TRG.EP0s NACK RDFN? Write 1 to EP0i packet enable bit (TRG.EP0i PKTE = 1) Valid data in EP0i FIFO? NACK Data transmission to host Set EP0i transmission...
Page 504: Figure 18.7 Data Stage (Control-Out) Operation
3. Data Stage (Control-Out) USB function Application OUT token reception 1 written to TRG.EP0s RDFN? NACK Data reception from host Clear EP0o reception Set EP0o reception Interrupt request complete flag complete flag (IFR0.EP0o TS = 1) (IFR0.EP0o TS = 0) Read data from EP0o OUT token reception receive data size register...
Page 505: Figure 18.8 Status Stage (Control-In) Operation
4. Status Stage (Control-In) USB function Application OUT token reception 0-byte reception from host Set EP0o reception Clear EP0o reception Interrupt request complete flag complete flag (IFR0.EP0o TS = 1) (IFR0.EP0o TS = 0) Write 1 to EP0o read End of control transfer complete bit (TRG.EP0o RDFN = 1) End of control transfer...
Page 506: Figure 18.9 Status Stage (Control-Out) Operation
5. Status Stage (Control-Out) USB function Application IN token reception Clear EP0i transfer Interrupt request Valid data request flag in EP0i FIFO? NACK (IFR0.EP0i TR = 0) Write 1 to EP0i packet 0-byte transmission to host enable bit (TRG.EP0i PKTE = 1) Set EP0i transmission Clear EP0i transmission Interrupt request...
Page 507: Ep1 Bulk-Out Transfer (Dual Fifos)
18.4.4 EP1 Bulk-Out Transfer (Dual FIFOs) USB function Application OUT token reception Space in EP1 FIFO? NACK Data reception from host Interrupt request Set EP1 FIFO full status Read EP1 receive data (IFR0.EP1 FULL = 1) size register (EPSZ1) Read data from EP1 data register (EPDR1) Write 1 to EP1 read complete bit...
Page 508: Ep2 Bulk-In Transfer (Dual Fifos)
18.4.5 EP2 Bulk-In Transfer (Dual FIFOs) USB function Application IN token reception Clear EP2 transfer Interrupt request Valid data request flag in EP2 FIFO? (IFR0.EP2 TR = 0) NACK Enable EP2 FIFO Data transmission to host empty interrupt (IER0.EP2 EMPTY = 1) Interrupt Set EP2 request...
Page 509: Ep3 Interrupt-In Transfer
data transmission is completed, the FIFO used in the data transmission becomes empty. If the other FIFO contains valid transmit data at this time, transmission can be continued. When transmission of all data has been completed, write 0 to the EP2EMPTY bit in IER0 and disable interrupt requests.
Page 510: Processing Of Usb Standard Commands And Class/Vendor Commands
18.5 Processing of USB Standard Commands and Class/Vendor Commands 18.5.1 Processing of Commands Transmitted by Control Transfer A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 18.2 below.
Page 511: Stall Operations
18.6 Stall Operations 18.6.1 Overview This section describes stall operations in this module. There are two cases in which the USB function module stall function is used: • When the application forcibly stalls an endpoint for some reason • When a stall is performed automatically within the USB function module due to a USB specification violation The USB function module has internal status bits that hold the status (stall or non-stall) of each endpoint.
Page 512: Figure 18.13 Forcible Stall By Application
(1) Transition from normal operation to stall (1-1) 1. 1 written to EPSTL Internal status bit EPSTL by application 0 → 1 (1-2) Reference 1. IN/OUT token Transaction request received from host EPSTL Internal status bit 2. EPSTL referenced (1-3) 1.
Page 513: Automatic Stall By Usb Function Module
18.6.3 Automatic Stall by USB Function Module When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to the EPSTL register, and returns a stall handshake (1-1 in figure 18.14).
Page 514: Dma Transfer
18.7 DMA Transfer 18.7.1 Overview DMA transfer can be performed for endpoints 1 and 2 in this module. Note that word or longword data cannot be transferred. When endpoint 1 holds at least one byte of valid receive data, a DMA request for endpoint 1 is generated.
Page 515: Dma Transfer For Endpoint 2
18.7.3 DMA Transfer for Endpoint 2 When the transmit data at EP2 is transferred by the DMAC, the USB function module automatically performs the same processing as writing 1 to the PKTE bit in TRG if the currently selected FIFO (64 bytes) becomes full. Accordingly, to transfer data of a multiple of 64 bytes, the user need not write 1 to the PKTE bit.
Page 516: Example Of Usb External Circuitry
18.8 Example of USB External Circuitry 1. USB Transceiver A USB transceiver IC (such as a PDIUSBP11) should be connected externally when no internal transceiver is used. The USB transceiver manufacturer should be consulted concerning the recommended circuit from the USB transceiver to the USB connector, etc. 2.
Page 517: Figure 18.17 Example Of Usb Function Module External Circuitry (Internal Transceiver)
This LSI General output port, etc. IC allowing voltage application when system (LSI) power is off USB module VBUS connector IC allowing voltage EXTAL_USB application when system (LSI) power is off 48 MHz VBUS cable Note: Operation is not guaranteed with this sample circuit. If external surge and ESD noise countermeasures are required for the system, a protective diode or the noise canceler should be used for this purpose.
Page 518: Figure 18.18 Example Of Usb Function Module External Circuitry (External Transceiver)
This LSI General output port, etc. IC allowing voltage application when system (LSI) power is off USB module VBUS connector IC allowing voltage application when system (LSI) power is off VBUS EXTAL_USB 48 MHz SPEED TXENL TXDMNS TXDPLS XVDATA cable DPLS DMNS SUSPND...
Page 519: Usage Notes
18.9 Usage Notes 18.9.1 Receiving Setup Data Note the following for EPDR0s that receives 8-byte setup data: 1. As a latest setup command must be received in high priority, the write from the USB bus takes priority over the read from the CPU. If the next setup command reception is started while the CPU is reading data after the data is received, the read from the CPU is forcibly terminated.
Page 520: Assigning Interrupt Sources To Ep0
18.9.4 Assigning Interrupt Sources to EP0 The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations. 18.9.5 Clearing the FIFO when DMA Transfer Is Enabled The endpoint 1 data register (EPDR1) cannot be cleared when DMA transfer for endpoint 1 is enabled (EP1 DMAE in DMAR = 1).
Page 521: Section 19 Pin Function Controller
Section 19 Pin Function Controller 19.1 Overview The pin function controller (PFC) consists of registers to select the pin functions and I/O directions of multiplex pins. Pin functions and I/O directions can be individually selected for every pin regardless of the LSI operating mode. Table 19.1 lists the multiplex pins of this LSI. Table 19.1 Multiplex Pins Port Port Function (Related Module)
Page 522 Port Port Function (Related Module) Other Functions (Related Module) PTD7 input/output (port) output (BSC) C S 6 B PTD6 input/output (port) output (BSC) C S 5 B NF * PTD5 input (port) PTD4 input/output (port) CKE output (BSC) PTD3 input/output (port) output (BSC) C A S U PTD2 input/output (port)
Page 523 Port Port Function (Related Module) Other Functions (Related Module) PTH6 input/output (port) DREQ1 input (DMAC) PTH5 input/output (port) DREQ0 input (DMAC) PTH4 input/output (port) IRQ4 input (INTC) PTH3 input/output (port) IRQ3 input (INTC)/ input (INTC) I R L 3 PTH2 input/output (port) IRQ2 input (INTC)/ input (INTC) I R L 2...
Page 524 Port Port Function (Related Module) Other Functions (Related Module)  PTN7 input/output (port) PTN6 input/output (port) DPLS input (USB) PTN5 input/output (port) DMNS input (USB) PTN4 input/output (port) TXDPLS output (USB) PTN3 input/output (port) TXDMNS output (USB) PTN2 input/output (port) XVDATA input (USB) PTN1 input/output (port) TXENL output (USB)
Page 525: Register Descriptions
19.2 Register Descriptions The PFC has the following registers. For details on register addresses and access sizes, see section 24, List of Registers. • Port A control register (PACR) • Port B control register (PBCR) • Port C control register (PCCR) •...
Page 526: Port A Control Register (Pacr)
19.2.1 Port A Control Register (PACR) PACR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Initial Name Value Description PA7MD1 PTA7 Mode PA7MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PA6MD1 PTA6 Mode...
Page 527: Port B Control Register (Pbcr)
Initial Name Value Description PA2MD1 PTA2 Mode PA2MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PA1MD1 PTA1 Mode PA1MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PA0MD1...
Page 528 Initial Name Value Description PB5MD1 PTB5 Mode PB5MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PB4MD1 PTB4 Mode PB4MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PB3MD1...
Page 529: Port C Control Register (Pccr)
19.2.3 Port C Control Register (PCCR) PCCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Initial Name Value Description PC7MD1 PTC7 Mode PC7MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PC6MD1 PTC6 Mode...
Page 530 Initial Name Value Description PC2MD1 PTC2 Mode PC2MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PC1MD1 PTC1 Mode PC1MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PC0MD1...
Page 531: Port D Control Register (Pdcr)
19.2.4 Port D Control Register (PDCR) PDCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Initial Name Value Description PD7MD1 PTD7 Mode PD7MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PD6MD1 PTD6 Mode...
Page 532 Initial Name Value Description PD2MD1 PTD2 Mode PD2MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PD1MD1 PTD1 Mode PD1MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PD0MD1...
Page 533: Port E Control Register (Pecr)
19.2.5 Port E Control Register (PECR) PECR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Initial Name Value Description PE7MD1 PTE7 Mode PE7MD0 00: Setting prohibited 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PE6MD1 PTE6 Mode...
Page 534: Port E Control Register 2 (Pecr2)
Initial Name Value Description PE1MD1 PTE1 Mode PE1MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PE0MD1 PTE0 Mode PE0MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 19.2.6...
Page 535: Port F Control Register (Pfcr)
19.2.7 Port F Control Register (PFCR) PFCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Initial Name Value Description PF7MD1 PTF7 Mode 00: Other functions * PF7MD0 (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PF6MD1...
Page 536: Port F Control Register 2 (Pfcr2)
Initial Name Value Description PF1MD1 PTF1 Mode PF1MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PF0MD1 PTF0 Mode PF0MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Notes: 1.
Page 537: Port G Control Register
Initial Name Value Description PF1MD2 PTF1 Mode 2 This bit is valid when the PF1MD[1:0] bits in PFCR are set to B'00 (other functions). 0: AUDATA1 (AUD) 1: TO1 (TPU) PF0MD2 PTF0 Mode 2 This bit is valid when the PF0MD[1:0] bits in PFCR are set to B'00 (other functions).
Page 538 Initial Name Value Description PG4MD1 PTG4 Mode PG4MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PG3MD1 PTG3 Mode 00: Other functions * PG3MD0 (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off)
Page 539: Port H Control Register (Phcr)
19.2.10 Port H Control Register (PHCR) PHCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Initial Name Value Description 15, 14 — Reserved These bits are always read as 0. The write value should always be 0.
Page 540: Port J Control Register (Pjcr)
Initial Name Value Description PH1MD1 PTH1 Mode PH1MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PH0MD1 PTH0 Mode PH0MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 19.2.11 Port J Control Register (PJCR)
Page 541 Initial Name Value Description PJ4MD1 PTJ4 Mode PJ4MD0 00: NF 01: Port output 10: Setting prohibited 11: Setting prohibited PJ3MD1 PTJ3 Mode PJ3MD0 00: NF 01: Port output 10: Setting prohibited 11: Setting prohibited PJ2MD1 PTJ2 Mode PJ2MD0 00: NF 01: Port output 10: Setting prohibited 11: Setting prohibited...
Page 542: Port K Control Register (Pkcr)
19.2.12 Port K Control Register (PKCR) PKCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Initial Name Value Description PK7MD1 PTK7 Mode PK7MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PK6MD1 PTK6 Mode...
Page 543 Initial Name Value Description PK1MD1 PTK1 Mode PK1MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PK0MD1 PTK0 Mode PK0MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) Rev.
Page 544: Port L Control Register (Plcr)
19.2.13 Port L Control Register (PLCR) PLCR is a 16-bit readable/writable register that selects the pin function. Initial Name Value Description 15 to 8 — Reserved These bits are always read as 0. The write value should always be 0. PL3MD1 PTL3 Mode PL3MD0...
Page 545: Port M Control Register (Pmcr)
19.2.14 Port M Control Register (PMCR) PMCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control. Initial Name Value Description 15, 14 — Reserved These bits are always read as 0. The write value should always be 0.
Page 546: Port N Control Register (Pncr)
Initial Name Value Description PM1MD1 PTM1 Mode PM1MD0 00: Setting prohibited 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PM0MD1 PTM0 Mode PM0MD0 00: Setting prohibited 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) 19.2.15 Port N Control Register (PNCR) PNCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS...
Page 547 Initial Name Value Description PN4MD1 PTN4 Mode PN4MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PN3MD1 PTN3 Mode PN3MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) PN2MD1...
Page 548: Port N Control Register 2 (Pncr2)
19.2.16 Port N Control Register 2 (PNCR2) PNCR2 is an 8-bit readable/writable register that selects the pin function. Initial Name Value Description — Reserved This bit is always read as 0. The write value should always be 0. PN6MD2 PTN6 Mode 2 This bit is valid when the PN6MD[1:0] bits in PNCR are set to B'00 (other functions).
Page 549: Port Sc Control Register (Scpcr)
Initial Name Value Description PN1MD2 PTN1 Mode 2 This bit is valid when the PN1MD[1:0] bits in PNCR are set to B'00 (other functions). 0: Setting prohibited 1: TXENL (USB) PN0MD2 PTN0 Mode 2 This bit is valid when the PN0MD[1:0] bits in PNCR are set to B'00 (other functions).
Page 550 Initial Name Value Description SCP4MD1 SCPT4 Mode SCP4MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) SCP3MD1 SCPT3 Mode SCP3MD0 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) SCP2MD1...
Page 551 Initial Name Value Description SCP1MD1 SCPT1 Mode SCP1MD0 These bits select pin function and input pull-up MOS control. 00: Other functions (see table 19.1) 01: Port output 10: Port input (pull-up MOS: On) 11: Port input (pull-up MOS: Off) SCP0MD1 SCPT0 Mode SCP0MD0 These bits select pin function and input pull-up MOS...
Page 552 Rev. 2.00, 09/03, page 506 of 690...
Page 553: Section 20 I/O Ports
Section 20 I/O Ports This LSI has fourteen I/O ports (ports A to H, J to N, and SC). All port pins are multiplexed with other pin functions (the pin function controller (PFC) handles the selection of pin functions and pull-up MOS control).
Page 554: Port A Data Register (Padr)
20.1.2 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT to PA0DT correspond to pins PTA7 to PTA0. When the pin function is general output port, if the port is read, the value of the corresponding PADR bit is returned directly.
Page 555: Register Description
20.2.1 Register Description Port B has the following register. For details on the register address and access size, see section 24, List of Registers. • Port B data register (PBDR) 20.2.2 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores data for pins PTB7 to PTB0. Bits PB7DT to PB0DT correspond to pins PTB7 to PTB0.
Page 556: Port C
20.3 Port C Port C is an 8-bit input/output port with the pin configuration shown in figure 20.3. Each pin has an input pull-up MOS, which is controlled by the port C control register (PCCR) in the PFC. PTC7 (input/output)/CS6A (output) PTC6 (input/output)/CS5A (output) PTC5 (input/output)/CS4 (output) PTC4 (input/output)/CS3 (output)
Page 557: Port D
Table 20.3 Port C Data Register (PCDR) Read/Write Operations PCCR State PCnMD1 PCnMD0 Pin State Read Write Other function PCDR value Data can be written to PCDR but no effect on pin state. Output PCDR value Written data is output from the pin. Input (Pull-up Pin state Data can be written to PCDR but no effect on...
Page 558: Table 20.4 Port D Data Register (Pddr) Read/Write Operations
Initial Name Value Description 7 to PD7DT Table 20.4 shows the function of PDDR. PD0DT Table 20.4 Port D Data Register (PDDR) Read/Write Operations PDCR State PDnMD1 PDnMD0 Pin State Read Write Other function PDDR value Data can be written to PDDR but no effect on pin state.
Page 559: Port E
20.5 Port E Port E is an 8-bit input/output port with the pin configuration shown in figure 20.5. Each pin has an input pull-up MOS, which is controlled by the port E control register (PECR) in the PFC. PTE7 (input/output) PTE6 (input/output)/TCLK (input) PTE5 (input/output)/STATUS1 (output)/CTS0 (input) PTE4 (input/output)/STATUS0 (output)/RTS0 (output)
Page 560: Port F
Table 20.5 Port E Data Register (PEDR) Read/Write Operations PECR State PEnMD1 PEnMD0 Pin State Read Write Other function PEDR value Data can be written to PEDR but no effect on pin state. Output PEDR value Written data is output from the pin. Input (Pull-up Pin state Data can be written to PEDR but no effect on...
Page 561: Port G
Initial Name Value Description 7 to PF7DT Table 20.6 shows the function of PFDR. PF0DT Table 20.6 Port F Data Register (PFDR) Read/Write Operations PFCR State PFnMD1 PFnMD0 Pin State Read Write Other function PFDR value Data can be written to PFDR but no effect on pin state.
Page 562: Port G Data Register
20.7.2 Port G Data Register (PGDR) PGDR is an 8-bit readable/writable register that stores data for pins PTG7 to PTG0. Bits PG7DT to PG0DT correspond to pins PTG7 to PTG0. When the pin function is general output port, if the port is read, the value of the corresponding PGDR bit is returned directly.
Page 563: Register Description
20.8.1 Register Description Port H has the following register. For details on the register address and access size, see section 24, List of Registers. • Port H data register (PHDR) 20.8.2 Port H Data Register (PHDR) PHDR is an 8-bit readable/writable register that stores data for pins PTH6 to PTH0. Bits PH6DT to PH0DT correspond to pins PTH6 to PTH0.
Page 564: Port J
20.9 Port J Port J is an 8-bit output port with the pin configuration shown in figure 20.9. PTJ7 (output)/NF (output) PTJ6 (output)/NF (output) PTJ5 (output)/NF (output) PTJ4 (output)/NF (output) Port J PTJ3 (output)/NF (output) PTJ2 (output)/NF (output) PTJ1 (output)/NF (output) PTJ0 (output)/NF (output) Figure 20.9 Port J 20.9.1...
Page 565: Port K
Table 20.9 Port J Data Register (PJDR) Read/Write Operations PJCR State PJnMD1 PJnMD0 Pin State Read Write PJDR value Data can be written to PJDR but no effect on pin state. Output PJDR value Written data is output from the pin. ...
Page 566: Port L
Initial Name Value Description 7 to 0 PK7DT Table 20.10 shows the function of PKDR. PK0DT Table 20.10 Port K Data Register (PKDR) Read/Write Operations PKCR State PKnMD1 PKnMD0 Pin State Read Write Other function PKDR value Data can be written to PKDR but no effect on pin state.
Page 567: Port L Data Register (Pldr)
20.11.2 Port L Data Register (PLDR) PLDR is an 8-bit read-only register that stores data for pins PTL3 to PTL0. Bits PL3DT to PL0DT correspond to pins PTL3 to PTL0. If the port is read, the corresponding pin level is read. Initial Name Value...
Page 568: 20.12.1 Register Description
20.12.1 Register Description Port M has the following register. For details on the register address and access size, see section 24, List of Registers. • Port M data register (PMDR) 20.12.2 Port M Data Register (PMDR) PMDR is an 8-bit readable/writable register that stores data for pins PTM6 and PTM4 to PTM0. Bits PM6DT and PM4DT to PM0DT correspond to pins PTM6 and PTM4 to PTM0.
Page 569: Port N
PMCR State PM4MD1 PM4MD0 Pin State Read Write PMDR value Data can be written to PMDR but no effect on pin state. Setting PMDR value Written data is output from the pin. Prohibited Input (Pull-up Pin state Data can be written to PMDR but no effect MOS on) on pin state.
Page 570: Sc Port
Initial Name Value Description 7 to 0 PN7DT Table 20.13 shows the function of PNDR. PN0DT Table 20.13 Port N Data Register (PNDR) Read/Write Operations PNCR State PNnMD1 PNnMD0 Pin State Read Write Other function PNDR value Data can be written to PNDR but no effect on pin state.
Page 571: 20.14.1 Register Description
20.14.1 Register Description Port SC has the following register. For details on the register address and access size, see section 24, List of Registers. • SC port data register (SCPDR) 20.14.2 Port SC Data Register (SCPDR) SCPDR is an 8-bit readable/writable that stores data for pins SCPT5 to SCPT0. Bits SCP5DT to SCP0DT correspond to pins SCPT5 to SCPT0.
Page 572 • SCP0DR and SCP2DR SCPCR State SCPnMD1 SCPnMD0 Pin State Read Write Other function Prohibited Prohibited TxD: Output SCPDR value Written data is output on TxD pin. RxD: Input (cannot be read) TxD: Output high RxD pin state Data can be written to SCPDR but impedance no effect on pin state.
Page 573: Section 21 A/D Converter
Section 21 A/D Converter This LSI includes a 10-bit successive-approximation A/D converter allowing selection of up to four analog input channels. 21.1 Features • 10-bit resolution • Four input channels • Minimum conversion time: 8.5 µs per channel (Pφ = 33 MHz operation) •...
Page 574: Figure 21.1 Block Diagram Of A/D Converter
Figure 21.1 shows a block diagram of the A/D converter. Internal Peripheral data bus data bus 10-bit Pφ/4 − Analog Pφ/8 Control circuit multi- Comparator plexer Pφ/16 Sample-and- hold circuit interrupt signal Legend ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D...
Page 575: Input/Output Pins
21.2 Input/Output Pins Table 21.1 summarizes the A/D converter’s pins. The AV and AV pins are the power supply for the analog circuits in the A/D converter. The AV pin also functions as the A/D conversion reference voltage pin. Table 21.1 Pin Configuration Input/ Pin Name Abbreviation...
Page 576: A/D Data Registers A To D (Addra To Addrd)
21.3.1 A/D Data Registers A to D (ADDRA to ADDRD) The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. Table 21.2 indicates the pairings of analog input channels and A/D data registers that store the results of A/D conversion.
Page 577 Initial Name Value Description ADIE A/D Interrupt Enable Enables or disables the interrupt (ADI) requested by ADF. Set the ADIE bit while the ADST bit is 0. 0: Interrupt (ADI) requested by ADF is disabled 1: Interrupt (ADI) requested by ADF is enabled ADST A/D Start Starts or stops A/D conversion.
Page 578 Initial Name Value Description CKS1 Clock Select CKS0 Selects the A/D conversion time. Clear the ADST bit to 0 before changing the conversion time. 00: Conversion time = 151 states (maximum) at Pφ/4 01: Conversion time = 285 states (maximum) at Pφ/8 10: Conversion time = 545 states (maximum) at Pφ/16 11: Setting prohibited Note: If the minimum conversion time is not satisfied,...
Page 579: Operation
21.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. To avoid malfunction, switch operating modes while the ADST bit of ADCSR is 0. Changing operating modes and channels and setting the ADST bit can be performed simultaneously.
Page 580: Scan Mode
21.4.3 Scan Mode Scan mode should be selected when performing A/D conversions of analog inputs on one or more specified channels. Scan mode is useful for monitoring analog inputs. 1. When the ADST bit is set to 1 by software, A/D conversion starts with the smaller number of the analog input channel in the group (for instance, AN0, and AN1 to AN3).
Page 581: Figure 21.2 A/D Conversion Timing
A/D conversion time (t CONV A/D conversion start delay time (t ) Analog input sampling time (t Write cycle A/D synchronization time Pφ Address Internal write signal Write timing of ADST Analog input sampling signal Sample and hold A/D conversion executed A/D converter Idle time A/D conversion ended...
Page 582: Interrupts And Dmac Transfer Request
21.5 Interrupts and DMAC Transfer Request The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request is enabled when ADF in ADCSR is set to 1and the ADIE bit in ADCSR is set to 1 after A/D conversion.
Page 583: Figure 21.3 Definitions Of A/D Conversion Accuracy
Digital output Ideal A/D conversion characteristic Quantization error Analog input voltage Figure 21.3 Definitions of A/D Conversion Accuracy Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog input Offset error voltage Figure 21.4 Definitions of A/D Conversion Accuracy Rev.
Page 584: Usage Notes
21.7 Usage Notes 21.7.1 Allowable Signal-Source Impedance For the analog input design of this LSI, conversion accuracy is guaranteed for an input signal with signal-source impedance of 5 kΩ or less. The specification is for charging input capacitance of the sample and hold circuit of the A/D converter within sampling time.
Page 585: Notes On Board Design
• Relationships of AV , AV and V Q, V Q: AV Q ± 0.2 V and AV Q. Even when the A/D converter is not used, do not open AV and AV 21.7.4 Notes on Board Design In designing a board, separate digital circuits and analog circuits. Do not intersect or locate closely signal lines of a digital circuit and an analog circuit.
Page 586: Figure 21.7 Analog Input Pin Equivalent Circuit
Table 21.6 Analog Input Pin Ratings Item Unit Analog input capacitance — Allowable signal-source impedance — kΩ 3 kΩ AN0 to AN3 To A/D converter 20 pF Note: Values are for reference. Figure 21.7 Analog Input Pin Equivalent Circuit Rev. 2.00, 09/03, page 540 of 690...
Page 587: Section 22 User Break Controller
Section 22 User Break Controller The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch.
Page 588: Figure 22.1 Block Diagram Of User Break Controller
Figure 22.1 shows a block diagram of the UBC. Access IAB LAB Control ASID Access comparator BBRA BARA Address comparator BAMRA ASID BASRA comparator Channel A Access BBRB comparator BARB Address comparator BAMRB ASID BASRB comparator BBRB Data comparator BDMRB Channel B BETR BRSR...
Page 589: Register Descriptions
22.2 Register Descriptions The user break controller has the following registers. For details on register addresses and access sizes, refer to section 24, List of Registers. • Break address register A (BARA) • Break address mask register A (BAMRA) • Break bus cycle register A (BBRA) •...
Page 590: Break Address Mask Register A (Bamra)
22.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA. Initial Name Value Description 31 to 0 BAMA31 to Break Address Mask A BAMA0 Specify bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0).
Page 591: Break Address Register B (Barb)
Initial Name Value Description IDA1 Instruction Fetch/Data Access Select A IDA0 Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle...
Page 592: Break Address Mask Register B (Bamrb)
22.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Initial Name Value Description 31 to 0 BAMB31 Break Address Mask B Specifies bits masked in the break address of channel B BAMB0 specified by BARB (BAB31 to BAB0).
Page 593: Break Data Mask Register B (Bdmrb)
22.2.7 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB. Initial Name Value Description 31 to 0 BDMB31 to Break Data Mask B BDMB0 Specifies bits masked in the break data of channel B specified by BDRB (BDB31 to BDB0).
Page 594 Initial Name Value Description CDB1 L Bus Cycle/I Bus Cycle Select B CDB0 Select the L bus cycle or I bus cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle IDB1...
Page 595: Break Control Register (Brcr)
22.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Specifies whether channels A and B are used in two independent channel conditions or under the sequential condition. 2. Specifies whether a break is set before or after instruction execution. 3.
Page 596 Initial Name Value Description SCMFCA L Bus Cycle Condition Match Flag A When the L bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel A does not match 1: The L bus cycle condition for channel A matches SCMFCB...
Page 597 Initial Name Value Description  9, 8 Reserved These bits are always read as 0. The write value should always be 0. DBEB Data Break Enable B Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel 1: The data bus condition is included in the condition of channel B...
Page 598: Execution Times Break Register (Betr)
22.2.10 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 – 1 times. When a break condition is satisfied, it decrements the BETR value.
Page 599: Branch Source Register (Brsr)
22.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset.
Page 600: Branch Destination Register (Brdr)
22.2.12 Branch Destination Register (BRDR) BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset.
Page 601: Break Asid Register B (Basrb)
22.2.14 Break ASID Register B (BASRB) BASRB is an 8-bit readable/writable register that specifies ASID which becomes the break condition for channel B. BASRB is in CCN. Initial Name Value Description  7 to 0 BASB7 Break ASID B Store ASID (bits 7 to 0) which is the break condition for BASB0 channel B.
Page 602 5. When selecting the I bus as the break condition, note the following:  Several bus masters, including the CPU and DMAC, are connected to the I bus. The UBC monitors bus cycles generated by all bus masters, and determines the condition match. ...
Page 603: Break On Instruction Fetch Cycle
22.3.2 Break on Instruction Fetch Cycle 1. When L bus/instruction fetch/read/word or longword is set in the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it breaks before or after the execution of the instruction can then be selected with the PCBA or PCBB bit of the break control register (BRCR) for the appropriate channel.
Page 604: Break On Data Access Cycle
22.3.3 Break on Data Access Cycle 1. If the L bus is specified as a break condition for data access break, condition comparison is performed for the logical addresses (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the physical addresses (and data) of the data access cycles that are issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is satisfied.
Page 605: Sequential Break
occurs at a delayed branch instruction or its delay slot, the break may not actually take place until the first instruction at the branch destination. 22.3.4 Sequential Break 1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches.
Page 606 1. When instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved in the SPC. The instruction that matched the condition is not executed, and the break occurs before it. However when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the SPC.
Page 607: Pc Trace
22.3.6 PC Trace 1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt exception) is generated, the branch source address and branch destination address are stored in BRSR and BRDR, respectively. 2. The values stored in BRSR and BRDR are as given below due to the kind of branch. ...
Page 608: Usage Examples
22.3.7 Usage Examples Break Condition Specified for an L Bus Instruction Fetch Cycle 1. Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300400 Specified conditions: Channel A/channel B independent mode •...
Page 609 3. Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300000 Specified conditions: Channel A/channel B independent mode • Channel A Address: H'00027128, Address mask: H'00000000 Bus cycle:...
Page 610 5. Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode •...
Page 611 Break Condition Specified for an L Bus Data Access Cycle Register specifications: BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode •...
Page 612: Notes
22.3.8 Notes 1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when the UBC register is changed, read from the last written register.
Page 613: Section 23 User Debugging Interface (Udi)
Section 23 User Debugging Interface (UDI) This LSI incorporates a user debugging interface (UDI) and advanced user debugger (AUD) for a boundary scan function and emulator support. This section describes the UDI. The AUD is a function exclusively for use by an emulator. Refer to the User’s Manual for the relevant emulator for details of the AUD.
Page 614: Input/Output Pins
23.2 Input/Output Pins Table 23.1 shows the pin configuration of the UDI. Table 23.1 Pin Configuration Pin Name Input/Output Description TCK * Input Serial Data Input/Output Clock Pin Data is serially supplied to the UDI from the data input pin (TDI), and output from the data output pin (TDO), in synchronization with this clock.
Page 615: Register Descriptions
Pin Name Input/Output Description Output Dedicated emulator pin A S E B R K A K AUDSYNC AUDATA3 to 0 AUDCK Note: * The pull-up MOS turns on if the pin function controller (PFC) is used to select other functions (UDI). 23.3 Register Descriptions The UDI has the following registers.
Page 616: Boundary Scan Register (Sdbsr)
Initial Name Value Description 15 to 13 TI7 to TI5 Test Instruction 7 to 0 The UDI instruction is transferred to SDIR by a serial input from TDI. 11 to 8 TI3 to TI0 For commands, see table 23.2.  7 to 2 Reserved These bits are always read as 1.
Page 617: Table 23.3 Sh7705 Pins And Boundary Scan Register Bits
Table 23.3 SH7705 Pins and Boundary Scan Register Bits Pin Name Pin Name from TDI VBUS/PTM6 D31/PTB7/PINT15 VBUS/PTM6 D30/PTB6/PINT14 D31/PTB7/PINT15 D29/PTB5/PINT13 D30/PTB6/PINT14 D28/PTB4/PINT12 D29/PTB5/PINT13 D27/PTB3/PINT11 D28/PTB4/PINT12 D26/PTB2/PINT10 D27/PTB3/PINT11 D25/PTB1/PINT9 D26/PTB2/PINT10 D24/PTB0/PINT8 D25/PTB1/PINT9 D23/PTA7/PINT7 D24/PTB0/PINT8 D22/PTA6/PINT6 D23/PTA7/PINT7 D21/PTA5/PINT5 D22/PTA6/PINT6 D20/PTA4/PINT4 D21/PTA5/PINT5...
Page 618 Pin Name Pin Name Control Control Control Control VBUS/PTM6 Control A0/PTK0 D31/PTB7/PINT15 Control A19/PTK1 D30/PTB6/PINT14 Control A20/PTK2 D29/PTB5/PINT13 Control A21/PTK3 D28/PTB4/PINT12 Control A22/PTK4 D27/PTB3/PINT11 Control A23/PTK5 D26/PTB2/PINT10 Control A24/PTK6 D25/PTB1/PINT9 Control A25/PTK7 D24/PTB0/PINT8 Control / PTC0 D23/PTA7/PINT7 Control / DQMUL/PTC1 W E 2 D22/PTA6/PINT6 Control...
Page 619 Pin Name Pin Name / PTD0 R A S L / PTD1 R A S U / PTD2 C A S L A0/PTK0 Control Control Control Control Control Control Control Control A19/PTK1 Control A20/PTK2 Control A21/PTK3 Control A22/PTK4 Control A23/PTK5 Control A24/PTK6 Control...
Page 620 Pin Name Pin Name / DQMUL/PTC1 Control NF/PTJ5 W E 2 / DQMUU/ / PTC2 Control NF/PTJ6 W E 3 Control NF/PTJ7 Control NF/PTM4 C S 0 / PTC3 Control PTM0 C S 2 / PTC4 Control PTM1 C S 3 / PTC5 Control PTM2...
Page 621 Pin Name Pin Name NF/PTJ6 PTM2 Control NF/PTJ7 PTM3 Control NF/PTM4 / PTF6 Control A S E B R K A K PTM0 STATUS0/PTE4/ R T S 0 PTM1 STATUS1/PTE5/ C T S 0 PTM2 PTN0/SUSPND PTM3 PTN1/TXENL / PTF6 PTN2/XVDATA A S E B R K A K / PTD3...
Page 622 Pin Name Pin Name AN0/PTL0 DREQ1/PTH6 AN1/PTL1 STATUS0/PTE4/ Control R T S 0 AN2/PTL2 STATUS1/PTE5/ Control C T S 0 AN3/PTL3 PTN0/SUSPND Control STATUS0/PTE4/ PTN1/TXENL Control R T S 0 STATUS1/PTE5/ PTN2/XVDATA Control C T S 0 PTN0/SUSPND PTN3/TXDMNS Control PTN1/TXENL PTN4/TXDPLS Control...
Page 623: Id Register (Sdid)
23.3.4 ID Register (SDID) SDID is a 32-bit read-only register that consists of connected 16-bit registers SDIDH and SDIDL, each of which can be read by the CPU. The IDCODE command is set from the UDI pin. This register can be read from the TDO when the TAP state is Shift-DR.
Page 624: Operation
23.4 Operation 23.4.1 TAP Controller Figure 23.2 shows the internal states of the TAP controller. State transitions basically conform to the JTAG standard. Test-logic-reset Run-test/idle Select-DR-scan Select-IR-scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR Figure 23.2 TAP Controller State Transitions Note: The transition condition is the TMS value at the rising edge of TCK.
Page 625: Reset Configuration
23.4.2 Reset Configuration Table 23.4 Reset Configuration Chip State A S E M D 0 R E S E T P T R S T Normal reset and UDI reset * Normal reset * UDI reset only Normal operation Reset hold * In ASE user mode * : Normal reset In ASE break mode *...
Page 626: Udi Reset
(when the UDI command is set) (when the boundary scan command is set) Figure 23.3 UDI Data Transfer Timing 23.4.4 UDI Reset An UDI reset is executed by setting an UDI reset assert command in SDIR. An UDI reset is of the same kind as a power-on reset.
Page 627: Boundary Scan
23.5 Boundary Scan A command can be set in SDIR by the UDI to place the UDI pins in boundary scan mode stipulated by JTAG. 23.5.1 Supported Instructions This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST) and three option instructions (IDCODE, CLAMP, and HIGHZ).
Page 628: Points For Attention
3. EXTEST: This instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board.
Page 629: Usage Notes
23.6 Usage Notes 1. An UDI command, once set, will not be modified as long as another command is not re-issued from the UDI. If the same command is given continuously, the command must be set after a command (BYPASS, etc.) that does not affect chip operations is once set. 2.
Page 630 Rev. 2.00, 09/03, page 584 of 690...
Page 631: Section 24 List Of Registers
Section 24 List of Registers This section gives information on the on-chip I/O registers and is configured as described below. 1. Register Addresses (by functional module, in order of the corresponding section numbers) • Descriptions by functional module, in order of the corresponding section numbers Entries that consist of ...
Page 632: Register Addresses
24.1 Register Addresses (by functional module, in order of the corresponding section numbers) Entries under Access size indicates numbers of bits. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access.
Page 633 Number Access Register Name of Bits Address Module Size Abbreviation Interrupt control register 0 ICR0 H'FFFF FEE0 INTC Interrupt control register 1 ICR1 H'A400 0010 Interrupt control register 2 ICR2 H'A400 0012 Interrupt request register 0 IRR0 H'A400 0004 Interrupt request register 1 IRR1 H'A400 0006 Interrupt request register 2...
Page 634 Number Access Register Name of Bits Address Module Size Abbreviation DMA source address register_0 SAR_0 H'A400 0020 DMAC 16/32 DMA destination address register_0 DAR_0 H'A400 0024 16/32 DMA transfer count register_0 DMATCR_0 32 H'A400 0028 16/32 DMA channel control register_0 CHCR_0 H'A400 002C 8/16/32...
Page 635 Number Access Register Name of Bits Address Module Size Abbreviation Timer start register TSTR H'FFFF FE92 TMU Timer constant register_0 TCOR_0 H'FFFF FE94 Timer counter_0 TCNT_0 H'FFFF FE98 Timer control register_0 TCR_0 H'FFFF FE9C Timer constant register_1 TCOR_1 H'FFFF FEA0 Timer counter_1 TCNT_1 H'FFFF FEA4...
Page 636 Number Access Register Name of Bits Address Module Size Abbreviation Timer interrupt enable register_1 TIER_1 H'A449 005C Timer status register_1 TSR_1 H'A449 0060 Timer counter_1 TCNT_1 H'A449 0064 Timer general register A_1 TGRA_1 H'A449 0068 Timer general register B_1 TGRB_1 H'A449 006C Timer general register C_1 TGRC_1...
Page 637 Number Access Register Name of Bits Address Module Size Abbreviation 64-Hz counter R64CNT H'FFFF FEC0 RTC Second counter RSECCNT H'FFFF FEC2 Minute counter RMINCNT H'FFFF FEC4 Hour counter RHRCNT H'FFFF FEC6 Day of week counter RWKCNT H'FFFF FEC8 Date counter RDAYCNT H'FFFF FECA Month counter...
Page 638 Number Access Register Name of Bits Address Module Size Abbreviation Serial mode register_2 SCSMR_2 H'A441 0000 SCIF_2 Bit rate register_2 SCBRR_2 H'A441 0004 (Channel 2) 8 Serial control register_2 SCSCR_2 H'A441 0008 Transmit data stop register_2 SCTDSR_2 8 H'A441 000C FIFO error count register_2 SCFER_2 H'A441 0010...
Page 639 Number Access Register Name Abbreviation of Bits Address Module Size       Port A control register PACR H'A400 0100 Port B control register PBCR H'A400 0102 Port C control register PCCR H'A400 0104 Port D control register PDCR H'A400 0106 Port E control register...
Page 640 Number Access Register Name Abbreviation of Bits Address Module Size       A/D data register A ADDRA H'A400 0080 A/D data register B ADDRB H'A400 0082 A/D data register C ADDRC H'A400 0084 A/D data register D ADDRD H'A400 0086 A/D control/status register...
Page 641: Register Bits
24.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/...
Page 642 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module         CCR1 Cache    ...
Page 643 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module Exception handing IPRA IPR15 IPR14 IPR13 IPR12 IPR11 IPR10 IPR9 IPR8 INTC IPR7 IPR6 IPR5 IPR4...
Page 644 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module         CMNCR     ...
Page 645 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module    IWRWD1 IWRWD0  CS6BBCR IWW1 IWW0 IWRWS1 IWRWS0  IWRRD1 IWRRD0  IWRRS1 IWRRS0 ...
Page 646 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module         CS4 WCR (burst ROM)  ...
Page 647 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module SDMR2 SDMR3 SAR_0 DMAC DAR_0         DMATCR_0 ...
Page 648 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module         CHCR_1 DMAC    ...
Page 649 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module         CHCR_3 DMAC    ...
Page 650 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module TCOR_1 TCNT_1        TCR_1   UNIE CKEG1 CKEG0 TPSC2...
Page 651 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module         TSTR     CST3 CST2 CST1...
Page 652 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module TCNT_1 TGRA_1 TGRB_1 TGRC_1 TGRD_1         TCR_2 CCLR2 CCLR1...
Page 653 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module         TMDR_3   BFWT  ...
Page 654 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module     RCR1 RCR2 PES2 PES1 PES0 RTCEN RESET START RYRAR ...
Page 655 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module  SCFDR_2 SCIF_2  SCFTDR_2 SCFTD7 SCFTD6 SCFTD5 SCFTD4 SCFTD3 SCFTD2 SCFTD1 SCFTD0 SCFRDR_2 SCFRD7 SCFRD6 SCFRD5 SCFRD4 SCFRD3 SCFRD2 SCFRD1 SCFRD0...
Page 656 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module PDCR PD7MD1 PD7MD0 PD6MD1 PD6MD0 PD5MD1 PD5MD0 PD4MD1 PD4MD0 PFC PD3MD1 PD3MD0 PD2MD1 PD2MD0 PD1MD1 PD1MD0 PD0MD1 PD0MD0 PECR...
Page 657 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module  PHDR PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT Port PJDR PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT...
Page 658 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module BARB BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17...
Page 659 Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/ Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module SDIR         SDID/SDIDH DID31 DID30 DID29 DID28 DID27 DID26...
Page 660: Register States In Each Operating Mode
24.3 Register States in Each Operating Mode Register Power-On Manual Software Module Abbreviation Reset Reset Standby Standby Sleep Module Initialized * Initialized * MMUCR Retained Retained Retained PTEH Undefined Undefined Retained Retained Retained PTEL Undefined Undefined Retained Retained Retained Undefined Undefined Retained Retained...
Page 661 Register Power-On Manual Software Module Abbreviation Reset Reset Standby Standby Sleep Module CS5ABCR Initialized Retained Retained Retained Retained CS5BBCR Initialized Retained Retained Retained Retained CS6ABCR Initialized Retained Retained Retained Retained CS6BBCR Initialized Retained Retained Retained Retained CS0WCR Initialized Retained Retained Retained Retained CS2 WCR...
Page 662 Register Power-On Manual Software Module Abbreviation Reset Reset Standby Standby Sleep Module DMATCR_3 Undefined Undefined Retained Retained Retained DMAC CHCR_3 Initialized Initialized Retained Retained Retained DMAOR Initialized Initialized Retained Retained Retained DMARS0 Initialized Initialized Retained Retained Retained DMARS1 Initialized Initialized Retained Retained Retained...
Page 663 Register Power-On Manual Software Module Abbreviation Reset Reset Standby Standby Sleep Module TSTR Initialized Initialized Retained Retained Retained TCR_0 Initialized Initialized Retained Retained Retained TMDR_0 Initialized Initialized Retained Retained Retained TIOR_0 Initialized Initialized Retained Retained Retained TIER_0 Initialized Initialized Retained Retained Retained TSR_0...
Page 664 Register Power-On Manual Software Module Abbreviation Reset Reset Standby Standby Sleep Module TCR_3 Initialized Initialized Retained Retained Retained TMDR_3 Initialized Initialized Retained Retained Retained TIOR_3 Initialized Initialized Retained Retained Retained TIER_3 Initialized Initialized Retained Retained Retained TSR_3 Initialized Initialized Retained Retained Retained TCNT_3...
Page 665 Register Power-On Manual Software Module Abbreviation Reset Reset Standby Standby Sleep Module SCSMR_0 Initialized Initialized Retained Retained Retained SCIF_0 SCBRR_0 Initialized Initialized Retained Retained Retained SCSCR_0 Initialized Initialized Retained Retained Retained SCTDSR_0 Initialized Initialized Retained Retained Retained SCFER_0 Initialized Initialized Retained Retained Retained...
Page 666 Register Power-On Manual Software Module Abbreviation Reset Reset Standby Standby Sleep Module EPSTL Initialized Initialized Retained Retained Retained IER0 Initialized Initialized Retained Retained Retained IER1 Initialized Initialized Retained Retained Retained EPSZ1 Initialized Initialized Retained Retained Retained DMAR Initialized Initialized Retained Retained Retained ISR0...
Page 667 Register Power-On Manual Software Module Abbreviation Reset Reset Standby Standby Sleep Module PHDR Initialized Retained Retained Retained Retained Port PJDR Initialized Retained Retained Retained Retained PKDR Initialized Retained Retained Retained Retained PLDR Initialized Retained Retained Retained Retained SCPDR Initialized Retained Retained Retained Retained...
Page 668 The SV bit is undefined. EXPEVT[11:0] = H'000 at a power-on reset and EXPEVT[11:0] = H'020 at a manual reset. The NMIL bit = 1 when the NMI input is high, and the NMIL bit = 0 when the NMI input is low.
Page 669: Section 25 Electrical Characteristics
Section 25 Electrical Characteristics 25.1 Absolute Maximum Ratings Table 25.1 shows the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage (I/O) –0.3 to 4.2 -RTC Power supply voltage (internal) –0.3 to 2.1 -PLL1 -PLL2 Input voltage (except port L) –0.3 to V...
Page 670: Figure 25.1 Power On/Off Sequence
• Power-off order 1. In the reverse order of powering-on, first turn off the 1.5 V power, then turn off the 3.3 V power within 1 ms. It is recommended that this interval will be as short as possible. 2. Pin states are undefined while only the 1.5 V power is off. The system design must ensure that these undefined states do not cause erroneous system operation.
Page 671: Dc Characteristics
25.2 DC Characteristics Tables 25.2 and 25.3 list DC characteristics. Table 25.2 DC Characteristics (1) [Common Items] (Condition: Ta = –20 to 75°C) Measurement Item Symbol Unit Conditions Power supply voltage -RTC -PLL1 -PLL2 — = 1.5 V Current Normal consumption operation Iφ...
Page 672 Measurement Item Symbol Unit Conditions All pins other — — capacitance than the USB transceiver pins (D+, D-) and PTM3 to PTM0 — — transceiver pins (D+, D–) and PTM3 to PTM0 Analog power-supply voltage (AD) Analog power-supply -USB 3.0 voltage (USB) Analog During A/D...
Page 673: Table 25.2 Dc Characteristics (2-A) [Excluding Usb-Related Pins]
Table 25.2 DC Characteristics (2-a) [Excluding USB-Related Pins] (Condition: Ta = –20 to 75°C) Measurement Item Symbol Unit Conditions Q × 0.9 — Input high Q + 0.3 R E S E T P voltage , NMI R E S E T M IRQ5 to IRQ0, PINT15 to PINT0, RXD0,...
Page 674: Table 25.2 Dc Characteristics (2-B) [Usb-Related Pins*]
Measurement Item Symbol Unit Conditions Q × 0.2 V Input low Other input –0.3 — voltage pins Output high All output pins V — — Q = 3.0 V, = –200 µA voltage — — Q = 3.0 V, = –2 mA Output low All output pins V —...
Page 675: Table 25.2 Dc Characteristics (2-C) [Usb Transceiver-Related Pins* 1 ]
Table 25.2 DC Characteristics (2-c) [USB Transceiver-Related Pins * (Condition: Ta = –20 to 75°C) Measurement Item Symbol Unit Conditions Power supply voltage * -USB (DP)–(DM) Differential input sensitivity — — Differential common mode — range Single ended receiver — threshold voltage Output high voltage —...
Page 676: Ac Characteristics
25.3 AC Characteristics In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Table 25.4 Maximum Operating Frequencies (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV...
Page 677: Clock Timing
25.3.1 Clock Timing Table 25.5 Clock Timing (Condition: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, = 3.0 to 3.6 V, V Q = V -RTC = V -USB = V -PLL1 = V...
Page 678: Figure 25.2 Extal Clock Input Timing
Item Symbol Unit Figure PLL synchronization settling time 1 — µs 25.9, 25.10 PLL1 PLL synchronization settling time 2 — µs 25.11 PLL2 Interrupt determination time — µs 25.10 IRLSTB (RTC used and standby mode) EXcyc EXTAL* (input) 1/2 V 1/2 V Note: * The clock input from the EXTAL pin.
Page 679: Figure 25.5 Power-On Oscillation Settling Time
Stable oscillation CKIO, internal clock RESPW RESPS OSC1 RESETP TRST Note: Oscillation settling time when built-in oscillator is used Figure 25.5 Power-On Oscillation Settling Time Stable oscillation Standby CKIO, internal clock RESPW OSC2 RESMW RESETP RESETM Note: Oscillation settling time when built-in oscillator is used Figure 25.6 Oscillation Settling Time at Standby Return (Return by Reset) Standby Stable oscillation...
Page 680: Figure 25.8 Oscillation Settling Time At Standby Return
Standby Stable oscillation CKIO, internal clock OSC4 IRL3 to IRL0 IRQ5 to IRQ0 PINT15 to PINT0 Note: Oscillation settling time when built-in oscillator is used in oscillation stop mode Figure 25.8 Oscillation Settling Time at Standby Return (Return by IRQ5 to IRQ0, PINT15 to PINT0, and I R L 3 I R L 0 Reset or NMI interrupt request...
Page 681: Figure 25.10 Pll Synchronization Settling Time By Irq/Irl, Pint Interrupts
PINT15 to PINT0, IRQ5 to IRQ0/IRL3 to IRL0 interrupt request Stable input clock Stable input clock EXTAL input or CKIO input PLL synchronization PLL synchronization IRLSTB PLL1 PLL output, CKIO output Internal clock STATUS 0 Normal Standby Normal STATUS 1 Note: PLL oscillation settling time when clock is input from EXTAL pin or CKIO pin in oscillation continuous mode.
Page 682: Control Signal Timing
25.3.2 Control Signal Timing Table 25.6 Control Signal Timing (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV = 3.0 to 3.6 V, V Q = V -RTC = V -USB = V...
Page 683: Figure 25.12 Reset Input Timing
CKIO RESPS RESPS RESMS RESMS RESPW RESETP RESMW RESETM Figure 25.12 Reset Input Timing CKIO NMIH NMIS IRQH IRQS IRQ5 to IRQ0 Figure 25.13 Interrupt Signal Input Timing CKIO BREQH BREQS BREQH BREQS BREQ BACKD BACKD BACK BOFF1 BON1 A25 to A0, D31 to D0 BOFF2 BON2...
Page 684: Ac Bus Timing
Normal mode Standby mode Normal mode CKIO STATUS 0 STATUS 1 BOFF2 BON2 RD, RD/WR, RASU/L, CASU/L, CSn, WEn, BS, BOFF1 BON1 A25 to A0, D31 to D0 Figure 25.15 Pin Drive Timing at Standby 25.3.3 AC Bus Timing Table 25.7 Bus Timing (1) (Conditions: V Q = V -RTC = V...
Page 685 66.67 MHz Item Symbol Min Unit Figure Write enable delay time — 1/2 t +10 ns 25.16 to 25.21 Write data delay time 1 — 25.16 to 25.20 WDD1 Write data delay time 2 — 25.26 to 25.29, 25.33 to 25.35 WDD2 Write data hold time 1 —...
Page 686: Basic Timing
25.3.4 Basic Timing CKIO A25 to A0 CSD1 CSD1 RWD1 RWD1 RD/WR RDH1 Read RDS1 D31 to D0 WEn * Write WDH1 WDD1 D31 to D0 WDH4 DACD DACD DACKn * Notes: 1. DACKn is a waveform when active-low is specified. 2.
Page 687: Figure 25.17 Basic Bus Cycle (One Software Wait)
CKIO A25 to A0 CSD1 CSD1 RWD1 RWD1 RD/WR RDH1 Read RDS1 D31 to D0 WEn * Write WDH1 WDD1 D31 to D0 WDH4 DACD DACD DACKn * WAIT Notes: 1. DACKn is a waveform when active-low is specified. 2. Output timing is the same when reading byte-selection SRAM. Figure 25.17 Basic Bus Cycle (One Software Wait) Rev.
Page 688: Figure 25.18 Basic Bus Cycle (One External Wait)
CKIO A25 to A0 CSD1 CSD1 RWD1 RWD1 RD/WR RDH1 Read RDS1 D31 to D0 WEn * Write WDH1 WDD1 D31 to D0 WDH4 DACD DACD DACKn * WAIT Notes: 1. DACKn is a waveform when active-low is specified. 2. Output timing is the same when reading byte-selection SRAM. Figure 25.18 Basic Bus Cycle (One External Wait) Rev.
Page 689: Figure 25.19 Basic Bus Cycle (One Software Wait, External Wait Enabled (Wm Bit = 0)
Tnop Tnop CKIO A25 to A0 CSD1 CSD1 CSD1 CSD1 RWD1 RWD1 RWD1 RWD1 RD/WR RDH1 RDH1 Read RDS1 RDS1 D15 to D0 WEn * Write WDD1 WDH1 WDD1 WDH1 D15 to D0 WDH4 WDH4 DACD DACD DACD DACD DACKn * WAIT Notes: 1.
Page 690: Figure 25.20 Address/Data Multiplex I/O Bus Cycle (Three Address Cycles, One Software Wait, One External Wait)
CKIO A25 to A0 CSD1 CSD1 RWD1 RWD1 RD/WR RDH1 Read RDS1 D15 to D0 Data Address WE0/1 WDD1 Write WDH1 D15 to D0 Address Data WAIT DACD DACD DACKn* Note: * DACKn is a waveform when active-low is specified. Figure 25.20 Address/Data Multiplex I/O Bus Cycle (Three Address Cycles, One Software Wait, One External Wait) Rev.
Page 691: Burst Rom Timing
25.3.5 Burst ROM Timing CKIO A25 to A0 CSD1 CSD1 RWD1 RWD1 RD/WR RDS3 RDS3 RDH3 RDH3 D31 to D0 DACD DACD DACKn WAIT is specified by earlier one of change of A25 to A0 or the RD rising edge. Notes: 1.
Page 692: Synchronous Dram Timing
25.3.6 Synchronous DRAM Timing CKIO Column address A25 to A0 Row address A12/A11 * Read A command CSD1 CSD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx RDS2 RDH2 D31 to D0 (High) DACD DACD DACKn * Notes: 1.
Page 693: Figure 25.23 Synchronous Dram Single Read Bus Cycle (Auto Precharge, Cas Latency = 2, Trcd = 2 Cycle, Trp = 2 Cycle)
CKIO Row address Column address A25 to A0 A12/A11 * Read A command CSD1 CSD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx RDS2 RDH2 D31 to D0 (High) DACD DACD DACKn * Notes: 1. Address pin to be connected to A10 of SDRAM. 2.
Page 694: Figure 25.24 Synchronous Dram Burst Read Bus Cycle (Single Read × 4), (Auto Precharge, Cas Latency = 2, Trcd = 1 Cycle, Trp = 2 Cycle)
CKIO Column A25 to A0 (1 to 4) address address A12/A11 * Read command Read A command CSD1 CSD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx RDS2 RDS2 RDH2 RDH2 D31 to D0 (High) DACD DACD DACKn * Notes: 1.
Page 695: Figure 25.25 Synchronous Dram Burst Read Bus Cycle (Single Read × 4), (Auto Precharge, Cas Latency = 2, Trcd = 2 Cycle, Trp = 1 Cycle)
CKIO Column A25 to A0 Row address (1 to 4) address A12/A11 * Read command Read A command CSD1 CSD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx RDS2 RDH2 RDS2 RDH2 D31 to D0 (High) DACD DACD DACKn *...
Page 696: Figure 25.26 Synchronous Dram Single Write Bus Cycle (Auto Precharge, Trwl = 2 Cycle)
Trwl CKIO Column A25 to A0 Row address address A12/A11 * Write A command CSD1 CSD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx WDD2 WDH2 D31 to D0 (High) DACD DACD DACKn * Notes: 1. Address pin to be connected to A10 of SDRAM. 2.
Page 697: Figure 25.27 Synchronous Dram Single Write Bus Cycle (Auto Precharge, Trcd = 3 Cycle, Trwl = 2 Cycle)
Trwl CKIO A25 to A0 Row address Column address A12/A11 * Write A command CSD1 CSD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx WDH2 WDD2 D31 to D0 (High) DACD DACD DACKn * Notes: 1.
Page 698: Figure 25.28 Synchronous Dram Burst Write Bus Cycle (Single Write × 4)
Trwl CKIO A25 to A0 Column (1-4) Row address address A12/A11 * Write A Write command command CSD1 CSD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx WDD2 WDH2 WDD2 WDH2 D31 to D0 (High) DACD DACD...
Page 699: Figure 25.29 Synchronous Dram Burst Write Bus Cycle (Single Write × 4)
Trwl CKIO A25 to A0 Column (1-4) Row address address A12/A11 * Write A Write command command CSD1 CSD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx WDD2 WDH2 WDD2 WDH2 D31 to D0 (High) DACD DACD...
Page 700: Figure 25.30 Synchronous Dram Burst Read Bus Cycle (Single Read × 4)
CKIO Column A25 to A0 (1-4) address address A12/A11 * Read command CSD1 CSD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx RDS2 RDH2 RDH2 RDS2 D31 to D0 (High) DACD DACD DACKn * Notes: 1. Address pin to be connected to A10 of SDRAM. 2.
Page 701 CKIO A25 to A0 Column (1-4) address A12/A11 * Read command CSD1 CSD1 CSD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASU/L CASD1 CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMD1 DQMxx RDS2 RDH2 RDS2 RDH2 D31 to D0 (High) DACD DACD DACD DACKn * Notes: 1.
Page 702 CKIO A25 to A0 Column (1-4) Row address address A12/A11 * Read command CSD1 CSD1 CSD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASD1 RASD1 RASD1 RASU/L CASD1 CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMD1 DQMxx RDS2 RDH2 RDS2 RDH2 D31 to D0 (High) DACD DACD...
Page 703 CKIO Column A25 to A0 (1-4) Row address address A12/A11 * Write command CSD1 CSD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx WDD2 WDD2 WDH2 WDH2 D31 to D0 (High) DACD DACD DACKn * Notes: 1.
Page 704 Tnop CKIO A25 to A0 Column (1-4) address A12/A11 * Write command CSD1 CSD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx WDD2 WDD2 WDH2 WDH2 D31 to D0 (High) DACD DACD DACKn * Notes: 1. Address pin to be connected to A10 of SDRAM. 2.
Page 705 CKIO Column A25 to A0 (1-4) Row address address A12/A11 * Write command CSD1 CSD1 RWD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASD1 RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMD1 DQMD1 DQMxx WDD2 WDH2 WDD2 WDH2 D31 to D0 (High) DACD DACD DACKn *...
Page 706: Figure 25.36 Synchronous Dram Auto-Refresh Timing (Trp = 2 Cycle)
CKIO A25 to A0 A12/A11 * CSD1 CSD1 CSD1 CSD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMxx (Hi-Z) D31 to D0 (High) DACKn * Notes: 1. Address pin to be connected to A10 of SDRAM. 2.
Page 707: Figure 25.37 Synchronous Dram Self-Refresh Timing (Trp = 2 Cycle)
CKIO A25 to A0 A12/A11 * CSD1 CSD1 CSD1 CSD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASD1 RASD1 RASU/L CASD1 CASD1 CASU/L DQMxx (Hi-Z) D31 to D0 CKED1 CKED1 DACKn * Notes: 1. Address pin to be connected to A10 of SDRAM. 2.
Page 708: Figure 25.38 Synchronous Dram Mode Register Write Timing (Trp = 2 Cycle)
CKIO PALL A25 to A0 A12/A11 * CSD1 CSD1 CSD1 CSD1 CSD1 CSD1 CSD1 CSD1 RWD1 RWD1 RWD1 RWD1 RWD1 RD/WR RASD1 RASD1 RASD1 RASD1 RASD1 RASD1 RASD1 RASD1 RASU/L CASD1 CASD1 CASD1 CASD1 CASD1 CASD1 CASU/L DQMxx (Hi-Z) D31 to D0 DACKn * Notes: 1.
Page 709: Table 25.8 Bus Timing (2)
Table 25.8 Bus Timing (2) (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV = 3.0 to 3.6 V, V Q = V -RTC = V -USB = V -PLL1 = V -PLL2 =...
Page 710: Figure 25.39 Access Timing In Low-Frequency Mode (Auto Precharge)
Tnop Trwl CKIO A25 to A0 A12/A11 * CSD2 CSD2 CSD2 CSD2 RWD2 RWD2 RWD2 RD/WR RASD2 RASD2 RASD2 RASD2 RASU/L CASD2 CASD2 CASD2 CASD2 CASU/L DQMD2 DQMD2 DQMD2 DQMD2 DQMxx WDD3 RDH4 WDH3 RDS4 D31 to D0 (High) DACD DACD DACD DACD...
Page 711: Figure 25.40 Synchronous Dram Auto-Refresh Timing (Trp = 2 Cycle, Low-Frequency Mode)
CKIO A25 to A0 A12/A11 * CSD2 CSD2 CSD2 CSD2 RWD2 RWD2 RWD2 RD/WR RASD2 RASD2 RASD2 RASD2 RASU/L CASD2 CASD2 CASU/L DQMxx (Hi-Z) D31 to D0 (High) DACKn * Notes: 1. Address pin to be connected to A10 of SDRAM. 2.
Page 712: Figure 25.41 Synchronous Dram Self-Refresh Timing (Trp = 2 Cycle, Low-Frequency Mode)
CKIO A25 to A0 A12/A11 * CSD2 CSD2 CSD2 CSD2 RWD2 RWD2 RWD2 RD/WR RASD2 RASD2 RASD2 RASD2 RASU/L CASD2 CASD2 CASU/L DQMxx (Hi-Z) D31 to D0 CKED2 CKED2 DACKn * Notes: 1. Address pin to be connected to A10 of SDRAM. 2.
Page 713: Figure 25.42 Synchronous Dram Mode Register Write Timing (Trp = 2 Cycle, Low-Frequency Mode)
CKIO PALL A25 to A0 A12/A11 * CSD2 CSD2 CSD2 CSD2 CSD2 CSD2 CSD2 CSD2 RWD2 RWD2 RWD2 RWD2 RWD2 RD/WR RASD2 RASD2 RASD2 RASD2 RASD2 RASD2 RASD2 RASD2 RASU/L CASD2 CASD2 CASD2 CASD2 CASD2 CASD2 CASU/L DQMxx (Hi-Z) D31 to D0 DACKn * Notes: 1.
Page 714: Dmac Signal Timing
25.3.7 DMAC Signal Timing Table 25.9 DMAC Signal Timing (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV = 3.0 to 3.6 V, V Q = V -RTC = V -USB = V...
Page 715: Tmu Signal Timing
25.3.8 TMU Signal Timing Table 25.10 TMU Signal Timing (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV = 3.0 to 3.6 V, V Q = V -RTC = V -USB = V...
Page 716: Rtc Signal Timing
25.3.9 RTC Signal Timing Table 25.11 RTC Signal Timing (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV = 3.0 to 3.6 V, V Q = V -RTC = V -USB = V...
Page 717: Scif Module Signal Timing
25.3.11 SCIF Module Signal Timing Table 25.13 SCIF Module Signal Timing (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV = 3.0 to 3.6 V, V Q = V -RTC = V -USB = V...
Page 718: Usb Module Signal Timing
Scyc (data trans- mission) (data reception) RTSD CTSS CTSH Figure 25.50 SCIF Input/Output Timing in Clock Synchronous Mode 25.3.12 USB Module Signal Timing Table 25.14 USB Module Clock Timing (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV...
Page 719: Usb Transceiver Timing
State oscillation USB crystal oscillator CCmin UOSC Figure 25.52 Oscillation Settling Time when USB Crystal Oscillator Is Turned On 25.3.13 USB Transceiver Timing Table 25.15 USB Transceiver Timing (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV...
Page 720: Port Input/Output Timing
25.3.14 Port Input/Output Timing Table 25.16 Port Input/Output Timing (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV = 3.0 to 3.6 V, V Q = V -RTC = V -USB = V...
Page 721: Udi Related Pin Timing
25.3.15 UDI Related Pin Timing Table 25.17 UDI Related Pin Timing (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV = 3.0 to 3.6 V, V Q = V -RTC = V -USB = V...
Page 722: Figure 25.55
RESETP TRSTS TRSTH TRST Figure 25.55 Input Timing (Reset Hold) T R S T TCKcyc TDIS TDIH TMSS TMSH TDOD Figure 25.56 UDI Data Transfer Timing RESETP ASEMD0S ASEMD0H ASEMD0 Figure 25.57 Input Timing A S E M D 0 Rev.
Page 723: Figure 25.58 Output Load Circuit
25.3.16 AC Characteristics Measurement Conditions • I/O signal reference level: V Q/2 (V Q = 3.0 to 3.6 V, V = 1.4 to 1.6 V) • Input pulse level: V Q to 3.0 V (where , NMI, IRQ5 to IRQ0, R E S E T P R E S E T M A S E M D 0...
Page 724: Table 25.18 A/D Converter Characteristics
25.4 A/D Converter Characteristics Table 25.18 lists the A/D converter characteristics. Table 25.18 A/D Converter Characteristics (Conditions: V Q = V -RTC = V -USB = 3.0 to 3.6 V, V -PLL1 = V -PLL2 = 1.4 to 1.6 V, AV = 3.0 to 3.6 V, V Q = V -RTC = V...
Page 725 Appendix I/O Port States in Each Processing State Table A.1 I/O Port States in Each Processing State Reset Power-Down States Power-on Manual Software Mastership Handling of Category Pin Reset Reset Standby Sleep Released Unused Pins Clock EXTAL Pull-up XTAL Open EXTAL2 Pull-up XTAL2...
Page 726 Reset Power-Down States Power-on Manual Software Mastership Handling of Reset Reset Standby Sleep Released Unused Pins Category Pin Data D[15:0] Pull-up Z P * Z P * IO P * Z P * Pull-up D[23:16]/ IO/IO PTA[7:0]/ PINT[7:0] Z P * Z P * IO P * Z P *...
Page 727 Reset Power-Down States Power-on Manual Software Mastership Handling of Reset Reset Standby Sleep Released Unused Pins Category Pin Z P * Z K * I P * I P * DMAC I/IO Pull-up DREQ0/ PTH[5] O P * Z K * O P * O P * DACK0/...
Page 728 Reset Power-Down States Power-on Manual Software Mastership Handling of Reset Reset Standby Sleep Released Unused Pins Category Pin O P * O K * O P * O P * O/IO Open TXDMNS/ PTN[3] O P * O K * O P * O P * TXDPLS/...
Page 729 Reset Power-Down States Power-on Manual Software Mastership Handling of Reset Reset Standby Sleep Released Unused Pins Category Pin       Vcc_USB VccQ Power supply       Vss_USB VssQ voltage    ...
Page 730 Pull-up MOS open To avoid the power friction, Vcc-PLL1, Vcc-PLL2, and Vss-PLL1, Vss-PLL2, and other digital Vcc, Vss should be arranged in three independent patterns from the board power-supply source. The values of PTJ6, PTJ1, and PTJ0 differ during power-on reset and after the power-on reset state is released.
Page 731 Package Dimensions Figures B.1 and B.2 show the package dimensions. Unit: mm 30.0 ± 0.2 *0.22 ± 0.05 0.08 M 0.20 ± 0.04 1.25 0° − 8° 0.5 ± 0.1 0.08 Package Code FP-208C  JEDEC JEITA Conforms *Dimension including the plating thickness Base material dimension Mass (reference value) 2.7 g...
Page 732 Unit: mm 12.00 0.20 C A 17 15 0.65 4 × 0.15 0.80 208 × φ0.40 ± 0.05 φ0.08 0.2 C 0.10 C Package Code TBP-208A  JEDEC  JEITA Mass (reference value) 0.26 g Figure B.2 Package Dimensions (TBP-208A) Rev.
Page 733 Index 16-bit timer pulse unit ......329 Crystal resonator ........273 16-Bit/32-Bit Displacement ..... 41 Cycle-Steal mode ........264 A/D conversion time ......534 Data stage ..........457 A/D converter ........527 Data-Array Read ........105 Absolute Addresses ......... 41 Data-Array Write........
Page 734 Load/Store Architecture ......40 BASRA...... 554, 594, 612, 621 Low-frequency mode ......228 BASRB...... 555, 594, 612, 621 Low-Power Consumption State ....25 BBRA ......544, 594, 612, 621 BBRB ......547, 594, 612, 621 MMU............65 BDMRB..... 547, 594, 611, 621 Module Standby Function .....
Page 735 ICR2 ......132, 587, 597, 614 PNDR......523, 593, 611, 621 IER0 ......444, 592, 609, 620 PTEH .........586, 595, 614 IER1 ......444, 592, 609, 620 PTEL .........586, 595, 614 IFR0......441, 592, 609, 619 R64CNT..... 354, 591, 607, 618 IFR1......
Page 736 SDID ..........577 Save Status Register (SSR)...... 36 SDID/SDIDH..... 594, 613, 621 Scan mode ..........534 SDIDL ....... 594, 613, 621 SDRAM interface........198 SDIR......569, 594, 613, 621 Sequential break........559 SDMR2.......229, 587, 601, 615 Serial communication interface with FIFO SDMR3.......230, 587, 601, 615 .............
Page 737 Publication Date: 1st Edition, November 2002 Rev.2.00, September 19, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. ©2002, 2003 Renesas Technology Corp. All rights reserved. Printed in Japan.
Page 738 Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd.
Page 739 SH7705 Group Hardware Manual REJ09B0082-0200O...

This manual is also suitable for:

Superh risc engine series Sh7700 series

Renesas SH7705 Hardware Manual

Configuration of this Manual

Table of Contents

Asthefinal Partof Eachsection.

Appendix

Section 1 Overview

Section 2 CPU

Section 3 Memory Management Unit (MMU)

Section 4 Cache

Section 5 Exception Handling

Section 6 Interrupt Controller (INTC)

Section 7 Bus State Controller (BSC)

Section 8 Direct Memory Access Controller (DMAC)

Section 9 Clock Pulse Generator (CPG)

Section 10 Watchdog Timer (WDT)

Section 11 Power-Down Modes

Section 12 Timer Unit (TMU)

Section 13 Compare Match Timer (CMT)

Section 14 16-Bit Timer Pulse Unit (TPU)

Section 15 Realtime Clock (RTC)

Section 16 Serial Communication Interface with FIFO (SCIF)

Section 17 Infrared Data Association Module (Irda)

Section 18 USB Function Module

Section 19 Pin Function Controller

Section 20 I/O Ports

Section 21 A/D Converter

Section 22 User Break Controller

Section 23 User Debugging Interface (UDI)

Section 24 List of Registers

Section 25 Electrical Characteristics

Quick Links

Chapters

Related Manuals for Renesas SH7705

Summary of Contents for Renesas SH7705