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8TCSR2—Timer Control/Status Register 2
8TCSR3—Timer Control/Status Register 3
8TCSR2
Initial value
Read/Write
8TCSR3
Initial value
Read/Write
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Bit
7
6
5
CMFB
CMFA
OVF
0
0
0
R/(W)*
R/(W)*
R/(W)*
Bit
7
6
5
CMFB
CMFA
OVF
0
0
0
R/(W)*
R/(W)*
R/(W)*
Timer overflow flag
[Clearing condition]
0
Read OVF when OVF = 1, then write 0 in OVF.
[Setting condition]
1
8TCNT overflows from H'FF to H'00.
Compare match/input capture flag A
[Clearing condition]
0
Read CMFA when CMFA = 1, then write 0 in CMFA.
[Setting condition]
1
8TCNT = TCORA
Compare match/input capture flag B
[Clearing condition]
0
Read CMFB when CMFB = 1, then write 0 in CMFB.
[Setting conditions]
• 8TCNT = TCORB
1
• The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
H'FFF92
H'FFF93
4
3
2
OIS3
OIS2
1
0
0
—
R/W
R/W
4
3
2
ICE
OIS3
OIS2
0
0
0
R/W
R/W
R/W
Output select A1 and A0
Bit 1
Bit 0
OS1
OS0
0
0
1
0
1
1
Output/input capture edge select B3 and B2
Bit 3
Bit 2
ICE in
8TCSR3
OIS3
OIS2
0
No change at compare match B
0
1
0 output at compare match B
0
0
1 output at compare match B
1
Output toggles at compare match
1
B
TCORB input capture on rising
0
edge
0
TCORB input capture on falling
1
1
edge
0
TCORB input capture on both
1
rising and falling edges
1
Input capture enable
0
TCORB is a compare match register
1
TCORB is an input capture register
8-bit timer channel 2
8-bit timer channel 3
1
0
OS1
OS0
0
0
R/W
R/W
1
0
OS1
OS0
0
0
R/W
R/W
Description
No change at compare match A
0 output at compare match A
1 output at compare match A
Output toggles at compare
match A
Description
701
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