Hitachi H8/3006 Hardware Manual page 371

For the timing, see section 10.4, Operation.
Bit 7—Compare Match Interrupt Enable B (CMIEB): Enables or disables the CMIB interrupt
request when the CMFB flag is set to 1 in 8TCSR.
Bit 7
CMIEB Description
0 CMIB interrupt requested by CMFB is disabled
1 CMIB interrupt requested by CMFB is enabled
Bit 6—Compare Match Interrupt Enable A (CMIEA): Enables or disables the CMIA interrupt
request when the CMFA flag is set to 1 in 8TCSR.
Bit 6
CMIEA Description
0 CMIA interrupt requested by CMFA is disabled
1 CMIA interrupt requested by CMFA is enabled
Bit 5—Timer Overflow Interrupt Enable (OVIE): Enables or disables the OVI interrupt
request when the OVF flag is set to 1 in 8TCSR.
Bit 5
OVIE Description
0 OVI interrupt requested by OVF is disabled
1 OVI interrupt requested by OVF is enabled
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits specify the 8TCNT
clearing source. Compare match A or B, or input capture B, can be selected as the clearing source.
Bit 4 Bit 3
CCLR1 CCLR0 Description
0 0 Clearing is disabled
1 Cleared by compare match A
1 0 Cleared by compare match B/input capture B
1 Cleared by input capture B
(Initial value)
(Initial value)
(Initial value)
(Initial value)
355