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Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read.
Bit
PA
Initial value
Read/Write
R/W
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 8.12 Port A Pin Functions (Modes 1, 2)
Pin
Pin Functions and Selection Method
PA
/TP
/
Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit PA
7
7
TIOCB
function as follows.
2
16-bit timer channel 2
settings
PA
DDR
7
NDER7
Pin function
Note: * TIOCB
16-bit timer channel 2
settings
IOB2
IOB1
IOB0
264
7
6
5
PA
PA
7
6
0
0
0
R/W
R/W
(1) in table below
TIOCB
input when IOB2 = 1 and PWM2 = 0.
2
(2)
0
0
4
3
PA
PA
5
4
3
0
0
R/W
R/W
Port A data 7 to 0
These bits store data for port A pins
—
—
output
2
(1)
0
0
1
1
—
2
1
PA
PA
2
1
0
0
R/W
R/W
DDR select the pin
7
(2) in table below
0
1
—
0
PA
input
PA
output
7
7
TIOCB
input*
2
(2)
1
—
—
0
PA
0
0
R/W
1
1
TP
output
7
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