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φ
Address bus
CS
0
AS
RD
Data bus
6.8.3
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface.
Wait states cannot be inserted in a burst cycle.
Full access
T
T
1
2
Read data
Figure 6.40 Example of Burst ROM Access Timing
Burst access
T
T
T
3
1
Only lower address changes
Read data
T
T
2
1
2
Read data
173
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