Dram Control Register B (Drcrb) - Hitachi H8/3006 Hardware Manual

Bit 2
RDM Description
0 DRAM interface: RAS up mode selected
1 DRAM interface: RAS down mode selected
Bit 1—Self-Refresh Mode (SRFMD): Specifies DRAM self-refreshing in software standby
mode.
When any of areas 2 to 5 is designated as DRAM space, DRAM self-refreshing is possible when a
transition is made to software standby mode after the SRFMD bit has been set to 1.
The normal access state is restored when software standby mode is exited, regardless of the
SRFMD setting.
Bit 1
SRFMD Description
0 DRAM self-refreshing disabled in software standby mode
1 DRAM self-refreshing enabled in software standby mode
Bit 0—Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If
areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1.
Bit 0
RFSHE Description
RFSH pin refresh signal output disabled
0
(RFSH pin can be used as input/output port)
RFSH pin refresh signal output enabled
1
6.2.8

DRAM Control Register B (DRCRB)

Bit 7
MXC1
Initial value 0
Read/Write R/W
DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column
address bits for the DRAM interface, the column address strobe output pin, enabling or disabling
of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state
insertion between RAS and CAS, and enabling or disabling of wait state insertion in refresh
cycles.
6 5
MXC0 CSEL RCYCE
0 0
R/W R/W
4 3
— TPC
0 1
R/W — R/W
(Initial value)
(Initial value)
(Initial value)
2 1 0
RCW RLW
0 0 0
R/W R/W
121