Hitachi H8/3006 Hardware Manual page 11

6.4.3 Valid Strobes........................................................................................................ 133
6.4.4 Memory Areas ...................................................................................................... 134
6.4.5 Basic Bus Control Signal Timing ......................................................................... 136
6.4.6 Wait Control.......................................................................................................... 143
6.5 DRAM Interface ................................................................................................................ 145
6.5.1 Overview............................................................................................................... 145
DRAM Space and RAS Output Pin Settings........................................................ 145
6.5.2
6.5.3 Address Multiplexing............................................................................................ 146
6.5.4 Data Bus................................................................................................................ 146
6.5.5 Pins Used for DRAM Interface ............................................................................ 146
6.5.6 Basic Timing......................................................................................................... 147
6.5.7 Precharge State Control ........................................................................................ 148
6.5.8 Wait Control.......................................................................................................... 149
Byte Access Control and CAS Output Pin ........................................................... 150
6.5.9
6.5.10 Burst Operation..................................................................................................... 152
6.5.11 Refresh Control..................................................................................................... 157
6.5.12 Examples of Use ................................................................................................... 160
6.5.13 Usage Notes .......................................................................................................... 164
6.6 Interval Timer .................................................................................................................... 167
6.6.1 Operation .............................................................................................................. 167
6.7 Interrupt Sources................................................................................................................ 172
6.8 Burst ROM Interface.......................................................................................................... 172
6.8.1 Overview............................................................................................................... 172
6.8.2 Basic Timing......................................................................................................... 172
6.8.3 Wait Control.......................................................................................................... 173
6.9 Idle Cycle ........................................................................................................................... 174
6.9.1 Operation .............................................................................................................. 174
6.9.2 Pin States in Idle Cycle ......................................................................................... 177
6.10 Bus Arbiter ......................................................................................................................... 178
6.10.1 Operation .............................................................................................................. 178
6.11 Register and Pin Input Timing ........................................................................................... 181
6.11.1 Register Write Timing .......................................................................................... 181
6.11.2 BREQ Pin Input Timing ....................................................................................... 182
Section 7 DMA Controller
7.1 Overview............................................................................................................................ 183
7.1.1 Features ................................................................................................................. 183
7.1.2 Block Diagram...................................................................................................... 184
7.1.3 Functional Overview ............................................................................................ 185
7.1.4 Pin Configuration.................................................................................................. 186
7.1.5 Register Configuration.......................................................................................... 186
7.2 Register Descriptions (1) (Short Address Mode)............................................................... 188
7.2.1 Memory Address Registers (MAR)...................................................................... 188
iv
................................................................................................. 183