Hitachi H8/3006 Hardware Manual page 601

Item
SCI Input Asyn-
clock chronous
cycle
Syn-
chronous
Input clock rise
time
Input clock fall
time
Input clock
pulse width
Transmit data
delay time
Receive data
setup time
(synchronous)
Receive Clock
data hold input
time (syn-
Clock
chronous)
output
DMAC TEND delay
time 1
TEND delay
time 2
DREQ setup
time
DREQ hold
time
588
A
Symbol Min Max
t 4 —
Scyc
6 —
t 1.5 —
SCKr
t 1.5 —
SCKf
t 0.4 0.6
SCKW
t — 100
TXD
t 100 —
RXS
t 100 —
RXH
0 —
t — 100
TED1
t — 100
TED2
t 40 —
DRQS
t 10 —
DRQH
Condition
B C
Min Max Min Max
4 — 4 —
6 — 6 —
1.5 — 1.5 —
1.5 — 1.5 —
0.4 0.6 0.4 0.6
— 100 — 100
100 — 100 —
100 — 100 —
0 — 0 —
— 100 — 50
— 100 — 50
40 — 25 —
10 — 10 —
Test
Unit Conditions
t Figure 20.20
cyc
t
cyc
t
cyc
t
cyc
t
Scyc
ns Figure 20.21
ns
ns
ns
ns Figure 20.22,
figure 20.23
ns
ns Figure 20.24
ns