Block Diagram - Hitachi H8/3006 Hardware Manual

7.1.2

Block Diagram

Figure 7.1 shows a DMAC block diagram.
Internal IMIA0
interrupts IMIA1
IMIA2
ADI
TXI0
RXI0
DREQ
0
DREQ
1
TEND
0
TEND
1
Interrupt DEND0A
signals DEND0B
DEND1A
DEND1B
Data buffer
Legend
DTCR: Data transfer control register
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
184
Internal address bus
Channel
Control logic
DTCR0A
DTCR0B
DTCR1A
DTCR1B
Channel
Internal data bus
Figure 7.1 Block Diagram of DMAC
Arithmetic-logic unit
Channel
0A
0
Channel
0B
Channel
1A
1
Channel
1B
Address buffer
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B