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Table 6.3
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR WCRH/WCRL
ABWn
ASTn
Wn1
0
0
—
1
0
1
1
0
—
1
0
1
6.3.3
Memory Interfaces
The H8/3006 and H8/3007 memory interfaces comprise a basic bus interface that allows direct
connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of
DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can
be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, and area 0 for which the burst
ROM interface is designated functions as burst ROM space.
6.3.4
Chip Select Signals
For each of areas 0 to 7, the H8/3006 and H8/3007 can output a chip select signal (CS
goes low when the corresponding area is selected. Figure 6.4 shows the output timing of a CSn
signal.
Output of CS
to CS
0
(DDR) of the corresponding port.
A reset leaves pin CS
select signals CS
to CS
1
I/O Ports.
130
Bus Specifications (Basic Bus Interface)
Wn0
Bus Width
—
16
0
1
0
1
—
8
0
1
0
1
: Output of CS
to CS
3
0
in the output state and pins CS
0
, the corresponding DDR bits must be set to 1. For details, see section 8,
3
Access States
2
3
2
3
is enabled or disabled in the data direction register
3
to CS
in the input state. To output chip
1
3
Program Wait States
0
0
1
2
3
0
0
1
2
3
to CS
) that
0
7
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